JP5975992B2 - 異なる閾値電圧を備えたｃｍｏｓトランジスタ製造 - Google Patents

異なる閾値電圧を備えたｃｍｏｓトランジスタ製造 Download PDF

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JP5975992B2
JP5975992B2 JP2013524959A JP2013524959A JP5975992B2 JP 5975992 B2 JP5975992 B2 JP 5975992B2 JP 2013524959 A JP2013524959 A JP 2013524959A JP 2013524959 A JP2013524959 A JP 2013524959A JP 5975992 B2 JP5975992 B2 JP 5975992B2
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logic
transistor
nmos transistor
pmos transistor
pmos
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JP2013537718A5 (enExample
JP2013537718A (ja
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シオン ワイゼ
シオン ワイゼ
シー ボールドウィン グレッグ
シー ボールドウィン グレッグ
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日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP2013524959A 2010-08-17 2011-08-17 異なる閾値電圧を備えたｃｍｏｓトランジスタ製造 Active JP5975992B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/857,954 US8377772B2 (en) 2010-08-17 2010-08-17 CMOS integration method for optimal IO transistor VT
US12/857,954 2010-08-17
PCT/US2011/048072 WO2012024391A2 (en) 2010-08-17 2011-08-17 Cmos transistor fabrication with different threshold voltages

Publications (3)

Publication Number Publication Date
JP2013537718A JP2013537718A (ja) 2013-10-03
JP2013537718A5 JP2013537718A5 (enExample) 2014-08-28
JP5975992B2 true JP5975992B2 (ja) 2016-08-23

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ID=45594389

Family Applications (1)

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JP2013524959A Active JP5975992B2 (ja) 2010-08-17 2011-08-17 異なる閾値電圧を備えたｃｍｏｓトランジスタ製造

Country Status (4)

Country Link
US (1) US8377772B2 (enExample)
JP (1) JP5975992B2 (enExample)
CN (1) CN103026485B (enExample)
WO (1) WO2012024391A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252147B2 (en) 2013-08-05 2016-02-02 Qualcomm Incorporated Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip
CN104167391A (zh) 2014-08-11 2014-11-26 矽力杰半导体技术(杭州)有限公司 Cmos结构的制造方法
CN108807281B (zh) * 2018-06-28 2020-09-01 上海华虹宏力半导体制造有限公司 半导体器件及其形成方法
TWI818928B (zh) * 2018-11-02 2023-10-21 聯華電子股份有限公司 一種製作半導體元件的方法
CN112201656A (zh) * 2020-12-02 2021-01-08 晶芯成(北京)科技有限公司 Cmos集成器件的形成方法

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IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
US5182719A (en) * 1988-06-09 1993-01-26 Hitachi, Ltd. Method of fabricating a second semiconductor integrated circuit device from a first semiconductor integrated circuit device
US5407849A (en) * 1992-06-23 1995-04-18 Imp, Inc. CMOS process and circuit including zero threshold transistors
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JP3101515B2 (ja) * 1995-01-20 2000-10-23 三洋電機株式会社 Ｃｍｏｓ半導体装置の製造方法
TW434834B (en) * 1996-06-29 2001-05-16 Hyundai Electronics Ind Method of manufacturing a complementary metal-oxide semiconductor device
KR100220252B1 (ko) * 1996-12-28 1999-09-15 김영환 반도체 소자의 제조방법
US6137144A (en) * 1998-04-08 2000-10-24 Texas Instruments Incorporated On-chip ESD protection in dual voltage CMOS
EP1005079B1 (en) * 1998-11-26 2012-12-26 STMicroelectronics Srl Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
KR100324931B1 (ko) * 1999-01-22 2002-02-28 박종섭 반도체장치 및 그의 제조방법
JP4501183B2 (ja) * 1999-09-14 2010-07-14 株式会社デンソー 半導体装置の製造方法
JP3324588B2 (ja) * 1999-12-22 2002-09-17 日本電気株式会社 半導体装置及びその製造方法
JP2001291779A (ja) * 2000-04-05 2001-10-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6329218B1 (en) * 2000-06-08 2001-12-11 United Microelectronics Corp. Method for forming a CMOS sensor with high S/N
JP2003051552A (ja) * 2001-08-03 2003-02-21 Hitachi Ltd 半導体集積回路装置の製造方法
US6713334B2 (en) * 2001-08-22 2004-03-30 Texas Instruments Incorporated Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask
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JP2003249570A (ja) * 2002-02-26 2003-09-05 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
AU2003236078A1 (en) * 2003-04-10 2004-11-04 Fujitsu Limited Semiconductor device and its manufacturing method
KR100493061B1 (ko) * 2003-06-20 2005-06-02 삼성전자주식회사 비휘발성 메모리가 내장된 단일 칩 데이터 처리 장치
JP2010073739A (ja) * 2008-09-16 2010-04-02 Ricoh Co Ltd 半導体装置
KR101525498B1 (ko) * 2008-12-04 2015-06-03 삼성전자주식회사 반도체 장치 및 그의 제조 방법

Also Published As

Publication number Publication date
CN103026485B (zh) 2016-04-27
CN103026485A (zh) 2013-04-03
US20120045874A1 (en) 2012-02-23
WO2012024391A3 (en) 2012-08-09
US8377772B2 (en) 2013-02-19
JP2013537718A (ja) 2013-10-03
WO2012024391A2 (en) 2012-02-23

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