CN103026485B - 具有不同阈值电压的cmos晶体管制作 - Google Patents

具有不同阈值电压的cmos晶体管制作 Download PDF

Info

Publication number
CN103026485B
CN103026485B CN201180036518.5A CN201180036518A CN103026485B CN 103026485 B CN103026485 B CN 103026485B CN 201180036518 A CN201180036518 A CN 201180036518A CN 103026485 B CN103026485 B CN 103026485B
Authority
CN
China
Prior art keywords
transistor
logic
transistors
onmos
opmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180036518.5A
Other languages
English (en)
Chinese (zh)
Other versions
CN103026485A (zh
Inventor
熊伟泽
格雷格·C·鲍德温
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103026485A publication Critical patent/CN103026485A/zh
Application granted granted Critical
Publication of CN103026485B publication Critical patent/CN103026485B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
CN201180036518.5A 2010-08-17 2011-08-17 具有不同阈值电压的cmos晶体管制作 Active CN103026485B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/857,954 2010-08-17
US12/857,954 US8377772B2 (en) 2010-08-17 2010-08-17 CMOS integration method for optimal IO transistor VT
PCT/US2011/048072 WO2012024391A2 (en) 2010-08-17 2011-08-17 Cmos transistor fabrication with different threshold voltages

Publications (2)

Publication Number Publication Date
CN103026485A CN103026485A (zh) 2013-04-03
CN103026485B true CN103026485B (zh) 2016-04-27

Family

ID=45594389

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180036518.5A Active CN103026485B (zh) 2010-08-17 2011-08-17 具有不同阈值电压的cmos晶体管制作

Country Status (4)

Country Link
US (1) US8377772B2 (enExample)
JP (1) JP5975992B2 (enExample)
CN (1) CN103026485B (enExample)
WO (1) WO2012024391A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252147B2 (en) 2013-08-05 2016-02-02 Qualcomm Incorporated Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip
CN104167391A (zh) 2014-08-11 2014-11-26 矽力杰半导体技术(杭州)有限公司 Cmos结构的制造方法
CN108807281B (zh) * 2018-06-28 2020-09-01 上海华虹宏力半导体制造有限公司 半导体器件及其形成方法
TWI818928B (zh) * 2018-11-02 2023-10-21 聯華電子股份有限公司 一種製作半導體元件的方法
CN112201656A (zh) * 2020-12-02 2021-01-08 晶芯成(北京)科技有限公司 Cmos集成器件的形成方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143594A (en) * 1998-04-08 2000-11-07 Texas Instruments Incorporated On-chip ESD protection in dual voltage CMOS
TW490808B (en) * 1999-12-22 2002-06-11 Nippon Electric Co Semiconductor device and method of fabricating the same
US20020140047A1 (en) * 1998-11-26 2002-10-03 Stmicroelectronics S.R.I. Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
US5182719A (en) * 1988-06-09 1993-01-26 Hitachi, Ltd. Method of fabricating a second semiconductor integrated circuit device from a first semiconductor integrated circuit device
US5407849A (en) * 1992-06-23 1995-04-18 Imp, Inc. CMOS process and circuit including zero threshold transistors
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JP3101515B2 (ja) * 1995-01-20 2000-10-23 三洋電機株式会社 Ｃｍｏｓ半導体装置の製造方法
TW434834B (en) * 1996-06-29 2001-05-16 Hyundai Electronics Ind Method of manufacturing a complementary metal-oxide semiconductor device
KR100220252B1 (ko) * 1996-12-28 1999-09-15 김영환 반도체 소자의 제조방법
KR100324931B1 (ko) * 1999-01-22 2002-02-28 박종섭 반도체장치 및 그의 제조방법
JP4501183B2 (ja) * 1999-09-14 2010-07-14 株式会社デンソー 半導体装置の製造方法
JP2001291779A (ja) * 2000-04-05 2001-10-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6329218B1 (en) * 2000-06-08 2001-12-11 United Microelectronics Corp. Method for forming a CMOS sensor with high S/N
JP2003051552A (ja) * 2001-08-03 2003-02-21 Hitachi Ltd 半導体集積回路装置の製造方法
US6713334B2 (en) * 2001-08-22 2004-03-30 Texas Instruments Incorporated Fabricating dual voltage CMOSFETs using additional implant into core at high voltage mask
US6861341B2 (en) * 2002-02-22 2005-03-01 Xerox Corporation Systems and methods for integration of heterogeneous circuit devices
JP2003249570A (ja) * 2002-02-26 2003-09-05 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US6855985B2 (en) * 2002-09-29 2005-02-15 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology
JP4942009B2 (ja) * 2003-04-10 2012-05-30 富士通セミコンダクター株式会社 半導体装置
KR100493061B1 (ko) * 2003-06-20 2005-06-02 삼성전자주식회사 비휘발성 메모리가 내장된 단일 칩 데이터 처리 장치
JP2010073739A (ja) * 2008-09-16 2010-04-02 Ricoh Co Ltd 半導体装置
KR101525498B1 (ko) * 2008-12-04 2015-06-03 삼성전자주식회사 반도체 장치 및 그의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6143594A (en) * 1998-04-08 2000-11-07 Texas Instruments Incorporated On-chip ESD protection in dual voltage CMOS
US20020140047A1 (en) * 1998-11-26 2002-10-03 Stmicroelectronics S.R.I. Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
TW490808B (en) * 1999-12-22 2002-06-11 Nippon Electric Co Semiconductor device and method of fabricating the same

Also Published As

Publication number Publication date
CN103026485A (zh) 2013-04-03
US8377772B2 (en) 2013-02-19
US20120045874A1 (en) 2012-02-23
WO2012024391A3 (en) 2012-08-09
WO2012024391A2 (en) 2012-02-23
JP2013537718A (ja) 2013-10-03
JP5975992B2 (ja) 2016-08-23

Similar Documents

Publication Publication Date Title
US6514810B1 (en) Buried channel PMOS transistor in dual gate CMOS with reduced masking steps
CN100565841C (zh) 半导体装置及其制造方法
US6548874B1 (en) Higher voltage transistors for sub micron CMOS processes
EP1191577A1 (en) MOSFET transistor
EP1026738B1 (en) Novel mixed voltage CMOS process for high reliability and high performance core and I/O transistors with reduced mask steps
CN103026485B (zh) 具有不同阈值电压的cmos晶体管制作
CN107068682A (zh) 半导体集成电路器件及其制造方法
US20030127694A1 (en) Higher voltage transistors for sub micron CMOS processes
US6583013B1 (en) Method for forming a mixed voltage circuit having complementary devices
JPH11330267A (ja) 高電圧からドレンエクステンダ注入を除くことによる二重供給電圧の組込み
JP4383929B2 (ja) フラッシュメモリ素子の高電圧トランジスタの製造方法
US7052966B2 (en) Deep N wells in triple well structures and method for fabricating same
US9865507B2 (en) Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
US9337106B2 (en) Implant profiling with resist
US7560779B2 (en) Method for forming a mixed voltage circuit having complementary devices
CN102956494B (zh) 半导体装置及其制造方法
US20020052083A1 (en) Cost effective split-gate process that can independently optimize the low voltage(LV) and high voltage (HV) transistors to minimize reverse short channel effects
US7704814B2 (en) Method for manufacturing MOS transistor of semiconductor device
JP3430102B2 (ja) 半導体装置の製造方法
JP2003332461A (ja) 三重ウェル構造を持つ半導体素子の製造方法
CN109727906B (zh) N型半导体元器件的浅槽隔离结构的处理方法
KR100523606B1 (ko) 반도체 제조 장치에서의 소자 분리 방법
JP2008539592A (ja) ブロッキング特性の異なるゲート絶縁膜を備えた半導体デバイス
US20080023776A1 (en) Metal oxide semiconductor device with improved threshold voltage and drain junction breakdown voltage and method for fabricating same
CN104616995B (zh) 耗尽型mos管的制造方法及结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant