WO2012024391A2 - Cmos transistor fabrication with different threshold voltages - Google Patents

Cmos transistor fabrication with different threshold voltages Download PDF

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Publication number
WO2012024391A2
WO2012024391A2 PCT/US2011/048072 US2011048072W WO2012024391A2 WO 2012024391 A2 WO2012024391 A2 WO 2012024391A2 US 2011048072 W US2011048072 W US 2011048072W WO 2012024391 A2 WO2012024391 A2 WO 2012024391A2
Authority
WO
WIPO (PCT)
Prior art keywords
logic
pmos transistor
nmos transistor
transistor region
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/048072
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English (en)
French (fr)
Other versions
WO2012024391A3 (en
Inventor
Weize Xiong
Greg C. Baldwin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
Original Assignee
Texas Instruments Japan Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to JP2013524959A priority Critical patent/JP5975992B2/ja
Priority to CN201180036518.5A priority patent/CN103026485B/zh
Publication of WO2012024391A2 publication Critical patent/WO2012024391A2/en
Publication of WO2012024391A3 publication Critical patent/WO2012024391A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • This relates to methods of semiconductor device fabrication including setting threshold voltages (Vr) for dual voltage CMOS transistor devices.
  • CMOS complementary metal-oxide semiconductor
  • the low supply voltage transistors typically logic or core transistors, are used internally to the chip.
  • Logic transistors are usually in the central part of the die or chip (hereafter "chip") and are optimized for high packing density and performance. Logic transistors are smaller and have a thin gate oxide layer to maximize speed at low voltages.
  • the high supply voltage transistors are usually used to communicate to external devices/chips so are designated as input/output (I/O) transistors. These transistors are larger, and have a thicker gate oxide layer for reliable high voltage operation.
  • I/O transistors are larger, and have a thicker gate oxide layer for reliable high voltage operation.
  • the use of two different supply voltages requires two different gate oxide thicknesses. For example, I O transistors can often have a gate oxide thickness 2 to 4 times thicker than logic transistors.
  • FIGS. 2A-2D depict conventional methods for forming a semiconductor device having isolated regions of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor.
  • a blanket P-type substrate implant 40 is performed to set a threshold voltage (Vr) of the I/O NMOS transistor.
  • the conventional I/O PMOS transistor, the logic PMOS transistor, and the I/O NMOS transistor are covered by a photoresist 50, exposing only the logic NMOS region to form a DNWELL at 55 in the logic NMOS transistor.
  • FIG. 2C when standard NWELL pattern is performed (see 65) to form the logic PMOS transistor, the I/O PMOS transistor is also exposed to the NWELL implant by a photoresist 60.
  • FIG. 2D when the PWELL pattern is performed (see 75) in the
  • the I/O NMOS transistor is also exposed to the PWELL implant. This exposure of the I/O NMOS transistor can affect the threshold voltage of the I/O NMOS transistor that are previously set in FIG. 2A.
  • a described example method of fabricating a CMOS transistor includes providing a semiconductor substrate that includes isolated regions of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor.
  • a threshold voltage (V T ) of the I/O NMOS transistor can then be set by implanting a P-type dopant in the I/O NMOS transistor; and a threshold voltage (V T ) of the I/O PMOS transistor can be set by implanting an N-type dopant in the I/O PMOS transistor.
  • an NWELL region can then be formed in the logic PMOS transistor and a PWELL region can then be formed in the logic NMOS transistor.
  • a described example CMOS transistor can be formed in a semiconductor substrate including isolated regions of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor.
  • a blanket implanting of a P-type dopant can be performed in each isolated region of the semiconductor substrate to set a threshold voltage (V T ) of the I/O NMOS transistor.
  • a threshold voltage (V T ) of the I/O PMOS transistor can be set by implanting an N-type dopant in the I/O PMOS transistor with both the logic PMOS transistor and the I/O NMOS transistor masked.
  • the I/O NMOS transistor with the set V T , the I/O PMOS transistor with the set V T , and the logic NMOS transistor can then be masked to form an NWELL region in the logic PMOS transistor. This is followed by masking the I O NMOS transistor with the set V T , the I/O PMOS transistor with the set V T , and the logic PMOS transistor to form a PWELL region in the logic NMOS transistor.
  • a described example CMOS transistor can be formed in a semiconductor substrate that includes isolated regions of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor.
  • a blanket implanting of boron can be performed in each isolated region of the semiconductor substrate to set a threshold voltage (V T ) of the I/O NMOS transistor.
  • the set V T of the I/O NMOS transistor can be optionally adjusted by a surface boron implant.
  • a deep NWELL can be formed in both the logic NMOS transistor and the I/O PMOS transistor in order to set a threshold voltage (V T ) of the I/O PMOS transistor.
  • the set V T of the I/O PMOS transistor can be optionally adjusted by a surface N-type implant.
  • An NWELL region can be formed in the logic PMOS transistor by masking the I/O NMOS transistor with the set V T , the I/O PMOS transistor with the set V T , and the logic NMOS transistor.
  • a PWELL region can be formed in the logic NMOS transistor by masking the I/O NMOS transistor with the set V T , the I/O PMOS transistor with the set V T , and the logic PMOS transistor.
  • FIGS. 1A-1D depict an example semiconductor device at various stages of fabrication.
  • FIGS. 2A-2D depict a conventional semiconductor device at fabrication stages corresponding to those of FIGS. 1A-1D.
  • Described example embodiments illustrate methods for fabricating dual supply voltage CMOS devices to obtain a desired I/O transistor threshold voltage.
  • the dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor.
  • the fabrication of the dual supply voltage CMOS devices can include first setting and/or adjusting the threshold voltage (V T ) of each of the I/O NMOS and I/O PMOS transistors to a desired level.
  • Logic NMOS and logic PMOS transistors can then be formed with I/O NMOS and PMOS transistors masked without affecting the set/adjusted V T of the I/O transistors.
  • FIGS. 1A-1D depict an example semiconductor device at various stages of fabrication.
  • FIGS. 2A-2D depict a semiconductor device at corresponding stages of a conventional fabrication process.
  • the example fabrication process begins with the formation of isolation structures 120 in a semiconductor substrate 110, for example, a silicon substrate.
  • the isolation structures 120 may be LOCOS (local oxidation of silicon) oxidations, shallow trench isolation (STI), or other isolation structures.
  • the substrate 110 in FIG. 1A may include isolated regions for ones or more of a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor.
  • a thin disposable oxide layer 130 may be grown to protect the example silicon surface of the substrate 110 during subsequent implants to form the disclosed CMOS device.
  • an I/O NMOS V T implant is performed in the I/O NMOS transistor to set the threshold voltage (V T ) of the I/O NMOS transistor.
  • a blanket P-type implant for example, a blanket PWELL Boron implant, is performed in each isolated region of the semiconductor substrate 110.
  • the example blanket P-type implant may also be used to isolate the subsequently formed NWELL of I/O NMOS transistor from NWELL of the logic NMOS transistor.
  • the NWELL formation in the I/O NMOS transistor and the logic NMOS transistor can use conventional procedures as known to one of ordinary skill in the art.
  • the blanket P-type substrate implant 140 may be performed in both cases of FIG. 1A and FIG. 2A, the implant dose, energy, and/or depth of the disclosed device (see FIG. 1A) can be different from the conventional device (see FIG. 2A).
  • the blanket P-type substrate implant 140 in FIG. 1A for the disclosed I/O NMOS VT can have an implant dose of about
  • lel2 atoms/cm to about lel3 atoms/cm at an energy of about 300 KeV to about 500 KeV Boron to set the VT of the disclosed I/O NMOS transistor at or close to a desired VT level.
  • an additional surface P-type implant may be performed to adjust the V T of the I/O NMOS transistor set by the blanket P-type implant at 140.
  • the threshold voltage (VT) of the I/O NMOS transistor can be set and/or adjusted to a desired level ranging from about 0.2V to about 1.0V, or from about 0.2V to about 0.7V or from about 0.3 to about 1.0V.
  • the logic PMOS and/or I/O PMOS transistors can also receive the P-type implants, these P-type implants can be compensated by subsequent N-type implants, for example, as shown in FIG. IB and FIG. 1C.
  • the threshold voltage (VT) of the I/O PMOS transistor can be set and/or adjusted, for example, by an I/O PMOS VT implant in the I/O PMOS transistor.
  • a photoresist 150 is deposited and patterned to cover the logic PMOS transistor and the I/O NMOS transistor, and to expose the I/O PMOS transistor and the logic NMOS transistor.
  • An N-type implant is then applied at 155 to the exposed regions of the I O PMOS transistor and the logic NMOS transistor.
  • a deep NWELL i.e., DNWELL
  • the deep NWELL implant can be a light compensation N-type implant, which can in turn be compensated by following heavy P-type well/channel stop implants in the logic NMOS transistor.
  • the photoresist 150 can also open the DNWELL formation to the I/O PMOS transistor. This differs from the corresponding conventional manufacturing step shown in FIG. 2B, where conventional I/O PMOS transistor as well as the logic PMOS transistor and the I/O NMOS transistor are covered by a photoresist 50, exposing only the logic NMOS region to form the DNWELL in the logic NMOS transistor.
  • the deep NWELL implant may be an I/O PMOS V T implant to set the V T of the I O PMOS transistor to a desired V T level.
  • the deep NWELL implant can be performed with a dose ranging from about lel3 atoms/cm to about
  • the DNWELL implant can be selected to be sufficient for setting the I/O PMOS transistor to the desired V T - Meanwhile, this DNEWLL implant can be selected to be light enough to have no or little impact on the threshold voltage of other transistors in the chip including the I/O NMOS transistor, the logic PMOS transistor, and/or the logic NMOS transistor.
  • the implant dose used for forming the DNWELL in the I/O PMOS transistor and the logic NMOS transistor can be significantly lower than the implant dose for subsequently forming PWELL and/or P-channel (see FIG. ID) in the logic NMOS transistor.
  • the subsequent PWELL formation in the logic NMOS substrate can use an implant dose of about 5el2 atoms/cm or greater.
  • an additional surface N-type implant can be performed to adjust the V T of the I/O PMOS transistor set by the DNWELL implant in FIG. IB.
  • the threshold voltage (V T ) of the I/O PMOS transistor can be set and/or adjusted to a desired level ranging from about -0.2V to about -1.0V, or from -0.2V to about - 0.7V, or from -0.3V to about - 1.0V.
  • the threshold voltage V T for each of the I/O NMOS transistor and the I/O POMS transistor can be set and/or adjusted to a desirable level without using any additional masks.
  • the I/O NMOS transistor and the I/O POMS transistor each with suitable V T can then be masked during the following formation of the disclosed dual supply voltage CMOS device.
  • formation and V T control of logic transistors can be separated from I/O transistors.
  • channels and wells can be formed in the logic NMOS and PMOS transistors by conventional masking and implanting processes, but with the I/O transistors masked, as exemplarily shown in FIGS. 1C-1D.
  • another photoresist 160 can be deposited and patterned, for example, to cover the I/O NMOS transistor, the I O PMOS transistor, and the logic NMOS transistor.
  • the photoresist 160 can expose the logic PMOS transistor to perform a standard NWELL pattern in the P-region of the logic PMOS transistor.
  • NWELL pattern is performed to form the logic PMOS transistor, the I/O PMOS transistor is also exposed to the NWELL implant by a photoresist 60.
  • a third photoresist 170 can be deposited and patterned, for example, to cover the I/O NMOS transistor, the I/O PMOS transistor, and the logic PMOS transistor.
  • the photoresist 170 can expose the logic NMOS to perform a standard PWELL pattern in the deep NWELL region of the logic NMOS transistor.
  • the I/O NMOS transistor is also exposed to the PWELL implant. This exposure of the I/O NMOS transistor can affect the threshold voltage of the I/O NMOS transistor that is already set or adjusted.
  • CMOS device to complete the formation of the disclosed dual voltage supply CMOS device, a portion associated with logic transistors of the oxide layer 130 can then be etched off. A gate dielectric, either oxide or nitrided oxide, can be grown. A polysilicon or metal gate can then be formed. Generally, all gates can be a single layer of polysilicon, although differently doped layers can be used to form the PMOS and NMOS gates.
  • the formation of transistors can be continued to include channel implants, sidewall spacer formation, source/drain implants, silicide formation on the gate and on the source/drain areas, deposition of a dielectric and/or metallization, etc., as known to one of ordinary skill in the art.
  • the N-type implants or NWELL formation can use various dopants including, for example, phosphorous, silicon, germanium, selenium, sulfur and/or tellurium, while the P-type implants or PWELL formation can use dopants including, for example, boron, beryllium, strontium, barium, zinc, and/or magnesium. Other dopants can also be used.
  • the location and/or formation order of the N-type and P-type regions can be reversed for the disclosed CMOS devices.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
PCT/US2011/048072 2010-08-17 2011-08-17 Cmos transistor fabrication with different threshold voltages Ceased WO2012024391A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2013524959A JP5975992B2 (ja) 2010-08-17 2011-08-17 異なる閾値電圧を備えたｃｍｏｓトランジスタ製造
CN201180036518.5A CN103026485B (zh) 2010-08-17 2011-08-17 具有不同阈值电压的cmos晶体管制作

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/857,954 US8377772B2 (en) 2010-08-17 2010-08-17 CMOS integration method for optimal IO transistor VT
US12/857,954 2010-08-17

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WO2012024391A2 true WO2012024391A2 (en) 2012-02-23
WO2012024391A3 WO2012024391A3 (en) 2012-08-09

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CN108807281B (zh) * 2018-06-28 2020-09-01 上海华虹宏力半导体制造有限公司 半导体器件及其形成方法
TWI818928B (zh) * 2018-11-02 2023-10-21 聯華電子股份有限公司 一種製作半導體元件的方法
CN112201656A (zh) * 2020-12-02 2021-01-08 晶芯成(北京)科技有限公司 Cmos集成器件的形成方法

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Also Published As

Publication number Publication date
CN103026485B (zh) 2016-04-27
CN103026485A (zh) 2013-04-03
US20120045874A1 (en) 2012-02-23
WO2012024391A3 (en) 2012-08-09
US8377772B2 (en) 2013-02-19
JP2013537718A (ja) 2013-10-03
JP5975992B2 (ja) 2016-08-23

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