JP2013537718A5 - - Google Patents

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Publication number
JP2013537718A5
JP2013537718A5 JP2013524959A JP2013524959A JP2013537718A5 JP 2013537718 A5 JP2013537718 A5 JP 2013537718A5 JP 2013524959 A JP2013524959 A JP 2013524959A JP 2013524959 A JP2013524959 A JP 2013524959A JP 2013537718 A5 JP2013537718 A5 JP 2013537718A5
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JP
Japan
Prior art keywords
transistor
logic
nmos transistor
pmos transistor
pmos
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JP2013524959A
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English (en)
Japanese (ja)
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JP2013537718A (ja
JP5975992B2 (ja
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Priority claimed from US12/857,954 external-priority patent/US8377772B2/en
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Publication of JP2013537718A5 publication Critical patent/JP2013537718A5/ja
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Publication of JP5975992B2 publication Critical patent/JP5975992B2/ja
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JP2013524959A 2010-08-17 2011-08-17 異なる閾値電圧を備えたｃｍｏｓトランジスタ製造 Active JP5975992B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/857,954 US8377772B2 (en) 2010-08-17 2010-08-17 CMOS integration method for optimal IO transistor VT
US12/857,954 2010-08-17
PCT/US2011/048072 WO2012024391A2 (en) 2010-08-17 2011-08-17 Cmos transistor fabrication with different threshold voltages

Publications (3)

Publication Number Publication Date
JP2013537718A JP2013537718A (ja) 2013-10-03
JP2013537718A5 true JP2013537718A5 (enExample) 2014-08-28
JP5975992B2 JP5975992B2 (ja) 2016-08-23

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Family Applications (1)

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JP2013524959A Active JP5975992B2 (ja) 2010-08-17 2011-08-17 異なる閾値電圧を備えたｃｍｏｓトランジスタ製造

Country Status (4)

Country Link
US (1) US8377772B2 (enExample)
JP (1) JP5975992B2 (enExample)
CN (1) CN103026485B (enExample)
WO (1) WO2012024391A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252147B2 (en) 2013-08-05 2016-02-02 Qualcomm Incorporated Methods and apparatuses for forming multiple radio frequency (RF) components associated with different RF bands on a chip
CN104167391A (zh) 2014-08-11 2014-11-26 矽力杰半导体技术(杭州)有限公司 Cmos结构的制造方法
CN108807281B (zh) * 2018-06-28 2020-09-01 上海华虹宏力半导体制造有限公司 半导体器件及其形成方法
TWI818928B (zh) * 2018-11-02 2023-10-21 聯華電子股份有限公司 一種製作半導體元件的方法
CN112201656A (zh) * 2020-12-02 2021-01-08 晶芯成(北京)科技有限公司 Cmos集成器件的形成方法

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IT1225873B (it) * 1987-07-31 1990-12-07 Sgs Microelettrica S P A Catan Procedimento per la fabbricazione di celle di memoria eprom cmos con riduzione del numero di fasi di mascheratura.
US5182719A (en) * 1988-06-09 1993-01-26 Hitachi, Ltd. Method of fabricating a second semiconductor integrated circuit device from a first semiconductor integrated circuit device
US5407849A (en) * 1992-06-23 1995-04-18 Imp, Inc. CMOS process and circuit including zero threshold transistors
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JP3101515B2 (ja) * 1995-01-20 2000-10-23 三洋電機株式会社 Ｃｍｏｓ半導体装置の製造方法
TW434834B (en) * 1996-06-29 2001-05-16 Hyundai Electronics Ind Method of manufacturing a complementary metal-oxide semiconductor device
KR100220252B1 (ko) * 1996-12-28 1999-09-15 김영환 반도체 소자의 제조방법
US6137144A (en) * 1998-04-08 2000-10-24 Texas Instruments Incorporated On-chip ESD protection in dual voltage CMOS
EP1005079B1 (en) * 1998-11-26 2012-12-26 STMicroelectronics Srl Process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry
KR100324931B1 (ko) * 1999-01-22 2002-02-28 박종섭 반도체장치 및 그의 제조방법
JP4501183B2 (ja) * 1999-09-14 2010-07-14 株式会社デンソー 半導体装置の製造方法
JP3324588B2 (ja) * 1999-12-22 2002-09-17 日本電気株式会社 半導体装置及びその製造方法
JP2001291779A (ja) * 2000-04-05 2001-10-19 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6329218B1 (en) * 2000-06-08 2001-12-11 United Microelectronics Corp. Method for forming a CMOS sensor with high S/N
JP2003051552A (ja) * 2001-08-03 2003-02-21 Hitachi Ltd 半導体集積回路装置の製造方法
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KR100493061B1 (ko) * 2003-06-20 2005-06-02 삼성전자주식회사 비휘발성 메모리가 내장된 단일 칩 데이터 처리 장치
JP2010073739A (ja) * 2008-09-16 2010-04-02 Ricoh Co Ltd 半導体装置
KR101525498B1 (ko) * 2008-12-04 2015-06-03 삼성전자주식회사 반도체 장치 및 그의 제조 방법

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