JP5901771B2 - メモリリフレッシュ法および装置 - Google Patents
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- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
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- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
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- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G06F11/0751—Error or fault detection not based on redundancy
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- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
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Description
本出願は、2011年8月31日に出願された米国特許出願第13/222,282号に基づく優先権の利益を主張するものであり、それが参照によりその全体において本願に組み込まれる。
Claims (6)
- 其々が複数のページからなる複数のブロックを備えたメモリデバイスの制御方法であって、
前記複数のブロックのうち、第1のブロックに含まれる第1のページを指定する読み取りコマンドを発行することと、
前記読み取りコマンドが前記第1のブロックに対する所定回数以上の読み取りコマンドか否かを判定することと、
前記読み取りコマンドが前記第1のブロックに対する所定回数以上の読み取りコマンドであると判定された場合に、前記第1のブロック内において特定の一部のページのデータを読み取って、前記一部のページのデータに閾値を超えた数の誤りがあるか否かを判定することと、
前記誤りの数が前記閾値を超える場合、前記第1のブロックに対してリフレッシュ制御を行うための印を付けることと、
を含むメモリデバイスの制御方法。 - 前記特定の一部のページは2以上のページからなり、前記2以上のページのいずれか一つのページに前記閾値を超えた数の誤りがあった場合に、前記一部のページのデータに前記閾値を超えた数の誤りがあると判定することを特徴とする請求項1に記載のメモリデバイスの制御方法。
- 前記特定の一部のページを含む前記複数のページのデータは其々誤り訂正符号を用いて読み出されるものであって、前記誤り訂正符号により訂正可能となるエラーの数は、前記閾値よりも大きいことを特徴とする請求項2に記載のメモリデバイスの制御方法。
- 前記印の付けられた前記第1のブロックに含まれる前記複数のページのデータをコピーすることと、
コピーされた前記複数のページのデータを再プログラムすることと、
を更に含む請求項1に記載のメモリデバイスの制御方法。 - 電源投入時に、前記複数のブロックに対して前記印の有無を判定することを更に含み、
前記印の付けられた前記第1のブロックに含まれる前記複数のページのデータをコピーすること及び前記コピーされた前記複数のページのデータを再プログラムすることが共に前記電源投入時に行われることを特徴とする請求項4に記載のメモリデバイスの制御方法。 - 前記コピーされた前記複数のページのデータを再プログラムした後に、前記第1のブロックに付けられた前記印を取り除くことを更に含む請求項4に記載のメモリデバイスの制御方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/222,282 | 2011-08-31 | ||
US13/222,282 US9176800B2 (en) | 2011-08-31 | 2011-08-31 | Memory refresh methods and apparatuses |
PCT/US2012/052687 WO2013033107A2 (en) | 2011-08-31 | 2012-08-28 | Memory refresh methods and apparatuses |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2014525634A JP2014525634A (ja) | 2014-09-29 |
JP2014525634A5 JP2014525634A5 (ja) | 2015-09-17 |
JP5901771B2 true JP5901771B2 (ja) | 2016-04-13 |
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Application Number | Title | Priority Date | Filing Date |
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JP2014528524A Active JP5901771B2 (ja) | 2011-08-31 | 2012-08-28 | メモリリフレッシュ法および装置 |
Country Status (6)
Country | Link |
---|---|
US (3) | US9176800B2 (ja) |
EP (1) | EP2751809B1 (ja) |
JP (1) | JP5901771B2 (ja) |
KR (1) | KR102000307B1 (ja) |
CN (2) | CN103843069B (ja) |
WO (1) | WO2013033107A2 (ja) |
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US20160019974A1 (en) | 2016-01-21 |
EP2751809B1 (en) | 2020-04-01 |
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US9176800B2 (en) | 2015-11-03 |
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US10109357B2 (en) | 2018-10-23 |
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EP2751809A4 (en) | 2014-12-31 |
US20170352429A1 (en) | 2017-12-07 |
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CN107402832B (zh) | 2020-11-27 |
WO2013033107A2 (en) | 2013-03-07 |
KR20140059821A (ko) | 2014-05-16 |
US20130055046A1 (en) | 2013-02-28 |
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