JP5885952B2 - 積層状の相互接続ヒートシンク - Google Patents

積層状の相互接続ヒートシンク Download PDF

Info

Publication number
JP5885952B2
JP5885952B2 JP2011158573A JP2011158573A JP5885952B2 JP 5885952 B2 JP5885952 B2 JP 5885952B2 JP 2011158573 A JP2011158573 A JP 2011158573A JP 2011158573 A JP2011158573 A JP 2011158573A JP 5885952 B2 JP5885952 B2 JP 5885952B2
Authority
JP
Japan
Prior art keywords
substrate
heat spreader
heat
core
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2011158573A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012028771A (ja
JP2012028771A5 (enExample
Inventor
エー． バッチマン マーク
エー． バッチマン マーク
ダブリュ． オーゼンバッハ ジョン
ダブリュ． オーゼンバッハ ジョン
エム．マーチャント サイレッシュ
エム．マーチャント サイレッシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Publication of JP2012028771A publication Critical patent/JP2012028771A/ja
Publication of JP2012028771A5 publication Critical patent/JP2012028771A5/ja
Application granted granted Critical
Publication of JP5885952B2 publication Critical patent/JP5885952B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2011158573A 2010-07-20 2011-07-20 積層状の相互接続ヒートシンク Active JP5885952B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/840,016 2010-07-20
US12/840,016 US8492911B2 (en) 2010-07-20 2010-07-20 Stacked interconnect heat sink

Publications (3)

Publication Number Publication Date
JP2012028771A JP2012028771A (ja) 2012-02-09
JP2012028771A5 JP2012028771A5 (enExample) 2014-08-14
JP5885952B2 true JP5885952B2 (ja) 2016-03-16

Family

ID=44719192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011158573A Active JP5885952B2 (ja) 2010-07-20 2011-07-20 積層状の相互接続ヒートシンク

Country Status (6)

Country Link
US (3) US8492911B2 (enExample)
EP (2) EP3651194B8 (enExample)
JP (1) JP5885952B2 (enExample)
KR (1) KR101795047B1 (enExample)
CN (1) CN102339800A (enExample)
TW (1) TWI413222B (enExample)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120053675A (ko) * 2010-11-18 2012-05-29 삼성전자주식회사 반도체 패키지 및 그의 제조 방법, 및 인터포저 칩 및 그의 제조 방법
US8384215B2 (en) * 2010-12-30 2013-02-26 Industrial Technology Research Institute Wafer level molding structure
US20120299173A1 (en) * 2011-05-26 2012-11-29 Futurewei Technologies, Inc. Thermally Enhanced Stacked Package and Method
DE102011088256A1 (de) * 2011-12-12 2013-06-13 Zf Friedrichshafen Ag Multilayer-Leiterplatte sowie Anordnung mit einer solchen
US8946757B2 (en) * 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9236322B2 (en) * 2012-04-11 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for heat spreader on silicon
US9337123B2 (en) 2012-07-11 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal structure for integrated circuit package
US10269676B2 (en) * 2012-10-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced package-on-package (PoP)
US20140133105A1 (en) * 2012-11-09 2014-05-15 Nvidia Corporation Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structure
US20140225248A1 (en) * 2013-02-13 2014-08-14 Qualcomm Incorporated Power distribution and thermal solution for direct stacked integrated circuits
KR102103375B1 (ko) * 2013-06-18 2020-04-22 삼성전자주식회사 반도체 패키지
KR102057210B1 (ko) 2013-07-05 2020-01-22 에스케이하이닉스 주식회사 반도체 칩 및 이를 갖는 적층형 반도체 패키지
US9496297B2 (en) 2013-12-05 2016-11-15 Optiz, Inc. Sensor package with cooling feature and method of making same
TW201533882A (zh) * 2014-02-21 2015-09-01 南茂科技股份有限公司 覆晶堆疊封裝
US9524917B2 (en) 2014-04-23 2016-12-20 Optiz, Inc. Chip level heat dissipation using silicon
US9786633B2 (en) 2014-04-23 2017-10-10 Massachusetts Institute Of Technology Interconnect structures for fine pitch assembly of semiconductor structures and related techniques
US9356009B2 (en) * 2014-05-27 2016-05-31 Micron Technology, Inc. Interconnect structure with redundant electrical connectors and associated systems and methods
US9691746B2 (en) 2014-07-14 2017-06-27 Micron Technology, Inc. Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
US10079224B2 (en) * 2014-08-11 2018-09-18 Massachusetts Institute Of Technology Interconnect structures for assembly of semiconductor structures including at least one integrated circuit structure
TWI614860B (zh) * 2014-10-08 2018-02-11 李明芬 一種半導體引線鍵合結構及其製程
US9706668B2 (en) * 2014-10-24 2017-07-11 Samsung Electro-Mechanics Co., Ltd. Printed circuit board, electronic module and method of manufacturing the same
WO2016118210A2 (en) 2014-11-05 2016-07-28 Massachusetts Institute Of Technology Interconnect structures for assembly of multi-layer semiconductor devices
DE112014007285B4 (de) * 2014-12-26 2024-01-18 Mitsubishi Electric Corporation Halbleitermodul
US9971970B1 (en) 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
CN108281404A (zh) * 2015-04-30 2018-07-13 华为技术有限公司 一种集成电路管芯及制造方法
US9302905B1 (en) * 2015-06-15 2016-04-05 Innovative Micro Technology Method for forming a microfabricated structure
US10134972B2 (en) 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
WO2017015432A1 (en) 2015-07-23 2017-01-26 Massachusetts Institute Of Technology Superconducting integrated circuit
DE102015116807A1 (de) * 2015-10-02 2017-04-06 Infineon Technologies Austria Ag Funktionalisierte Schnittstellenstruktur
US10242968B2 (en) 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
WO2017131831A2 (en) 2015-11-05 2017-08-03 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
KR102372300B1 (ko) 2015-11-26 2022-03-08 삼성전자주식회사 스택 패키지 및 그 제조 방법
DE102016214607B4 (de) * 2016-08-05 2023-02-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Elektronisches Modul und Verfahren zu seiner Herstellung
US10381541B2 (en) 2016-10-11 2019-08-13 Massachusetts Institute Of Technology Cryogenic electronic packages and methods for fabricating cryogenic electronic packages
US9996725B2 (en) 2016-11-03 2018-06-12 Optiz, Inc. Under screen sensor assembly
US10163751B2 (en) * 2016-11-29 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Heat transfer structures and methods for IC packages
US11276667B2 (en) * 2016-12-31 2022-03-15 Intel Corporation Heat removal between top and bottom die interface
US11121301B1 (en) 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US10229864B1 (en) * 2017-09-14 2019-03-12 Northrop Grumman Systems Corporation Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias
US11004763B2 (en) 2018-12-20 2021-05-11 Northrop Grumman Systems Corporation Superconducting device with multiple thermal sinks
JP7267767B2 (ja) * 2019-02-20 2023-05-02 ローム株式会社 半導体装置および半導体装置の製造方法
CN110707055B (zh) * 2019-09-11 2021-12-28 长江存储科技有限责任公司 芯片、电子设备
US11522118B2 (en) 2020-01-09 2022-12-06 Northrop Grumman Systems Corporation Superconductor structure with normal metal connection to a resistor and method of making the same
CN113113367A (zh) * 2020-01-13 2021-07-13 华为技术有限公司 芯片、芯片的制造方法和电子设备
KR102767656B1 (ko) * 2020-03-26 2025-02-17 엘지마그나 이파워트레인 주식회사 양면 냉각형 파워 모듈
CN115461858A (zh) * 2020-08-04 2022-12-09 华为技术有限公司 多芯片堆叠封装、电子设备及制备方法
KR20240006528A (ko) 2021-05-06 2024-01-15 퀄컴 테크놀로지스, 인크. 수직 열 경로를 갖는 고전력 다이 히트 싱크
KR20240000507U (ko) * 2021-07-29 2024-03-15 마벨 아시아 피티이 엘티디. 적층형 집적 회로의 3차원 패키지에서 열 방출 및 전기적 견고성 개선
US20230046413A1 (en) * 2021-08-13 2023-02-16 Mediatek Inc. Semiconductor package assembly
US20230395450A1 (en) * 2022-06-01 2023-12-07 Taiwan Semiconductor Manufacturing Company Limited Reinforced structure with capping layer and methods of forming the same
US20240332121A1 (en) * 2023-03-30 2024-10-03 International Business Machines Corporation Electrically-insulating and highly thermal conductive sheet for electronic devices
KR20260089502A (ko) * 2023-09-28 2026-06-15 피.씨.비. 테크놀로지스 리미티드 고전력 디바이스 패키지를 위한 전도성 관통부를 갖는 열 확산 코어

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020637A (en) 1997-05-07 2000-02-01 Signetics Kp Co., Ltd. Ball grid array semiconductor package
KR100432715B1 (ko) * 2001-07-18 2004-05-24 엘지전자 주식회사 방열부재를 갖는 인쇄회로기판 및 그 제조방법
JP2004172286A (ja) * 2002-11-19 2004-06-17 Kyocera Chemical Corp 熱伝導シート
JP4300316B2 (ja) * 2005-02-15 2009-07-22 独立行政法人産業技術総合研究所 積層型集積回路装置
US7317256B2 (en) 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
JP5025113B2 (ja) * 2005-09-29 2012-09-12 三洋電機株式会社 回路装置
JP4463178B2 (ja) * 2005-09-30 2010-05-12 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US7432592B2 (en) 2005-10-13 2008-10-07 Intel Corporation Integrated micro-channels for 3D through silicon architectures
KR100702968B1 (ko) 2005-11-24 2007-04-03 삼성전자주식회사 플로팅된 히트 싱크를 갖는 반도체 패키지와, 그를 이용한적층 패키지 및 그의 제조 방법
KR100842910B1 (ko) * 2006-06-29 2008-07-02 주식회사 하이닉스반도체 스택 패키지
US8110899B2 (en) 2006-12-20 2012-02-07 Intel Corporation Method for incorporating existing silicon die into 3D integrated stack
US20080153200A1 (en) * 2006-12-22 2008-06-26 Arkalgud Sitaram Stacked semiconductor components
CN101589468A (zh) * 2007-01-17 2009-11-25 Nxp股份有限公司 具有通过衬底的通路孔的系统级封装
US20080173792A1 (en) * 2007-01-23 2008-07-24 Advanced Chip Engineering Technology Inc. Image sensor module and the method of the same
US20080217761A1 (en) * 2007-03-08 2008-09-11 Advanced Chip Engineering Technology Inc. Structure of semiconductor device package and method of the same
US20080237844A1 (en) * 2007-03-28 2008-10-02 Aleksandar Aleksov Microelectronic package and method of manufacturing same
TWI338939B (en) 2007-08-15 2011-03-11 Via Tech Inc Package module and electronic device
US7592697B2 (en) 2007-08-27 2009-09-22 Intel Corporation Microelectronic package and method of cooling same
JP2009071004A (ja) * 2007-09-13 2009-04-02 Panasonic Corp 半導体装置とその製造方法
JP2009246258A (ja) * 2008-03-31 2009-10-22 Nikon Corp 半導体装置および製造方法
US7803714B2 (en) 2008-03-31 2010-09-28 Freescale Semiconductor, Inc. Semiconductor through silicon vias of variable size and method of formation
US8154134B2 (en) * 2008-05-12 2012-04-10 Texas Instruments Incorporated Packaged electronic devices with face-up die having TSV connection to leads and die pad
US7928563B2 (en) 2008-05-28 2011-04-19 Georgia Tech Research Corporation 3-D ICs with microfluidic interconnects and methods of constructing same
US8026567B2 (en) * 2008-12-22 2011-09-27 Taiwan Semiconductor Manufactuirng Co., Ltd. Thermoelectric cooler for semiconductor devices with TSV
US8314483B2 (en) * 2009-01-26 2012-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. On-chip heat spreader
KR20120053675A (ko) * 2010-11-18 2012-05-29 삼성전자주식회사 반도체 패키지 및 그의 제조 방법, 및 인터포저 칩 및 그의 제조 방법

Also Published As

Publication number Publication date
JP2012028771A (ja) 2012-02-09
CN102339800A (zh) 2012-02-01
TWI413222B (zh) 2013-10-21
US8492911B2 (en) 2013-07-23
US9054064B2 (en) 2015-06-09
EP2410563A3 (en) 2017-12-06
KR101795047B1 (ko) 2017-11-07
EP2410563A2 (en) 2012-01-25
KR20120018713A (ko) 2012-03-05
TW201212181A (en) 2012-03-16
EP3651194B1 (en) 2021-11-17
EP3651194B8 (en) 2021-12-22
EP3651194A1 (en) 2020-05-13
US20150214130A1 (en) 2015-07-30
US20120020028A1 (en) 2012-01-26
US20130280864A1 (en) 2013-10-24
EP2410563B1 (en) 2020-04-15

Similar Documents

Publication Publication Date Title
KR101795047B1 (ko) 적층형 상호접속 열 싱크
US11233036B2 (en) Interconnect structure with redundant electrical connectors and associated systems and methods
US10157772B2 (en) Semiconductor packaging structure and process
US10157900B2 (en) Semiconductor structure and manufacturing method thereof
CN104752236B (zh) 用于封装应用的两步模塑研磨
CN102769076B (zh) 封装载板的制作方法
KR102001128B1 (ko) 열 관리를 위한 미세가공된 필라 핀들을 포함하는 전자 패키지 및 다이를 제조하는 방법
CN112088429B (zh) 均热板以及其制造方法
CN102779808B (zh) 集成电路封装和封装方法
CN103681541A (zh) 晶圆级嵌入式散热器
CN103688350A (zh) 嵌入pcb基板的芯片模块
CN104637895B (zh) 封装结构及其制造方法
CN101292348B (zh) 具有增强的热和器件性能的可堆叠晶片或管芯封装
CN102790140A (zh) 封装结构及其制作方法
US20250309043A1 (en) Package structure and manufacturing method thereof
CN121054495A (zh) 形成封装结构的方法、以及封装结构

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20120713

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140702

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140702

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20140729

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20140805

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20140805

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150217

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150303

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150721

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150826

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20160112

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20160210

R150 Certificate of patent or registration of utility model

Ref document number: 5885952

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250