JP5881734B2 - 同時のウェハ結合及び相互接続接合 - Google Patents

同時のウェハ結合及び相互接続接合 Download PDF

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JP5881734B2
JP5881734B2 JP2013546103A JP2013546103A JP5881734B2 JP 5881734 B2 JP5881734 B2 JP 5881734B2 JP 2013546103 A JP2013546103 A JP 2013546103A JP 2013546103 A JP2013546103 A JP 2013546103A JP 5881734 B2 JP5881734 B2 JP 5881734B2
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microelectronic
metal layer
bond pad
metal
dielectric layer
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JP2014500630A5 (https=
JP2014500630A (ja
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オガネシアン，ヴァーゲ
ハーバ，ベルガセム
モハメッド，イリヤス
サヴァリア，ピーユーシュ
ミッチェル，クレイグ
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テッセラ，インコーポレイテッド
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
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    • H10W72/07231—Techniques
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    • H10W72/07331—Connecting techniques
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    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
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    • H10W72/241—Dispositions, e.g. layouts
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/251—Materials
    • H10W72/255—Materials of outermost layers of multilayered bumps, e.g. material of a coating
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/322—Multilayered die-attach connectors, e.g. a coating on a top surface of a core
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    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/342—Dispositions of die-attach connectors, e.g. layouts relative to the surface, e.g. recessed, protruding
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    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
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    • H10W72/853—On the same surface
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W99/00—Subject matter not provided for in other groups of this subclass

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
JP2013546103A 2010-12-20 2011-04-01 同時のウェハ結合及び相互接続接合 Active JP5881734B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201061424906P 2010-12-20 2010-12-20
US61/424,906 2010-12-20
PCT/US2011/030871 WO2012087364A1 (en) 2010-12-20 2011-04-01 Simultaneous wafer bonding and interconnect joining

Publications (3)

Publication Number Publication Date
JP2014500630A JP2014500630A (ja) 2014-01-09
JP2014500630A5 JP2014500630A5 (https=) 2014-05-15
JP5881734B2 true JP5881734B2 (ja) 2016-03-09

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US (2) US8486758B2 (https=)
EP (1) EP2656383B1 (https=)
JP (1) JP5881734B2 (https=)
KR (2) KR101091551B1 (https=)
CN (1) CN103370784B (https=)
TW (1) TWI406383B (https=)
WO (1) WO2012087364A1 (https=)

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US9704841B2 (en) * 2014-03-26 2017-07-11 United Microelectronics Corp. Method of packaging stacked dies on wafer using flip-chip bonding
CN105023877B (zh) 2014-04-28 2019-12-24 联华电子股份有限公司 半导体晶片、封装结构与其制作方法
KR102258743B1 (ko) 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
TWI645479B (zh) 2015-05-13 2018-12-21 財團法人工業技術研究院 貼合結構、其製造方法及晶粒結構
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US9666560B1 (en) 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
US9691747B1 (en) 2015-12-21 2017-06-27 International Business Machines Corporation Manufacture of wafer—panel die package assembly technology
TWI607587B (zh) * 2016-09-13 2017-12-01 台灣琭旦股份有限公司 固晶穩固製程
US10283445B2 (en) 2016-10-26 2019-05-07 Invensas Corporation Bonding of laminates with electrical interconnects
CN111115555B (zh) * 2019-12-20 2023-08-29 北京航天控制仪器研究所 一种用于mems晶圆级共晶键合封装的硅槽结构及制备方法
CN111179612B (zh) * 2019-12-27 2021-09-07 讯飞智元信息科技有限公司 交叉口车道功能生成方法、装置和设备
US11270963B2 (en) 2020-01-14 2022-03-08 Sandisk Technologies Llc Bonding pads including interfacial electromigration barrier layers and methods of making the same
US20210296281A1 (en) * 2020-03-20 2021-09-23 Integrated Silicon Solution Inc. Wafer-bonding structure and method of forming thereof
CN112103261A (zh) * 2020-11-10 2020-12-18 浙江里阳半导体有限公司 半导体封装结构及其制作方法
US12598962B2 (en) 2023-03-14 2026-04-07 Adeia Semiconductor Bonding Technologies Inc. System and method for bonding transparent conductor substrates

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US8709913B2 (en) 2014-04-29
KR20120069515A (ko) 2012-06-28
US20130341804A1 (en) 2013-12-26
WO2012087364A1 (en) 2012-06-28
US20120153488A1 (en) 2012-06-21
JP2014500630A (ja) 2014-01-09
CN103370784B (zh) 2016-08-24
KR101091551B1 (ko) 2011-12-13
TWI406383B (zh) 2013-08-21
US8486758B2 (en) 2013-07-16
EP2656383A1 (en) 2013-10-30
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