CN103370784B - 同时的晶圆结合及互连接合 - Google Patents

同时的晶圆结合及互连接合 Download PDF

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Publication number
CN103370784B
CN103370784B CN201180067909.3A CN201180067909A CN103370784B CN 103370784 B CN103370784 B CN 103370784B CN 201180067909 A CN201180067909 A CN 201180067909A CN 103370784 B CN103370784 B CN 103370784B
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metal layer
microelectronic
metal
major surface
assembly
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CN103370784A (zh
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瓦格·奥甘赛安
贝勒卡西姆·哈巴
伊利亚斯·默罕默德
皮尤什·萨瓦利亚
克雷格·米切尔
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
CN201180067909.3A 2010-12-20 2011-04-01 同时的晶圆结合及互连接合 Active CN103370784B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201061424906P 2010-12-20 2010-12-20
US61/424,906 2010-12-20
PCT/US2011/030871 WO2012087364A1 (en) 2010-12-20 2011-04-01 Simultaneous wafer bonding and interconnect joining

Publications (2)

Publication Number Publication Date
CN103370784A CN103370784A (zh) 2013-10-23
CN103370784B true CN103370784B (zh) 2016-08-24

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US (2) US8486758B2 (https=)
EP (1) EP2656383B1 (https=)
JP (1) JP5881734B2 (https=)
KR (2) KR101091551B1 (https=)
CN (1) CN103370784B (https=)
TW (1) TWI406383B (https=)
WO (1) WO2012087364A1 (https=)

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US9237648B2 (en) 2013-02-25 2016-01-12 Invensas Corporation Carrier-less silicon interposer
US9691693B2 (en) 2013-12-04 2017-06-27 Invensas Corporation Carrier-less silicon interposer using photo patterned polymer as substrate
CN104900543B (zh) * 2014-03-06 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
US9704841B2 (en) * 2014-03-26 2017-07-11 United Microelectronics Corp. Method of packaging stacked dies on wafer using flip-chip bonding
CN105023877B (zh) 2014-04-28 2019-12-24 联华电子股份有限公司 半导体晶片、封装结构与其制作方法
KR102258743B1 (ko) 2014-04-30 2021-06-02 삼성전자주식회사 반도체 패키지의 제조 방법, 이에 의해 형성된 반도체 패키지 및 이를 포함하는 반도체 장치
US9437536B1 (en) 2015-05-08 2016-09-06 Invensas Corporation Reversed build-up substrate for 2.5D
TWI645479B (zh) 2015-05-13 2018-12-21 財團法人工業技術研究院 貼合結構、其製造方法及晶粒結構
US10211160B2 (en) 2015-09-08 2019-02-19 Invensas Corporation Microelectronic assembly with redistribution structure formed on carrier
US9666560B1 (en) 2015-11-25 2017-05-30 Invensas Corporation Multi-chip microelectronic assembly with built-up fine-patterned circuit structure
US9691747B1 (en) 2015-12-21 2017-06-27 International Business Machines Corporation Manufacture of wafer—panel die package assembly technology
TWI607587B (zh) * 2016-09-13 2017-12-01 台灣琭旦股份有限公司 固晶穩固製程
US10283445B2 (en) 2016-10-26 2019-05-07 Invensas Corporation Bonding of laminates with electrical interconnects
CN111115555B (zh) * 2019-12-20 2023-08-29 北京航天控制仪器研究所 一种用于mems晶圆级共晶键合封装的硅槽结构及制备方法
CN111179612B (zh) * 2019-12-27 2021-09-07 讯飞智元信息科技有限公司 交叉口车道功能生成方法、装置和设备
US11270963B2 (en) 2020-01-14 2022-03-08 Sandisk Technologies Llc Bonding pads including interfacial electromigration barrier layers and methods of making the same
US20210296281A1 (en) * 2020-03-20 2021-09-23 Integrated Silicon Solution Inc. Wafer-bonding structure and method of forming thereof
CN112103261A (zh) * 2020-11-10 2020-12-18 浙江里阳半导体有限公司 半导体封装结构及其制作方法
US12598962B2 (en) 2023-03-14 2026-04-07 Adeia Semiconductor Bonding Technologies Inc. System and method for bonding transparent conductor substrates

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CN101527300A (zh) * 2008-03-05 2009-09-09 台湾积体电路制造股份有限公司 堆叠式集成电路与其制造方法

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US20130341804A1 (en) 2013-12-26
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US8486758B2 (en) 2013-07-16
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