JP5867467B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5867467B2 JP5867467B2 JP2013182439A JP2013182439A JP5867467B2 JP 5867467 B2 JP5867467 B2 JP 5867467B2 JP 2013182439 A JP2013182439 A JP 2013182439A JP 2013182439 A JP2013182439 A JP 2013182439A JP 5867467 B2 JP5867467 B2 JP 5867467B2
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- 239000004065 semiconductor Substances 0.000 title claims description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims description 75
- 238000000034 method Methods 0.000 claims description 32
- 238000005219 brazing Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 description 13
- 230000004048 modification Effects 0.000 description 6
- 238000012986 modification Methods 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 230000035882 stress Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L2924/37001—Yield
Description
(実施例1の特徴2) 溝の幅方向におけるマスクの開口幅の製造誤差を記号aで表し、マスクの載置位置の誤差を記号bで表した場合に、溝の幅がa+2b以上である。
(実施例2の特徴1) 基板の上面には、凹部が形成されている。基板上にマスクを載置する工程では、凹部に隣接する領域をマスクで覆い、凹部上にマスクの開口が位置するようにマスクを載置する。このとき、マスクの開口の端部は、凹部の上方に位置させる。凹部とマスクの間には空間が存在する。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
12:半導体基板
14:絶縁膜
14a:段差構造体
14b:絶縁膜
16:導電膜
18:基板
20:溝
22:内部領域
24:外部領域
30:はんだ
32:外部端子
40:マスク
42:開口
44:端部
50:凹部
52:外部領域
Claims (3)
- 半導体装置の製造方法であって、
上面に凹部を有する基板上に、開口を有するマスクを載置する工程であって、基板の上面のうちの凹部の外側の外部領域の少なくとも一部がマスクの下面に接触し、かつ、凹部の上方にマスクの開口の端部が位置するように載置する工程と、
基板上にマスクを載置した後に、マスクを通して基板の上面に導電膜を成長させる工程と、
導電膜を成長させた後に、マスクを基板から取り外す工程、
を有し、
凹部が、基板の上面を一巡するように伸びる溝であることを特徴とする半導体装置の製造方法。 - マスクの下面に平坦領域が形成されており、
基板上にマスクを載置する工程では、平坦領域を外部領域の少なくとも一部に接触させることを特徴とする請求項1の製造方法。 - マスクを基板から取り外した後に、基板の上面の導電膜に対してろう付けする工程をさらに有する請求項1または2の製造方法。
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JP2013182439A JP5867467B2 (ja) | 2013-09-03 | 2013-09-03 | 半導体装置の製造方法 |
US14/469,056 US9437562B2 (en) | 2013-09-03 | 2014-08-26 | Semiconductor device and manufacturing method of semiconductor device |
DE102014217257.8A DE102014217257A1 (de) | 2013-09-03 | 2014-08-29 | Halbleitervorrichtung und herstellungsverfahren einer halblei- tervorrichtung |
CN201410439886.XA CN104425296B (zh) | 2013-09-03 | 2014-09-01 | 半导体装置以及半导体装置的制造方法 |
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