CN109671774B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN109671774B
CN109671774B CN201710975386.1A CN201710975386A CN109671774B CN 109671774 B CN109671774 B CN 109671774B CN 201710975386 A CN201710975386 A CN 201710975386A CN 109671774 B CN109671774 B CN 109671774B
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source electrode
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CN109671774A (zh
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潘盼
张乃千
宋晰
许建华
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Suzhou Nexun High Energy Semiconductor Co ltd
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Abstract

本发明实施例提供一种半导体器件及其制造方法，涉及微电子技术领域。该半导体器件包括半导体基底、源极、栅极和漏极。源极、栅极和漏极制作于所述半导体基底一侧，在源极所在区域预留有通孔区域并在该通孔区域制作有刻蚀阻挡层；位于所述刻蚀阻挡层下方设置有贯穿所述半导体基底的通孔。通过在源极中设置通孔区域，并在通孔区域内设置刻蚀阻挡层，使得在进行与源极对应的通孔刻蚀时，能减少对通孔区域源极金属的刻蚀损伤。在刻蚀过程中，可以更容易的判断刻蚀进度，降低通孔刻蚀的工艺难度。同时可以提高通孔刻蚀时的刻蚀选择比，减少刻蚀过程中刻蚀产物的数量。

Description

半导体器件及其制造方法
技术领域
本发明涉及微电子技术领域，具体而言，涉及一种半导体器件及其制造方法。
背景技术
氮化镓半导体材料具有禁带宽度大、电子饱和漂移速率高、击穿场强高、耐高温等显著优点，与第一代半导体硅和第二代半导体砷化镓相比，更适合于制作高温、高压、高频和大功率的电子器件，具有广阔的应用前景，已成为目前半导体行业研究的热点。
氮化镓高电子迁移率晶体管(HEMT)是利用AlGaN/GaN异质结处的二维电子气形成的一种氮化镓器件，可以应用于需要高频、高压和大功率的场合。在封装氮化镓器件时，为了提高器件增益，减小接地电阻，通常采用通孔结构。这种结构的通孔通常通过从基底背面刻蚀的方式引入，并通过使基底背面接地而实现半导体器件接地。具体而言，通孔贯穿基底和氮化物半导体层，直至源极，从而通过该通孔将源极和接地的基底背面相连。
目前氮化镓器件的通孔位置分布主要有两种形式。一种是将通孔开设在金属PAD区域。这种方式使通孔位于有源区的同侧，虽然降低了通孔对器件散热的影响，但是导致有源区电流整体流向相同、不分散，从而使有源区金属插指之间产生了互感。并且这种方式也增大了有源区内的源极到地的距离，即增大了源极的接地电阻，从而影响了器件的增益等性能。另一种是将通孔开设在位于有源区的源极的下方。这种方式使每个有源区内的源极可以通过通孔直接接地，减小了有源区内的源极到地的距离，从而减小了接地电阻。但是，这种将通孔全部设置在有源区的方式会在通孔刻蚀时，因刻蚀在源极OHMC接触金属上。因为OHMC接触金属的颜色在刻蚀之后呈现暗黑色，无法判断有多少刻蚀副产物残留在通孔底部。增加了刻蚀工艺难度，影响器件特性。
发明内容
鉴于以上内容，本发明实施例的目的在于提供一种半导体器件及其制造方法，以改善上述问题。
本发明实施例提供的技术方案如下：
一种半导体器件，所述半导体器件包括：
半导体基底；
制作于所述半导体基底一侧的源极、栅极和漏极；
在形成欧姆接触的源极所在区域预留的通孔区域以及在该区域制作的刻蚀阻挡层；以及
位于所述刻蚀阻挡层下方贯穿所述半导体基底的通孔。
进一步的，所述刻蚀阻挡层的面积小于所述预留的通孔区域的面积，所述刻蚀阻挡层与所述源极之间具有空隙，使所述源极与所述刻蚀阻挡层不直接接触。
进一步的，所述源极以及所述刻蚀阻挡层上方覆盖有连通金属，使所述源极和所述刻蚀阻挡层通过该连通金属连接。
进一步的，所述刻蚀阻挡层覆盖所述预留的通孔区域和源极，使所述刻蚀阻挡层与所述源极直接接触。
进一步的，所述预留的通孔区域在平行于所述栅极的方向上贯穿所述源极的至少一端，使该源极的至少一端呈开口状。
进一步的，所述预留的通孔区域在平行于所述栅极的方向贯穿所述源极，使该源极两端呈开口状。
进一步的，该半导体器件在每个源极对应的区域开设多个预留的通孔区域，该多个通孔区域相互连通并在平行于栅极的方向贯穿该源极，使该源极两端呈开口状。
进一步的，所述预留的通孔区域位于所述源极内部区域，使所述源极没有开口。
进一步的，所述刻蚀阻挡层的面积大于所述通孔靠近所述半导体基底设置所述源极一侧的横截面的面积。
本发明还提供了一种半导体器件的制造方法，该制造方法包括：
提供一半导体基底；
在所述半导体基底一侧制作源极、栅极和漏极，其中，在制作所述源极时，在所述源极所在区域形成预留的通孔区域，该通孔区域内没有源极欧姆金属；
在所述预留的通孔区域制作刻蚀阻挡层；
在所述源极和刻蚀阻挡层位于所述半导体基底的同一侧制作连通金属，使所述源极和刻蚀阻挡层通过所述连通金属连接；
从所述半导体基底远离所述源极的一侧，所述刻蚀阻挡层的下方刻蚀形成贯穿所述半导体基底的通孔。
进一步的，在所述源极所在区域形成预留的通孔区域的步骤包括：
在所述半导体基底一侧预先确定的预留的通孔区域的部分使用遮挡材料覆盖，然后在该侧沉积材料形成源极欧姆金属；
将所述遮挡材料去除，形成所述预留的通孔区域。
本申请实施例提供的半导体器件通过在源极中设置预留的通孔区域，并在预留的通孔区域内设置刻蚀阻挡层，使得在进行与源极对应的通孔刻蚀时，能减少对通孔区域源极金属的刻蚀损伤。在刻蚀过程中，可以更容易的判断刻蚀进度，降低通孔刻蚀的工艺难度。同时可以提高通孔刻蚀时的刻蚀选择比，减少刻蚀过程中刻蚀产物的数量。
为使本发明的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1是本发明实施例提供的一种半导体器件的源漏栅电极位置示意图。
图2是图1中沿A-A’切线的截面图。
图3是本发明实施例提供的半导体器件中源极OHMC金属部分的一种示意图。
图4是本发明实施例提供的半导体器件中源极OHMC金属和刻蚀阻挡层金属位置的一种示意图。
图5是本发明实施例提供的半导体器件中源极OHMC金属、刻蚀阻挡层和通孔所处位置的一种示意图。
图6是本发明实施例提供的半导体器件中源极OHMC金属和预留的通孔区域部分的另一示意图。
图7是本发明实施例提供的半导体器件中源极OHMC金属和预留的通孔区域部分的另一示意图。
图8是本发明实施例提供的半导体器件中源极OHMC金属和预留的通孔区域部分的另一示意图。
图9是本发明实施例提供的半导体器件中源极OHMC金属和预留的通孔区域部分的另一示意图。
图10是本发明实施例提供的半导体器件的示意图。
图11是本发明实施例提供的半导体器件的部分制造方法的流程图。
图标：100-半导体器件；110-半导体基底；111-基底片；112-外延层；120-源极；130-漏极；140-栅极；150-刻蚀阻挡层；160-通孔；170-连通金属；10-有源区；20-无源区；180-栅极焊盘；181-栅极连通金属；182-栅极互连线；190-漏极焊盘；191-漏极连通金属；192-漏极互连线；210-预留的通孔区域；211-开口。
具体实施方式
下面将结合本发明实施例中附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
发明人发现，在进行源极对应的通孔刻蚀时，欧姆金属与半导体材料在高温退火后融合，部分金属扩散至半导体材料内且不均匀，因此半导体和金属不存在清晰的界面，导致通孔刻蚀时无法准确判断刻蚀终点，存在非常大的欠刻蚀或过刻蚀风险，工艺无法控制。同时也因为源极的合金金属颜色会影响刻蚀结果的判断，另一方面该区域金属为合金金属，电阻相对较高，影响电流。
本申请实施例提供了一种半导体器件100，如图1和图2所示，所述半导体器件100包括半导体基底110、源极120、漏极130、栅极140、刻蚀阻挡层150以及通孔160。
半导体基底110可以包括基底片111和生长在基底片111一侧的外延层112。基底片111可以采用由硅、蓝宝石、碳化硅或砷化镓中的其中一种材料形成。外延层112可由氮化镓或铝镓氮中的一种或两种形成。可以理解的是，半导体基底110也可以只由基底片111构成，不生长外延层112。
源极120、漏极130和栅极140制作于所述半导体基底110一侧。在本申请实施例中，半导体基底110上可以制作多个源极120、多个栅极140和多个漏极130。多个源极120和多个漏极130可以交替设置，多个栅极140可以呈插指状设置在相邻的源极120和漏极130之间。其中，源极120和漏极130可以为欧姆接触电极，栅极140可以为肖特基接触电极。栅极140可以为单层金属栅极，也可以是双层金属或多层金属形成的叠层或多层栅极结构。
在本申请实施例中，源极120所在区域内预留有通孔区域210(可结合参考图6)，在该预留的通孔区域210内制作有刻蚀阻挡层150。在源极120的制作过程中，可以先在预留的通孔区域210制作遮挡材料，如使用光刻工艺制作形成通孔区域210，再在源极区域通过蒸发或者溅射等工艺形成源极120欧姆金属，将遮挡材料剥离后即可形成没有欧姆金属的通孔区域210，源极120可以采用一种金属材料或者多种金属材料的复合材料形成，高温退火后使源极120与半导体基底110形成欧姆接触。在该通孔区域210内再通过光刻、沉积或刻蚀等工艺即可形成刻蚀阻挡层150。刻蚀阻挡层150的材料可以采用一种金属或多种金属的复合材料。例如，可以采用金、钨、鉑、钛、镍金属中的一种或者几种的组合形成刻蚀阻挡层150。
本申请实施例中的通孔160位于所述刻蚀阻挡层150下方且贯穿所述半导体基底110。通孔160的形状可以根据实际需要确定，例如通孔160的横截面可以为圆形、椭圆形、方形或其他形状，本申请实施例对通孔160的形状并不做出限定。通孔区域210的形状可以与通孔160的形状相对应，也可以制作成圆形、椭圆形、方形或其他形状。通孔160的数量也可以根据实际需要确定，通孔160可以为一个或多个。
刻蚀阻挡层150的材料相对于半导体基底110和连通金属有更高的刻蚀选择比，能够确保通孔160被刻蚀完成时能完全穿过半导体基底110，而终止于该刻蚀阻挡层150，使进行通孔160的刻蚀时不会损伤或穿过正面电极金属。刻蚀阻挡层150的横截面形状和通孔160的横截面形状相同或相似，其形状的大小和具有结构有关。
如图3所示，所述源极120以及所述刻蚀阻挡层150上方还可以覆盖连通金属170，使所述源极120和所述刻蚀阻挡层150通过该连通金属170连接。可以理解的是，制作形成连通金属170后，本申请实施例中的可以把刻蚀阻挡层150以及连通金属170也作为源极的一部分，当然刻蚀阻挡层150以及连通金属170也可以是分别独立的部分。半导体基底110远离源极120的一侧还可以制作接地电极，在通孔160内可以填充导电材料，使源极120可以通过通孔160内的导电材料与接地电极连接，实现源极120的接地。其中，通孔区域210的边缘与通过制作欧姆金属形成的源极120的相应的边缘，在垂直于栅极140方向上的宽度可以大于3um。
在一种具体实施方式中，如图4和图5所示，刻蚀阻挡层150的面积大于通孔160趋近于有源极一侧的半导体基底的横截面(俯视)的面积。所述刻蚀阻挡层150与所述源极120之间具有空隙，使所述源极120与所述刻蚀阻挡层150不直接接触。
在另一种具体实施方式中，刻蚀阻挡层150还可以覆盖所述预留的通孔区域210，使所述刻蚀阻挡层150与所述源极120直接接触。优选的，刻蚀阻挡层150的面积小于所述预留的通孔区域210的面积。
如图6至图8所示，在通孔区域210的形成过程中，为了更容易的剥离通孔区域210内覆盖的遮挡材料。所述通孔区域210在平行于所述栅极140的方向上贯穿所述源极120的至少一端，使该源极120的至少一端呈开口状。通孔区域210形成的开口211可以更容易的将通孔区域210内的如光刻胶等材料剥离，降低通孔区域210的制作难度，简化通孔区域210的制作工艺，提高半导体器件100的制作效率，降低生产成本。
本申请实施例中的通孔区域210为与所有通孔160对应的区域，一个源极120对应的通孔160可以为多个，通孔区域210可以为多个，每个通孔区域210内制作有与通孔160对应的刻蚀阻挡层150，多个刻蚀阻挡层150之间相互独立。例如，通孔160的数量可以为1个至10个，相应的，通孔区域210的数量也为1个至10个，刻蚀阻挡层150的数量也为1个至10个。
详细的，如图7所示，所述通孔区域210在平行于所述栅极140的方向可以左右贯穿所述源极120，使该源极120两端呈开口状。在通孔区域210为一个时，该通孔区域210在平行于栅极140的方向上分别形成开口211，使其贯穿源极120。或者，如图6所示，在通孔区域210为多个时，多个通孔区域210可以在平行于栅极140的方向上依次排列，位于两端的两个通孔区域210分别形成开口211。或者，再如图8所示，所有通孔区域210也可以相互连通并贯穿源极120，使源极120的两端呈开口状。
如图9所示，所述预留的通孔区域210也可以完全位于源极120欧姆金属区域内，使源极没有开口，通孔区域210周围都有制作源极形成的欧姆金属。
如图10所示，本申请实施例中的半导体器件100可以包括有源区10和无源区20，上述源极120、漏极130和栅极140可以制作于有源区10。有源区10内的源极120、漏极130和栅极140可以为多个，无源区20还可以制作多个栅极焊盘180和多个漏极焊盘190。栅极焊盘180可以通过栅极连通金属181、栅极互连线182与栅极140连接，漏极焊盘190可以通过漏极连通金属191和漏极互连线192与漏极130连接。栅极互连线182和漏极互连线192可以采用金属或其他材料制作，本申请实施例对其不做出限制。
本申请实施例还提供了一种半导体器件的制造方法，如图11所示，包括以下步骤。
步骤S101，提供一半导体基底；
步骤S102，在所述半导体基底一侧制作源极、栅极和漏极，其中，在制作所述源极时，在所述源极所在区域形成预留的通孔区域，该预留的通孔区域内没有源极欧姆金属；
步骤S103，在所述预留的通孔区域制作刻蚀阻挡层；
步骤S104，在所述源极和刻蚀阻挡层位于所述半导体基底的同一侧制作连通金属，使所述源极和刻蚀阻挡层通过所述连通金属连接。
步骤S105，从所述半导体基底远离所述源极的一侧，所述刻蚀阻挡层的下方刻蚀形成贯穿所述半导体基底的通孔。
通过在所述源极和刻蚀阻挡层位于所述半导体基底的同一侧制作连通金属，还可以制作焊盘金属，使所述源极和刻蚀阻挡层通过所述连通金属连接，并与焊盘金属连接，形成完整器件。
在制作所述源极、栅极和漏极时，可以先制作源极和漏极，再制作栅极。在半导体基底的一侧通过光刻、沉积、刻蚀等工艺先形成源极和漏极。在形成源极时，可以在源极所在区域覆盖光刻胶等遮挡材料，光刻胶等遮挡材料覆盖的区域即为通孔区域。在形成源极和漏极后，可以通过退火使源极和漏极与半导体基底形成欧姆接触。
进一步的，将光刻胶等遮挡材料剥离，形成通孔区域。进而可以在通孔区域通过光刻、沉积或刻蚀等工艺制作形成刻蚀阻挡层。刻蚀阻挡层的面积大于通孔的横截面的面积。
然后，从半导体基底的另一侧刻蚀形成所述通孔，在通孔的刻蚀过程中，刻蚀阻挡层金属的刻蚀选择比可以大于半导体基底的刻蚀选择比。通孔的刻蚀过程中产生的刻蚀产物更少，可以更容易判断通孔的刻蚀进度。
综上所述，本申请实施例提供的半导体器件通过在源极中设置通孔区域，并在通孔区域内设置刻蚀阻挡层，使得在进行与源极对应的通孔刻蚀时，能减少对通孔区域源极金属的刻蚀损伤。在刻蚀过程中，可以更容易的判断刻蚀进度，降低通孔刻蚀的工艺难度。同时可以提高通孔刻蚀时的刻蚀选择比，减少刻蚀过程中刻蚀产物的数量。从而提高器件可靠性。
还需要说明的是，在本发明的描述中，除非另有明确的规定和限定，术语“设置”、“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种半导体器件，其特征在于，所述半导体器件包括：
半导体基底；
制作于所述半导体基底一侧的源极、栅极和漏极；
在形成欧姆接触的源极所在区域预留的通孔区域以及在该区域制作的刻蚀阻挡层；以及
位于所述刻蚀阻挡层下方贯穿所述半导体基底的通孔；
其中，所述预留的通孔区域在平行于所述栅极的方向上贯穿所述源极的至少一端，使该源极的至少一端呈开口状。
2.根据权利要求1所述的半导体器件，其特征在于，所述刻蚀阻挡层的面积小于所述预留的通孔区域的面积，所述刻蚀阻挡层与所述源极之间具有空隙，使所述源极与所述刻蚀阻挡层不直接接触。
3.根据权利要求2所述的半导体器件，其特征在于，所述源极以及所述刻蚀阻挡层上方覆盖有连通金属，使所述源极和所述刻蚀阻挡层通过该连通金属连接。
4.根据权利要求1所述的半导体器件，其特征在于，所述刻蚀阻挡层覆盖所述预留的通孔区域和源极，使所述刻蚀阻挡层与所述源极直接接触连通。
5.根据权利要求1所述的半导体器件，其特征在于，所述预留的通孔区域在平行于所述栅极的方向贯穿所述源极，使该源极两端呈开口状。
6.根据权利要求1至4任意一项所述的半导体器件，其特征在于，该半导体器件在每个源极对应的区域开设多个预留的通孔区域，该多个通孔区域相互连通并在平行于栅极的方向贯穿该源极，使该源极两端呈开口状。
7.根据权利要求1所述的半导体器件，其特征在于，所述刻蚀阻挡层的面积大于所述通孔靠近所述半导体基底设置所述源极一侧的横截面的面积。
8.一种半导体器件的制造方法，其特征在于，该制造方法包括：
提供一半导体基底；
在所述半导体基底一侧制作源极、栅极和漏极，其中，在制作所述源极时，在所述源极所在区域形成预留的通孔区域，该预留的通孔区域内没有源极欧姆金属；其中，所述预留的通孔区域在平行于所述栅极的方向上贯穿所述源极的至少一端，使该源极的至少一端呈开口状；
在所述预留的通孔区域制作刻蚀阻挡层；
在所述源极和刻蚀阻挡层位于所述半导体基底的同一侧制作连通金属，使所述源极和刻蚀阻挡层通过所述连通金属连接；
从所述半导体基底远离所述源极的一侧，所述刻蚀阻挡层的下方刻蚀形成贯穿所述半导体基底的通孔。
9.根据权利要求8所述的制造方法，其特征在于，在所述源极所在区域形成预留的通孔区域的步骤包括：
在所述半导体基底一侧预先确定的预留的通孔区域的部分使用遮挡材料覆盖，然后在该侧沉积材料形成源极欧姆金属；
将所述遮挡材料去除，形成所述预留的通孔区域。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7215800B2 (ja) * 2019-02-19 2023-01-31 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法および半導体装置
CN117941074A (zh) * 2021-09-15 2024-04-26 华为技术有限公司 半导体器件及其制备方法、功率放大电路、电子设备
WO2023159578A1 (zh) * 2022-02-28 2023-08-31 华为技术有限公司 半导体结构及其工作方法、功率放大电路、电子设备
KR102605408B1 (ko) * 2022-05-12 2023-11-23 주식회사 웨이브피아 반도체 장치

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335247A (zh) * 2007-06-29 2008-12-31 富士通株式会社 半导体器件及其制造方法
CN106252310A (zh) * 2016-06-02 2016-12-21 苏州能讯高能半导体有限公司 半导体器件及其制造方法
WO2017069461A1 (ko) * 2015-10-23 2017-04-27 (주)기가레인 고전자이동도 트랜지스터 및 그의 제조방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166867B2 (en) * 2003-12-05 2007-01-23 International Rectifier Corporation III-nitride device with improved layout geometry
US7119399B2 (en) * 2004-02-27 2006-10-10 Infineon Technologies Ag LDMOS transistor
US7675090B2 (en) * 2005-05-13 2010-03-09 Flextronics International Usa, Inc. Semiconductor device having a contact on a buffer layer thereof and method of forming the same
US7339208B2 (en) * 2005-05-13 2008-03-04 Coldwatt, Inc. Semiconductor device having multiple lateral channels and method of forming the same
US7285807B2 (en) * 2005-08-25 2007-10-23 Coldwatt, Inc. Semiconductor device having substrate-driven field-effect transistor and Schottky diode and method of forming the same
JP5091445B2 (ja) * 2006-09-15 2012-12-05 株式会社東芝 半導体装置およびその製造方法
US8003525B2 (en) * 2007-06-29 2011-08-23 Fujitsu Limited Semiconductor device and method of manufacturing the same
JP5487749B2 (ja) * 2009-06-17 2014-05-07 富士通株式会社 半導体装置及びその製造方法
US9276097B2 (en) * 2012-03-30 2016-03-01 Infineon Technologies Austria Ag Gate overvoltage protection for compound semiconductor transistors
JP5970736B2 (ja) * 2012-04-27 2016-08-17 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
JP6064628B2 (ja) * 2013-01-29 2017-01-25 富士通株式会社 半導体装置
US9871107B2 (en) * 2015-05-22 2018-01-16 Nxp Usa, Inc. Device with a conductive feature formed over a cavity and method therefor
US9589917B1 (en) * 2016-03-21 2017-03-07 Raytheon Company Microwave monolithic integrated circuit (MMIC) having integrated high power thermal dissipating load
US11114543B2 (en) * 2017-01-24 2021-09-07 Taiwan Semiconductor Manufacturing Co., Ltd. Group III-V device structure
US10096550B2 (en) * 2017-02-21 2018-10-09 Raytheon Company Nitride structure having gold-free contact and methods for forming such structures
US10224285B2 (en) * 2017-02-21 2019-03-05 Raytheon Company Nitride structure having gold-free contact and methods for forming such structures
US20190097001A1 (en) * 2017-09-25 2019-03-28 Raytheon Company Electrode structure for field effect transistor
US10153273B1 (en) * 2017-12-05 2018-12-11 Northrop Grumman Systems Corporation Metal-semiconductor heterodimension field effect transistors (MESHFET) and high electron mobility transistor (HEMT) based device and method of making the same
US11177216B2 (en) * 2018-09-06 2021-11-16 Raytheon Company Nitride structures having low capacitance gate contacts integrated with copper damascene structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101335247A (zh) * 2007-06-29 2008-12-31 富士通株式会社 半导体器件及其制造方法
WO2017069461A1 (ko) * 2015-10-23 2017-04-27 (주)기가레인 고전자이동도 트랜지스터 및 그의 제조방법
CN106252310A (zh) * 2016-06-02 2016-12-21 苏州能讯高能半导体有限公司 半导体器件及其制造方法

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