JP5808586B2 - インターポーザの製造方法 - Google Patents

インターポーザの製造方法 Download PDF

Info

Publication number
JP5808586B2
JP5808586B2 JP2011136861A JP2011136861A JP5808586B2 JP 5808586 B2 JP5808586 B2 JP 5808586B2 JP 2011136861 A JP2011136861 A JP 2011136861A JP 2011136861 A JP2011136861 A JP 2011136861A JP 5808586 B2 JP5808586 B2 JP 5808586B2
Authority
JP
Japan
Prior art keywords
layer
substrate
resin layer
interposer
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2011136861A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013004881A (ja
JP2013004881A5 (https=
Inventor
坂口　秀明
秀明 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011136861A priority Critical patent/JP5808586B2/ja
Priority to US13/528,100 priority patent/US8536714B2/en
Publication of JP2013004881A publication Critical patent/JP2013004881A/ja
Publication of JP2013004881A5 publication Critical patent/JP2013004881A5/ja
Application granted granted Critical
Publication of JP5808586B2 publication Critical patent/JP5808586B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP2011136861A 2011-06-21 2011-06-21 インターポーザの製造方法 Expired - Fee Related JP5808586B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011136861A JP5808586B2 (ja) 2011-06-21 2011-06-21 インターポーザの製造方法
US13/528,100 US8536714B2 (en) 2011-06-21 2012-06-20 Interposer, its manufacturing method, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011136861A JP5808586B2 (ja) 2011-06-21 2011-06-21 インターポーザの製造方法

Publications (3)

Publication Number Publication Date
JP2013004881A JP2013004881A (ja) 2013-01-07
JP2013004881A5 JP2013004881A5 (https=) 2014-06-26
JP5808586B2 true JP5808586B2 (ja) 2015-11-10

Family

ID=47361109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011136861A Expired - Fee Related JP5808586B2 (ja) 2011-06-21 2011-06-21 インターポーザの製造方法

Country Status (2)

Country Link
US (1) US8536714B2 (https=)
JP (1) JP5808586B2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908837B2 (en) 2021-03-16 2024-02-20 Kioxia Corporation Semiconductor device
US12501554B2 (en) 2021-03-22 2025-12-16 Panasonic Intellectual Property Management Co., Ltd. Wiring transfer plate, wiring-equipped wiring transfer plate, wiring body intermediate material, and method for manufacturing wiring body

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014011232A1 (en) 2012-07-12 2014-01-16 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
WO2011139619A1 (en) 2010-04-26 2011-11-10 Hsio Technologies, Llc Semiconductor device package adapter
WO2010138493A1 (en) 2009-05-28 2010-12-02 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2012074963A1 (en) 2010-12-01 2012-06-07 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2010147934A1 (en) 2009-06-16 2010-12-23 Hsio Technologies, Llc Semiconductor die terminal
WO2010141303A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Resilient conductive electrical interconnect
WO2014011226A1 (en) 2012-07-10 2014-01-16 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US8912812B2 (en) 2009-06-02 2014-12-16 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
WO2013036565A1 (en) 2011-09-08 2013-03-14 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US8928344B2 (en) 2009-06-02 2015-01-06 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
WO2010141296A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit semiconductor package
WO2010141298A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US9136196B2 (en) 2009-06-02 2015-09-15 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
WO2010141311A1 (en) * 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
WO2010141295A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed flexible circuit
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
WO2010141266A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit peripheral lead semiconductor package
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
WO2012078493A1 (en) 2010-12-06 2012-06-14 Hsio Technologies, Llc Electrical interconnect ic device socket
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US8981568B2 (en) 2009-06-16 2015-03-17 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8981809B2 (en) 2009-06-29 2015-03-17 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US8984748B2 (en) 2009-06-29 2015-03-24 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9082764B2 (en) 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
JP5803998B2 (ja) 2013-07-23 2015-11-04 株式会社村田製作所 電子部品の製造方法及び基板型の端子の製造方法
JP5803997B2 (ja) * 2013-07-23 2015-11-04 株式会社村田製作所 電子部品の製造方法
US9087702B2 (en) 2013-09-04 2015-07-21 Freescale Semiconductor, Inc. Edge coupling of semiconductor dies
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6341714B2 (ja) * 2014-03-25 2018-06-13 新光電気工業株式会社 配線基板及びその製造方法
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
US9859202B2 (en) * 2015-06-24 2018-01-02 Dyi-chung Hu Spacer connector
JP2018037465A (ja) * 2016-08-29 2018-03-08 ウシオ電機株式会社 半導体パッケージおよびその製造方法
US10902769B2 (en) 2017-07-12 2021-01-26 Facebook Technologies, Llc Multi-layer fabrication for pixels with calibration compensation
US10733930B2 (en) * 2017-08-23 2020-08-04 Facebook Technologies, Llc Interposer for multi-layer display architecture
WO2020090963A1 (ja) * 2018-11-02 2020-05-07 株式会社村田製作所 電子機器
MY202414A (en) 2018-11-28 2024-04-27 Intel Corp Embedded reference layers fo semiconductor package substrates
US11610935B2 (en) 2019-03-29 2023-03-21 Lumileds Llc Fan-out light-emitting diode (LED) device substrate with embedded backplane, lighting system and method of manufacture
US11631594B2 (en) 2019-11-19 2023-04-18 Lumileds Llc Fan out structure for light-emitting diode (LED) device and lighting system
US11777066B2 (en) 2019-12-27 2023-10-03 Lumileds Llc Flipchip interconnected light-emitting diode package assembly
US11664347B2 (en) 2020-01-07 2023-05-30 Lumileds Llc Ceramic carrier and build up carrier for light-emitting diode (LED) array
US11476217B2 (en) 2020-03-10 2022-10-18 Lumileds Llc Method of manufacturing an augmented LED array assembly

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2581592B2 (ja) * 1988-09-16 1997-02-12 株式会社日立製作所 フレキシブルピンキャリア及びそれを使用した半導体装置
JP4606783B2 (ja) * 2003-07-25 2011-01-05 新光電気工業株式会社 半導体装置
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
TWI288448B (en) * 2004-09-10 2007-10-11 Toshiba Corp Semiconductor device and method of manufacturing the same
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
JP5358077B2 (ja) * 2007-09-28 2013-12-04 スパンション エルエルシー 半導体装置及びその製造方法
KR20100099573A (ko) * 2009-03-03 2010-09-13 삼성전자주식회사 반도체 장치 및 그 제조방법
KR20100114421A (ko) * 2009-04-15 2010-10-25 삼성전자주식회사 적층 패키지

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908837B2 (en) 2021-03-16 2024-02-20 Kioxia Corporation Semiconductor device
US12501554B2 (en) 2021-03-22 2025-12-16 Panasonic Intellectual Property Management Co., Ltd. Wiring transfer plate, wiring-equipped wiring transfer plate, wiring body intermediate material, and method for manufacturing wiring body

Also Published As

Publication number Publication date
US8536714B2 (en) 2013-09-17
US20120326334A1 (en) 2012-12-27
JP2013004881A (ja) 2013-01-07

Similar Documents

Publication Publication Date Title
JP5808586B2 (ja) インターポーザの製造方法
JP4343044B2 (ja) インターポーザ及びその製造方法並びに半導体装置
KR100621438B1 (ko) 감광성 폴리머를 이용한 적층 칩 패키지 및 그의 제조 방법
JP5325736B2 (ja) 半導体装置及びその製造方法
JP4551321B2 (ja) 電子部品実装構造及びその製造方法
KR102450822B1 (ko) 반도체 장치의 제조 방법
JP4361826B2 (ja) 半導体装置
JP4551255B2 (ja) 半導体装置
JP5367523B2 (ja) 配線基板及び配線基板の製造方法
JP4708399B2 (ja) 電子装置の製造方法及び電子装置
JP5139347B2 (ja) 電子部品装置及びその製造方法
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
JP5237607B2 (ja) 基板の製造方法
JP5151158B2 (ja) パッケージ、およびそのパッケージを用いた半導体装置
JP5406572B2 (ja) 電子部品内蔵配線基板及びその製造方法
KR102210802B1 (ko) 반도체 장치 및 그 제조 방법
JPWO2020090601A1 (ja) 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法
JP2008270362A (ja) 積層配線基板及びその製造方法
JP5238182B2 (ja) 積層配線基板の製造方法
CN100563000C (zh) 半导体器件及其制造方法
JP2013030748A (ja) 電子部品
JP2009146940A (ja) 積層配線基板及びその製造方法
KR20130112353A (ko) 반도체 패키지 및 그 제조방법
JP5285385B2 (ja) 積層配線基板の製造方法
JP2008198805A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140514

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20140514

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20141222

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150113

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150216

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150901

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150909

R150 Certificate of patent or registration of utility model

Ref document number: 5808586

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees