JP5808586B2 - インターポーザの製造方法 - Google Patents

インターポーザの製造方法 Download PDF

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Publication number
JP5808586B2
JP5808586B2 JP2011136861A JP2011136861A JP5808586B2 JP 5808586 B2 JP5808586 B2 JP 5808586B2 JP 2011136861 A JP2011136861 A JP 2011136861A JP 2011136861 A JP2011136861 A JP 2011136861A JP 5808586 B2 JP5808586 B2 JP 5808586B2
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Japan
Prior art keywords
layer
substrate
resin layer
interposer
resin
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Expired - Fee Related
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JP2011136861A
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English (en)
Japanese (ja)
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JP2013004881A (ja
JP2013004881A5 (enExample
Inventor
坂口　秀明
秀明 坂口
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011136861A priority Critical patent/JP5808586B2/ja
Priority to US13/528,100 priority patent/US8536714B2/en
Publication of JP2013004881A publication Critical patent/JP2013004881A/ja
Publication of JP2013004881A5 publication Critical patent/JP2013004881A5/ja
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Publication of JP5808586B2 publication Critical patent/JP5808586B2/ja
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP2011136861A 2011-06-21 2011-06-21 インターポーザの製造方法 Expired - Fee Related JP5808586B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011136861A JP5808586B2 (ja) 2011-06-21 2011-06-21 インターポーザの製造方法
US13/528,100 US8536714B2 (en) 2011-06-21 2012-06-20 Interposer, its manufacturing method, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011136861A JP5808586B2 (ja) 2011-06-21 2011-06-21 インターポーザの製造方法

Publications (3)

Publication Number Publication Date
JP2013004881A JP2013004881A (ja) 2013-01-07
JP2013004881A5 JP2013004881A5 (enExample) 2014-06-26
JP5808586B2 true JP5808586B2 (ja) 2015-11-10

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US11908837B2 (en) 2021-03-16 2024-02-20 Kioxia Corporation Semiconductor device
US12501554B2 (en) 2021-03-22 2025-12-16 Panasonic Intellectual Property Management Co., Ltd. Wiring transfer plate, wiring-equipped wiring transfer plate, wiring body intermediate material, and method for manufacturing wiring body

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US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
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US9054097B2 (en) * 2009-06-02 2015-06-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
WO2013036565A1 (en) 2011-09-08 2013-03-14 Hsio Technologies, Llc Direct metalization of electrical circuit structures
WO2010141298A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US9093767B2 (en) 2009-06-02 2015-07-28 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9136196B2 (en) 2009-06-02 2015-09-15 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
WO2012078493A1 (en) 2010-12-06 2012-06-14 Hsio Technologies, Llc Electrical interconnect ic device socket
WO2012061008A1 (en) 2010-10-25 2012-05-10 Hsio Technologies, Llc High performance electrical circuit structure
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
WO2010141266A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit peripheral lead semiconductor package
WO2011002709A1 (en) 2009-06-29 2011-01-06 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
WO2010147934A1 (en) 2009-06-16 2010-12-23 Hsio Technologies, Llc Semiconductor die terminal
WO2010141316A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
US8618649B2 (en) 2009-06-02 2013-12-31 Hsio Technologies, Llc Compliant printed circuit semiconductor package
WO2010141313A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
WO2010141303A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9414500B2 (en) 2009-06-02 2016-08-09 Hsio Technologies, Llc Compliant printed flexible circuit
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US8981568B2 (en) 2009-06-16 2015-03-17 Hsio Technologies, Llc Simulated wirebond semiconductor package
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9082764B2 (en) 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US9087777B2 (en) * 2013-03-14 2015-07-21 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
JP5803998B2 (ja) * 2013-07-23 2015-11-04 株式会社村田製作所 電子部品の製造方法及び基板型の端子の製造方法
JP5803997B2 (ja) * 2013-07-23 2015-11-04 株式会社村田製作所 電子部品の製造方法
US9087702B2 (en) 2013-09-04 2015-07-21 Freescale Semiconductor, Inc. Edge coupling of semiconductor dies
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6341714B2 (ja) * 2014-03-25 2018-06-13 新光電気工業株式会社 配線基板及びその製造方法
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
US9859202B2 (en) * 2015-06-24 2018-01-02 Dyi-chung Hu Spacer connector
JP2018037465A (ja) * 2016-08-29 2018-03-08 ウシオ電機株式会社 半導体パッケージおよびその製造方法
US10902769B2 (en) 2017-07-12 2021-01-26 Facebook Technologies, Llc Multi-layer fabrication for pixels with calibration compensation
US10733930B2 (en) * 2017-08-23 2020-08-04 Facebook Technologies, Llc Interposer for multi-layer display architecture
WO2020090963A1 (ja) * 2018-11-02 2020-05-07 株式会社村田製作所 電子機器
MY202414A (en) 2018-11-28 2024-04-27 Intel Corp Embedded reference layers fo semiconductor package substrates
US11626448B2 (en) 2019-03-29 2023-04-11 Lumileds Llc Fan-out light-emitting diode (LED) device substrate with embedded backplane, lighting system and method of manufacture
US11156346B2 (en) 2019-11-19 2021-10-26 Lumileds Llc Fan out structure for light-emitting diode (LED) device and lighting system
US11777066B2 (en) 2019-12-27 2023-10-03 Lumileds Llc Flipchip interconnected light-emitting diode package assembly
US11664347B2 (en) 2020-01-07 2023-05-30 Lumileds Llc Ceramic carrier and build up carrier for light-emitting diode (LED) array
US11476217B2 (en) 2020-03-10 2022-10-18 Lumileds Llc Method of manufacturing an augmented LED array assembly

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2581592B2 (ja) * 1988-09-16 1997-02-12 株式会社日立製作所 フレキシブルピンキャリア及びそれを使用した半導体装置
JP4606783B2 (ja) * 2003-07-25 2011-01-05 新光電気工業株式会社 半導体装置
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
TWI288448B (en) * 2004-09-10 2007-10-11 Toshiba Corp Semiconductor device and method of manufacturing the same
US20090008792A1 (en) * 2004-11-19 2009-01-08 Industrial Technology Research Institute Three-dimensional chip-stack package and active component on a substrate
JP5358077B2 (ja) * 2007-09-28 2013-12-04 スパンション エルエルシー 半導体装置及びその製造方法
KR20100099573A (ko) * 2009-03-03 2010-09-13 삼성전자주식회사 반도체 장치 및 그 제조방법
KR20100114421A (ko) * 2009-04-15 2010-10-25 삼성전자주식회사 적층 패키지

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11908837B2 (en) 2021-03-16 2024-02-20 Kioxia Corporation Semiconductor device
US12501554B2 (en) 2021-03-22 2025-12-16 Panasonic Intellectual Property Management Co., Ltd. Wiring transfer plate, wiring-equipped wiring transfer plate, wiring body intermediate material, and method for manufacturing wiring body

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