JP5728151B2 - Soi基板の作製方法 - Google Patents
Soi基板の作製方法 Download PDFInfo
- Publication number
- JP5728151B2 JP5728151B2 JP2008072633A JP2008072633A JP5728151B2 JP 5728151 B2 JP5728151 B2 JP 5728151B2 JP 2008072633 A JP2008072633 A JP 2008072633A JP 2008072633 A JP2008072633 A JP 2008072633A JP 5728151 B2 JP5728151 B2 JP 5728151B2
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- crystal silicon
- substrate
- layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008072633A JP5728151B2 (ja) | 2007-03-26 | 2008-03-20 | Soi基板の作製方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007079946 | 2007-03-26 | ||
| JP2007079946 | 2007-03-26 | ||
| JP2008072633A JP5728151B2 (ja) | 2007-03-26 | 2008-03-20 | Soi基板の作製方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008270771A JP2008270771A (ja) | 2008-11-06 |
| JP2008270771A5 JP2008270771A5 (enExample) | 2011-04-14 |
| JP5728151B2 true JP5728151B2 (ja) | 2015-06-03 |
Family
ID=39792776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008072633A Expired - Fee Related JP5728151B2 (ja) | 2007-03-26 | 2008-03-20 | Soi基板の作製方法 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US8101466B2 (enExample) |
| JP (1) | JP5728151B2 (enExample) |
| WO (1) | WO2008123116A1 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008123116A1 (en) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| SG178762A1 (en) * | 2007-04-13 | 2012-03-29 | Semiconductor Energy Lab | Display device, method for manufacturing display device, and soi substrate |
| JP5250228B2 (ja) * | 2007-09-21 | 2013-07-31 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| JP5452900B2 (ja) * | 2007-09-21 | 2014-03-26 | 株式会社半導体エネルギー研究所 | 半導体膜付き基板の作製方法 |
| JP2009094488A (ja) * | 2007-09-21 | 2009-04-30 | Semiconductor Energy Lab Co Ltd | 半導体膜付き基板の作製方法 |
| TWI493609B (zh) * | 2007-10-23 | 2015-07-21 | Semiconductor Energy Lab | 半導體基板、顯示面板及顯示裝置的製造方法 |
| US20090193676A1 (en) * | 2008-01-31 | 2009-08-06 | Guo Shengguang | Shoe Drying Apparatus |
| USD602922S1 (en) * | 2008-05-09 | 2009-10-27 | Semiconductor Energy Laboratory Co., Ltd. | Contactless data carrier |
| USD645029S1 (en) * | 2008-05-09 | 2011-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Antenna |
| USD605642S1 (en) * | 2008-09-10 | 2009-12-08 | Semiconductor Energy Laboratory Co., Ltd. | Contactless data carrier |
| JP5478166B2 (ja) * | 2008-09-11 | 2014-04-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| US8278167B2 (en) | 2008-12-18 | 2012-10-02 | Micron Technology, Inc. | Method and structure for integrating capacitor-less memory cell with logic |
| KR101363022B1 (ko) * | 2008-12-23 | 2014-02-14 | 삼성디스플레이 주식회사 | 유기 발광 표시 장치 |
| JP5587107B2 (ja) * | 2009-09-18 | 2014-09-10 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| US9553016B2 (en) | 2010-07-09 | 2017-01-24 | Infineon Technologies Ag | Contacts for semiconductor devices and methods of forming thereof |
| US8487440B2 (en) | 2010-07-09 | 2013-07-16 | Infineon Technologies Ag | Backside processing of semiconductor devices |
| US20130017659A1 (en) * | 2011-07-11 | 2013-01-17 | United Microelectronics Corp. | Fabricating method of semiconductor device |
| US11043186B2 (en) * | 2016-11-02 | 2021-06-22 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method thereof, display device, and electronic device |
| DE102018205670A1 (de) * | 2018-04-13 | 2019-10-17 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Hermetisch abgedichtete Moduleinheit mit integrierten Antennen |
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| US4669177A (en) * | 1985-10-28 | 1987-06-02 | Texas Instruments Incorporated | Process for making a lateral bipolar transistor in a standard CSAG process |
| USRE38296E1 (en) | 1987-04-24 | 2003-11-04 | Hitachi, Ltd. | Semiconductor memory device with recessed array region |
| JPS6461943A (en) | 1987-09-02 | 1989-03-08 | Seiko Epson Corp | Semiconductor device and manufacture thereof |
| JPH046875A (ja) | 1990-04-24 | 1992-01-10 | Mitsubishi Materials Corp | シリコンウェーハ |
| US5618739A (en) * | 1990-11-15 | 1997-04-08 | Seiko Instruments Inc. | Method of making light valve device using semiconductive composite substrate |
| FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
| JPH05235312A (ja) * | 1992-02-19 | 1993-09-10 | Fujitsu Ltd | 半導体基板及びその製造方法 |
| FR2715501B1 (fr) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Procédé de dépôt de lames semiconductrices sur un support. |
| US5524339A (en) * | 1994-09-19 | 1996-06-11 | Martin Marietta Corporation | Method for protecting gallium arsenide mmic air bridge structures |
| US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
| JP3743519B2 (ja) * | 1994-10-18 | 2006-02-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | シリコン−酸化物薄層の製造方法 |
| US6011607A (en) | 1995-02-15 | 2000-01-04 | Semiconductor Energy Laboratory Co., | Active matrix display with sealing material |
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| FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
| FR2748850B1 (fr) * | 1996-05-15 | 1998-07-24 | Commissariat Energie Atomique | Procede de realisation d'un film mince de materiau solide et applications de ce procede |
| JP4103968B2 (ja) | 1996-09-18 | 2008-06-18 | 株式会社半導体エネルギー研究所 | 絶縁ゲイト型半導体装置 |
| US6159825A (en) | 1997-05-12 | 2000-12-12 | Silicon Genesis Corporation | Controlled cleavage thin film separation process using a reusable substrate |
| JPH1145862A (ja) | 1997-07-24 | 1999-02-16 | Denso Corp | 半導体基板の製造方法 |
| US6388652B1 (en) | 1997-08-20 | 2002-05-14 | Semiconductor Energy Laboratory Co., Ltd. | Electrooptical device |
| US6686623B2 (en) | 1997-11-18 | 2004-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and electronic apparatus |
| JPH11163363A (ja) | 1997-11-22 | 1999-06-18 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
| JP2000012864A (ja) | 1998-06-22 | 2000-01-14 | Semiconductor Energy Lab Co Ltd | 半導体装置の作製方法 |
| JP3385972B2 (ja) | 1998-07-10 | 2003-03-10 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法および貼り合わせウェーハ |
| US6271101B1 (en) | 1998-07-29 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Process for production of SOI substrate and process for production of semiconductor device |
| JP4476390B2 (ja) | 1998-09-04 | 2010-06-09 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
| KR20000040104A (ko) | 1998-12-17 | 2000-07-05 | 김영환 | 실리콘 온 인슐레이터 웨이퍼의 제조방법 |
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| JP4780828B2 (ja) * | 2000-11-22 | 2011-09-28 | 三井化学株式会社 | ウエハ加工用粘着テープ及びその製造方法並びに使用方法 |
| FR2818010B1 (fr) * | 2000-12-08 | 2003-09-05 | Commissariat Energie Atomique | Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses |
| JP2002198328A (ja) | 2000-12-25 | 2002-07-12 | Nec Corp | 半導体装置の製造方法および製造装置 |
| JP2003282885A (ja) * | 2002-03-26 | 2003-10-03 | Sharp Corp | 半導体装置およびその製造方法 |
| US7119365B2 (en) | 2002-03-26 | 2006-10-10 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate |
| JP4103447B2 (ja) | 2002-04-30 | 2008-06-18 | 株式会社Ihi | 大面積単結晶シリコン基板の製造方法 |
| US6908797B2 (en) | 2002-07-09 | 2005-06-21 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device |
| US6818529B2 (en) | 2002-09-12 | 2004-11-16 | Applied Materials, Inc. | Apparatus and method for forming a silicon film across the surface of a glass substrate |
| US7508034B2 (en) | 2002-09-25 | 2009-03-24 | Sharp Kabushiki Kaisha | Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device |
| JP4837240B2 (ja) * | 2002-09-25 | 2011-12-14 | シャープ株式会社 | 半導体装置 |
| US7176528B2 (en) | 2003-02-18 | 2007-02-13 | Corning Incorporated | Glass-based SOI structures |
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| JP2004356537A (ja) * | 2003-05-30 | 2004-12-16 | Canon Inc | 半導体装置及びその製造方法 |
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| JP4610982B2 (ja) | 2003-11-11 | 2011-01-12 | シャープ株式会社 | 半導体装置の製造方法 |
| JP3751972B2 (ja) * | 2003-12-02 | 2006-03-08 | 有限会社ボンドテック | 接合方法及びこの方法により作成されるデバイス並びに表面活性化装置及びこの装置を備えた接合装置 |
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| JP5110772B2 (ja) | 2004-02-03 | 2012-12-26 | 株式会社半導体エネルギー研究所 | 半導体薄膜層を有する基板の製造方法 |
| JP4540359B2 (ja) | 2004-02-10 | 2010-09-08 | シャープ株式会社 | 半導体装置およびその製造方法 |
| JP4744820B2 (ja) | 2004-07-12 | 2011-08-10 | シャープ株式会社 | 半導体装置の製造方法及び半導体装置の製造装置 |
| JP2008511137A (ja) | 2004-08-18 | 2008-04-10 | コーニング インコーポレイテッド | 高歪ガラス/ガラス−セラミックを有する絶縁体上半導体構造 |
| US7247545B2 (en) | 2004-11-10 | 2007-07-24 | Sharp Laboratories Of America, Inc. | Fabrication of a low defect germanium film by direct wafer bonding |
| EP1659623B1 (en) | 2004-11-19 | 2008-04-16 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Method for fabricating a germanium on insulator (GeOI) type wafer |
| JP2006210898A (ja) * | 2004-12-28 | 2006-08-10 | Shin Etsu Chem Co Ltd | Soiウエーハの製造方法及びsoiウェーハ |
| JP4776994B2 (ja) * | 2005-07-04 | 2011-09-21 | 浜松ホトニクス株式会社 | 加工対象物切断方法 |
| FR2888663B1 (fr) | 2005-07-13 | 2008-04-18 | Soitec Silicon On Insulator | Procede de diminution de la rugosite d'une couche epaisse d'isolant |
| JP2007053263A (ja) * | 2005-08-18 | 2007-03-01 | Toshiba Matsushita Display Technology Co Ltd | 薄膜トランジスタ、液晶表示装置およびそれらの製造方法 |
| KR101299604B1 (ko) | 2005-10-18 | 2013-08-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 그 제조 방법 |
| WO2007074551A1 (ja) | 2005-12-27 | 2007-07-05 | Shin-Etsu Chemical Co., Ltd. | Soiウェーハの製造方法及びsoiウェーハ |
| FR2911430B1 (fr) | 2007-01-15 | 2009-04-17 | Soitec Silicon On Insulator | "procede de fabrication d'un substrat hybride" |
| WO2008123116A1 (en) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| WO2008123117A1 (en) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| CN101281912B (zh) | 2007-04-03 | 2013-01-23 | 株式会社半导体能源研究所 | Soi衬底及其制造方法以及半导体装置 |
| SG178762A1 (en) * | 2007-04-13 | 2012-03-29 | Semiconductor Energy Lab | Display device, method for manufacturing display device, and soi substrate |
-
2008
- 2008-03-14 WO PCT/JP2008/055167 patent/WO2008123116A1/en not_active Ceased
- 2008-03-20 JP JP2008072633A patent/JP5728151B2/ja not_active Expired - Fee Related
- 2008-03-24 US US12/076,793 patent/US8101466B2/en not_active Expired - Fee Related
-
2011
- 2011-12-29 US US13/339,427 patent/US9111997B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| WO2008123116A1 (en) | 2008-10-16 |
| US9111997B2 (en) | 2015-08-18 |
| US20080237779A1 (en) | 2008-10-02 |
| US8101466B2 (en) | 2012-01-24 |
| US20120098086A1 (en) | 2012-04-26 |
| JP2008270771A (ja) | 2008-11-06 |
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