JP5680184B2 - データバス反転信号伝達を用いる同時スイッチング出力の低減 - Google Patents
データバス反転信号伝達を用いる同時スイッチング出力の低減 Download PDFInfo
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- JP5680184B2 JP5680184B2 JP2013504943A JP2013504943A JP5680184B2 JP 5680184 B2 JP5680184 B2 JP 5680184B2 JP 2013504943 A JP2013504943 A JP 2013504943A JP 2013504943 A JP2013504943 A JP 2013504943A JP 5680184 B2 JP5680184 B2 JP 5680184B2
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- JP
- Japan
- Prior art keywords
- data
- data bus
- bus inversion
- time slots
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Bus Control (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
- Information Transfer Systems (AREA)
- Mobile Radio Communication Systems (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/758,301 | 2010-04-12 | ||
| US12/758,301 US8260992B2 (en) | 2010-04-12 | 2010-04-12 | Reducing simultaneous switching outputs using data bus inversion signaling |
| PCT/US2011/031221 WO2011130059A1 (en) | 2010-04-12 | 2011-04-05 | Reducing simultaneous switching outputs using data bus inversion signaling |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013524383A JP2013524383A (ja) | 2013-06-17 |
| JP2013524383A5 JP2013524383A5 (enExample) | 2014-05-22 |
| JP5680184B2 true JP5680184B2 (ja) | 2015-03-04 |
Family
ID=44193919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013504943A Expired - Fee Related JP5680184B2 (ja) | 2010-04-12 | 2011-04-05 | データバス反転信号伝達を用いる同時スイッチング出力の低減 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8260992B2 (enExample) |
| EP (1) | EP2558945B1 (enExample) |
| JP (1) | JP5680184B2 (enExample) |
| KR (1) | KR101875098B1 (enExample) |
| CN (1) | CN102934098B (enExample) |
| TW (1) | TWI518512B (enExample) |
| WO (1) | WO2011130059A1 (enExample) |
Families Citing this family (24)
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| JP5384210B2 (ja) * | 2009-06-11 | 2014-01-08 | パナソニック株式会社 | データ送信装置、データ受信装置、及びデータ伝送システム |
| US8726139B2 (en) * | 2011-12-14 | 2014-05-13 | Advanced Micro Devices, Inc. | Unified data masking, data poisoning, and data bus inversion signaling |
| US8909840B2 (en) | 2011-12-19 | 2014-12-09 | Advanced Micro Devices, Inc. | Data bus inversion coding |
| US9275692B2 (en) | 2012-02-28 | 2016-03-01 | Micron Technology, Inc. | Memory, memory controllers, and methods for dynamically switching a data masking/data bus inversion input |
| JP2013222285A (ja) * | 2012-04-16 | 2013-10-28 | Fujitsu Semiconductor Ltd | バス回路および半導体装置 |
| US8854236B2 (en) * | 2012-05-18 | 2014-10-07 | Micron Technology, Inc. | Methods and apparatuses for low-power multi-level encoded signals |
| US9172567B2 (en) * | 2013-11-25 | 2015-10-27 | Qualcomm Incorporated | Methods and apparatus to reduce signaling power |
| CN104714902B (zh) * | 2013-12-12 | 2018-08-14 | 华为技术有限公司 | 一种信号处理方法及装置 |
| US9252802B2 (en) | 2014-02-07 | 2016-02-02 | Qualcomm Incorporated | Encoding for partitioned data bus |
| US9148171B1 (en) * | 2014-07-29 | 2015-09-29 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Parallel interface pattern modification for addressing signal integrity concerns |
| US9922686B2 (en) | 2016-05-19 | 2018-03-20 | Micron Technology, Inc. | Apparatuses and methods for performing intra-module databus inversion operations |
| KR102697484B1 (ko) | 2017-01-23 | 2024-08-21 | 에스케이하이닉스 주식회사 | 반도체장치 |
| US10146719B2 (en) | 2017-03-24 | 2018-12-04 | Micron Technology, Inc. | Semiconductor layered device with data bus |
| US10825545B2 (en) * | 2017-04-05 | 2020-11-03 | Micron Technology, Inc. | Memory device loopback systems and methods |
| US10540304B2 (en) | 2017-04-28 | 2020-01-21 | Advanced Micro Devices, Inc. | Power-oriented bus encoding for data transmission |
| KR102441578B1 (ko) * | 2017-10-27 | 2022-09-07 | 삼성전자주식회사 | 다중 데이터 버스 반전 동작을 수행하는 방법 및 메모리 장치 |
| US10664432B2 (en) | 2018-05-23 | 2020-05-26 | Micron Technology, Inc. | Semiconductor layered device with data bus inversion |
| US10964702B2 (en) | 2018-10-17 | 2021-03-30 | Micron Technology, Inc. | Semiconductor device with first-in-first-out circuit |
| CN109582507B (zh) * | 2018-12-29 | 2023-12-26 | 西安紫光国芯半导体股份有限公司 | 用于nvdimm的数据备份和恢复方法、nvdimm控制器以及nvdimm |
| US10963405B2 (en) | 2019-03-29 | 2021-03-30 | Intel Corporation | Minimum input/output toggling rate for interfaces |
| US10944422B1 (en) * | 2019-09-23 | 2021-03-09 | Advanced Micro Devices, Inc. | Entropy agnostic data encoding and decoding |
| US10861508B1 (en) | 2019-11-11 | 2020-12-08 | Sandisk Technologies Llc | Transmitting DBI over strobe in nonvolatile memory |
| KR20210076606A (ko) | 2019-12-16 | 2021-06-24 | 삼성전자주식회사 | SoC, 메모리 장치, 전자 장치 및 전자 장치의 데이터 저장 방법 |
| KR20240071166A (ko) | 2022-11-15 | 2024-05-22 | 에스케이하이닉스 주식회사 | 반도체시스템 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS58186847A (ja) * | 1982-04-27 | 1983-10-31 | Fujitsu Ltd | 内部デ−タバス制御回路 |
| JP3323134B2 (ja) * | 1998-08-18 | 2002-09-09 | エヌイーシー東芝スペースシステム株式会社 | 反転データのフレーム同期検出方法とその装置 |
| US6584526B1 (en) * | 2000-09-21 | 2003-06-24 | Intel Corporation | Inserting bus inversion scheme in bus path without increased access latency |
| AU2002211646A1 (en) | 2000-11-07 | 2002-05-21 | Intel Corporation | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
| US6771192B1 (en) * | 2000-11-22 | 2004-08-03 | Silicon Image, Inc. | Method and system for DC-balancing at the physical layer |
| US20020156953A1 (en) * | 2001-02-28 | 2002-10-24 | Beiley Mark A. | Dynamic bus inversion method |
| TW507128B (en) * | 2001-07-12 | 2002-10-21 | Via Tech Inc | Data memory controller supporting the data bus invert |
| US6898648B2 (en) * | 2002-02-21 | 2005-05-24 | Micron Technology, Inc. | Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing |
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| US20040068594A1 (en) * | 2002-10-08 | 2004-04-08 | Anthony Asaro | Method and apparatus for data bus inversion |
| US7113550B2 (en) * | 2002-12-10 | 2006-09-26 | Rambus Inc. | Technique for improving the quality of digital signals in a multi-level signaling system |
| GB2398650B (en) * | 2003-02-21 | 2006-09-20 | Picochip Designs Ltd | Communications in a processor array |
| JP4505195B2 (ja) * | 2003-04-01 | 2010-07-21 | エイティアイ テクノロジーズ インコーポレイテッド | メモリデバイスにおいてデータを反転させるための方法および装置 |
| JP2005130238A (ja) * | 2003-10-24 | 2005-05-19 | Seiko Epson Corp | 画像処理装置 |
| US20050132112A1 (en) | 2003-12-10 | 2005-06-16 | Pawlowski J. T. | I/O energy reduction using previous bus state and I/O inversion bit for bus inversion |
| US7411840B2 (en) * | 2004-03-02 | 2008-08-12 | Via Technologies, Inc. | Sense mechanism for microprocessor bus inversion |
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| KR100613464B1 (ko) * | 2005-07-06 | 2006-08-22 | 주식회사 하이닉스반도체 | 반도체 장치의 데이터 출력장치 및 출력방법 |
| KR100643498B1 (ko) * | 2005-11-21 | 2006-11-10 | 삼성전자주식회사 | 반도체 메모리에서의 데이터 버스 반전 회로 및 데이터버스 반전 방법 |
| KR100656448B1 (ko) * | 2005-11-29 | 2006-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 dbi 신호 생성장치 및 방법 |
| KR100877680B1 (ko) * | 2006-04-04 | 2009-01-09 | 삼성전자주식회사 | 반도체 장치 사이의 단일형 병렬데이터 인터페이스 방법,기록매체 및 반도체 장치 |
| KR20110101012A (ko) * | 2010-03-05 | 2011-09-15 | 삼성전자주식회사 | 컴바인드 코딩을 이용한 병렬데이터 인터페이스 방법, 기록매체 및 그 장치 |
| KR100763533B1 (ko) * | 2006-06-01 | 2007-10-05 | 삼성전자주식회사 | 버스 인버팅 코드 생성 장치 및 이를 이용한 버스 인버팅코드 생성 방법 |
| KR100744141B1 (ko) * | 2006-07-21 | 2007-08-01 | 삼성전자주식회사 | 싱글 엔디드 신호 라인의 가상 차동 상호 연결 회로 및가상 차동 신호 방식 |
| KR100780955B1 (ko) * | 2006-08-14 | 2007-12-03 | 삼성전자주식회사 | 데이터 반전 방식을 사용하는 메모리 시스템 |
| KR100837813B1 (ko) * | 2006-12-07 | 2008-06-13 | 주식회사 하이닉스반도체 | 반도체 집적 회로의 dbi 신호 생성 장치 및 방법 |
| KR100902051B1 (ko) * | 2007-07-12 | 2009-06-15 | 주식회사 하이닉스반도체 | 오류 검사 코드 생성장치 및 방법 |
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| JP5588976B2 (ja) * | 2008-06-20 | 2014-09-10 | ラムバス・インコーポレーテッド | 周波数応答バス符号化 |
| US7899961B2 (en) * | 2008-09-02 | 2011-03-01 | Qimonda Ag | Multi-mode bus inversion method and apparatus |
| KR101039862B1 (ko) * | 2008-11-11 | 2011-06-13 | 주식회사 하이닉스반도체 | 클럭킹 모드를 구비하는 반도체 메모리장치 및 이의 동작방법 |
| KR20100053202A (ko) * | 2008-11-12 | 2010-05-20 | 삼성전자주식회사 | Rdbi 기능을 지원하는 반도체 메모리 장치 및 그 테스트 방법 |
| KR100974223B1 (ko) * | 2008-11-13 | 2010-08-06 | 주식회사 하이닉스반도체 | 데이터 버스 인버전 기능을 갖는 반도체 집적회로 |
-
2010
- 2010-04-12 US US12/758,301 patent/US8260992B2/en active Active
-
2011
- 2011-04-05 WO PCT/US2011/031221 patent/WO2011130059A1/en not_active Ceased
- 2011-04-05 CN CN201180028766.5A patent/CN102934098B/zh active Active
- 2011-04-05 EP EP11717063.9A patent/EP2558945B1/en active Active
- 2011-04-05 JP JP2013504943A patent/JP5680184B2/ja not_active Expired - Fee Related
- 2011-04-05 KR KR1020127026440A patent/KR101875098B1/ko active Active
- 2011-04-11 TW TW100112428A patent/TWI518512B/zh active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201202938A (en) | 2012-01-16 |
| TWI518512B (zh) | 2016-01-21 |
| EP2558945A1 (en) | 2013-02-20 |
| KR101875098B1 (ko) | 2018-07-06 |
| US8260992B2 (en) | 2012-09-04 |
| WO2011130059A1 (en) | 2011-10-20 |
| CN102934098A (zh) | 2013-02-13 |
| CN102934098B (zh) | 2015-08-05 |
| US20110252171A1 (en) | 2011-10-13 |
| EP2558945B1 (en) | 2014-12-10 |
| JP2013524383A (ja) | 2013-06-17 |
| KR20130045257A (ko) | 2013-05-03 |
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