Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/14—Handling requests for interconnection or transfer
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

• the disclosed subject matter relates generally to computing systems and, more particularly, to a method and apparatus for reducing simultaneous switching outputs using data bus inversion signaling.
• dynamic memory devices are used to store large amounts of data for use by a processor or other computing device during its operation. Data is transferred between the computing device and the memory device over a memory bus.
• DDR double data rate
• SDRAM synchronous dynamic random access memory
• Data bus inversion is an I/O signaling technique that aims to reduce DC power consumption by selectively inverting the data bus for systems where the power consumed between alternate signaled states is asymmetric.
• the device communicating the data i.e., the processor for a write operation or the memory device for a read operation
• counts the number of 0s driven on a bus during a bit transfer time and if more than half the bus is electrical 0, the bus state is inverted.
• a DBI indicator bit is toggled to indicate that bus inversion has occurred. If the number of 0s and 1 s in the bit transfer time are less than or equal to half the bus width, no inversion takes place.
• Bus inversion may also be used in the case of address lines.
• data bus inversion applies generically to any type of bus inversion, such as DQ buses or address buses.
• DBI also has the property of reducing simultaneous switching outputs (SSO), defined as the absolute value of the number outputs that change to 1 minus the number of outputs that change to 0 in two consecutive bit time transfers.
• SSO simultaneous switching outputs
• the transmitted DBI bit is defined as 1 for no inversion and 0 for inversion. If all bit transfer times require inversion (e.g., a stream of 0s, which would be inverted to 1 s), and the DBI vector is transmitted after the last data transfer time, the system sees a worst case SSO transition where the last data transfer is all 1 s and the DBI bit transfer is all 0s.
• SSO simultaneous switching outputs
• a controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
• Another aspect of the disclosed subject matter is seen in a method including communicating a plurality of data transfers over a plurality of data lines defining a data bus using a plurality of data time slots, communicating a data bus inversion indicator for at least a subset of the data time slots indicating that bits communicated during the associated data time slot are inverted, wherein the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and communicating a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
• Figure 1 is a simplified block level diagram of a microprocessor interfaced with external memory
• Figure 2 is simplified block diagram illustrating the interface between a memory controller and a memory in the system of Figure 1 ;
• Figures 3-5 are diagrams illustrating data transfers using a sideband DBI signaling technique
• Figure 6 is a simplified block diagram of an alternative embodiment of an interface between the memory controller and the memory in the system of Figure 1 ;
• Figure 7 is a diagram illustrating data transfers using a global DBI signaling technique
• the microprocessor 100 employs a pair of substantially similar modules, module A 1 10 and module B 1 15.
• the modules 1 10, 1 15 include similar processing capabilities.
• the modules 1 10, 1 15 engage in processing under the control of software, and thus access memory, such as external memory 105 and/or caches, such as a shared L3 cache 120 and/or internal caches (not shown).
• An integrated memory controller 125 is provided to interface the modules 1 10, 1 15 with the external memory 105 over a memory bus 130.
• each of the modules 1 10, 1 15 may include additional circuitry for performing other useful tasks.
• the memory bus 130 includes data lines (DQ), address lines (AD), and control lines (CTL), such as chip select (CS), write enable (WE), bank select (BS), column access strobe (CAS), row access strobe (RAS), data mask (DM), and clock (CLK).
• DQ data lines
• AD address lines
• CTL control lines
• CS chip select
• WE write enable
• BS bank select
• CAS column access strobe
• RAS row access strobe
• DM data mask
• CLK clock
• the external memory 105 is a double data rate (DDR) memory, where data may be transferred on both rising and falling edges of the clock signal.
• DDR double data rate
• the integrated memory controller 125 and the external memory 105 communicate using a data bus inversion (DBI) scheme, where the bits driven on the DQ lines and/or address lines may be inverted to reduce the power consumption of the device or reduce noise by limiting the number of simultaneously switching outputs (SSO).
• DBI data bus inversion
• SSO simultaneously switching outputs
• the following examples relate to the inversion of the DQ lines, however, the concepts may be applied to any bus, such as an address bus.
• data transfers occupy n time slots, and the data bus inversion is controlled by an n-bit DBI vector, where each bit in the vector indicates whether the associated bits in the time slot have been inverted.
• DBIG global DBI
• DBIG global DBI
• the global DBI bit may be communicated within the data time slots, while in other embodiments, the global DBI bit may be communicated using a sideband signal (i.e., outside the bits of the data transfer).
• a first topology for communicating a global DBI control bit using a side band signal is illustrated.
• the external memory 105 has an 8-bit data bus and that a data transfer is implemented using 8 data time slots, 1 DBI control time slot, and 1 cyclic redundancy check (CRC) time slot.
• CRC cyclic redundancy check
• a bit value of "1 " is the low power state for the external memory 105.
• a data mask (DM) line 135 is used during write operations to indicate when data on the DQ lines 140 is valid. If the DM bit is asserted for a data slot, the data is ignored.
• the DM line 135 is typically unused during a read operation.
• the DM line 135 is used in a bidirectional manner to communicate DBI signaling information, as illustrated in Figure 3 for a write operation and as illustrated in Figures 4 or 5 for a read operation.
• data time slots 0-7 are implemented conventionally, where the DM bit is used to selectively mask the bytes being written.
• a DBI vector 145 is communicated on the DQ lines 140 indicating whether the bytes in the previous data slots had been inverted.
• a global DBI bit (DBIG) 150 is communicated using the DM line 135.
• DBIG bit 150 is asserted, the external memory 105 is signaled that the DBI vector 145 has itself been inverted.
• a controller in the external memory 105 inverts the DBI vector 145 and then uses the inverted values for processing the bytes in the data time slots.
• data transfer slots 0-7 are implemented conventionally, and the DM bit is unused (i.e., held at the low power state of "1 ".
• the DBI vector 145 is communicated on the DQ lines 140 to indicate whether the bytes in the previous data time slots have been inverted.
• the global DBI bit (DBIG) 150 is communicated using the DM line 135 during the DBI time slot 8.
• the memory controller 125 if the DBIG bit 150 is asserted, the memory controller 125 is signaled that the DBI vector 145 has itself been inverted.
• the memory controller 125 inverts the DBI vector 145 and then uses the inverted values for processing the bytes in the data time slots.
• Figure 5 illustrates an alternative embodiment of a read operation, where data time slots 0-7 are implemented conventionally, but the DM line 135 is used to communicate the DBI vector 145.
• data slot 8 the CRC data is sent, and the DBIG bit 150 is communicated using the DM line 135.
• the external memory 105 may include a bank of two 4-bit DDR memories 155, 160 grouped an 8-bit arrangement.
• the memory 155 is designated as an even bank
• the memory 160 is designated as an odd bank through the use of mode registers.
• the DQ lines 140 of the even bank 155 and those of the odd bank 160 are interleaved by bank. This interleaving pattern repeats for additional banks.
• data mask lines are not typically available for the memories 155, 160, so there is no sideband pin for sending a global DBI signal.
• the number of data slots for which DBI is implemented is reduced, and the global DBI bit 150 is sent over the DQ lines 140 along with a reduced DBI vector 165, 170 for each memory 155, 160.
• each DBI vector 165, 170 only covers 6 time slots.
• the DBI vector 165 for the even mode memory 155 implements DBI for data slots 0-5, and the odd mode memory implements DBI for data slots 2-7.
• the nibbles in time slots 6 and 7 for the even mode memory 155 and nibbles in time slots 0 and 1 for the odd mode memory 160 are never inverted.
• the DBI vectors 165, 170 are communicated over control time slots 8 and 9.
• a global DBI vector 175, 180 is also sent in control time slots 8 and 9, with a DBIA bit indicating if the time slot 8 portion of the DBI vector 165, 170 has been inverted, and a DBIB bit indicating if the time slot 9 portion of the DBI vector 165, 170 has been inverted.
• the DBI signaling techniques described herein enable DBI with minimum SSO.
• the SSO is less than 4.
• the SSO is a maximum of 6 over 8 bits. Reducing power consumption has the potential to reduce cooling requirements and extend battery life. Reducing SSO improves noise performance, which may have the potential to increase the maximum frequency at which the memory bus operates.
• An apparatus in accordance with one embodiment of the present subject matter includes a plurality of data lines defining a data bus for communicating data.
• a controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
• the apparatus may further include a signal line, and the controller may be operable to communicate the global data bus inversion indicator over the signal line.
• the signal line may be a data mask line.
• the data bus inversion vector may be communicated over the data lines in a control time slot other than the plurality of data time slots, and the controller may be operable to communicate data mask information over the data mask line for the data transfers during a write operation and communicate the global data bus inversion indicator over the data mask line during the control time slot.
• the controller may be operable to communicate the global data bus inversion indicator over the data mask line during the control time slot.
• the data bus inversion vector may be communicated over the data lines in a control time slot other than the plurality of data time slots, and the controller may be operable to communicate the global data bus inversion indicator over the data mask line during the control time slot.
• the data bus inversion vector may be communicated over the data lines in a control time slot other than the plurality of data time slots.
• the global data bus inversion indicator may be communicated over the data lines during the control time slot.
• the data lines may be grouped into a first group and a second group.
• the data bus inversion vector may have a first portion associated with the first group and a second portion associated with the second group. The first portion covers the first subset of the data time slots, the second portion covers a second subset of the time slots, and the data time slots not included in the first subset do not overlap the data time slots not included in the second subset.
• the first group may be associated with a first memory and the second group may be associated with a second memory.
• the controller may be a memory controller.
• the controller may be integrated into a memory device.
• the apparatus may also include a processor and a memory.
• the plurality of data lines may connect the processor to the memory.
• the data bus may be an address bus.
• a method in accordance with another embodiment of the present subject matter may include communicating a plurality of data transfers over a plurality of data lines defining a data bus using a plurality of data time slots, communicating a data bus inversion indicator for at least a subset of the data time slots indicating that bits communicated during the associated data time slot are inverted, wherein the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and communicating a global data bus inversion indicator indicating an inversion of the data bus inversion vector.
• Communicating the global data bus inversion indicator may include communicating the global data bus inversion indicator using at least one of the data lines.
• the data bus inversion vector may cover less than a total number of the data time slots, and the global data bus inversion indicator may be communicated with the data bus inversion vector during at least one control time slot.
• Communicating the global data bus inversion indicator may include communicating the global data bus inversion indicator using a signal line associated with the data bus other than the data lines.

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• 2010
  • 2010-04-12 US US12/758,301 patent/US8260992B2/en active Active
• 2011
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