WO2002039290A2 - Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion - Google Patents
Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion Download PDFInfo
- Publication number
- WO2002039290A2 WO2002039290A2 PCT/US2001/031816 US0131816W WO0239290A2 WO 2002039290 A2 WO2002039290 A2 WO 2002039290A2 US 0131816 W US0131816 W US 0131816W WO 0239290 A2 WO0239290 A2 WO 0239290A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- bits
- inversion signal
- inversion
- bus
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
Definitions
- the present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of reducing simultaneous switching output noise on a data bus.
- simultaneous switching output noise This noise results from several to many output drivers on a particular device switching states at the same time.
- One example of this may include a system logic device driving 32 bits of data at once to a graphics device over a graphics bus.
- the system logic device may drive 32 bits of "P's during one clock period and then drive 32 bits of "0"s during the next clock period, h this example all of the graphics bus bits change state from one clock period to the next.
- Such transitions may induce simultaneous switching output noise on some or all of the 32 data lines and limit the possible clock frequency for the graphics bus, thereby limiting the potential performance of the graphics subsystem.
- Figure 1 is a block diagram of an embodiment of a system including a system logic device having a dynamic bus inversion encoder and a graphics device having a dynamic bus inversion decoder.
- Figure 2 is a block diagram of an embodiment of a dynamic bus inversion encoder.
- Figure 3 is a flow diagram of an embodiment of a method for reducing simultaneous switching output noise using dynamic bus inversion.
- FIG. 1 is a block diagram of an embodiment of a system 100 including a system logic device 120 having a dynamic bus inversion (DBI) encoder 200 and a graphics device 130 having a DBI decoder 124.
- the system 100 also includes a processor 110 coupled to the system logic device 120.
- the system logic device is further coupled to a system memory 140 and an input/output hub 150.
- DBI dynamic bus inversion
- the system logic device 120 is coupled to the graphics device 130 by way of an output data bus 203 and an inversion signal 205.
- the DBI encoder 200 compares a set of data bits previously placed on the output data bus 203 with a next set of data bits to be placed on the data bus 203.
- the DBI encoder 200 determines how many data bit transitions would occur on the data bus 203 as a result of the next set of data bits being driven on the data bus 203 following the previous set of data bits. If the number of potential data bit transitions is greater than a predetermined number, then the DBI encoder 200 inverts each data bit in the next set of data bits and drives the inverted data onto the output data bus 203.
- the DBI encoder 200 asserts the inversion signal 205 to indicate to the DBI decoder 124 that the data bits have been inverted.
- the DBI decoder 124 then inverts the inverted data bits in order to restore the original data.
- the predetermined number is selected to produce the fewest bit transitions.
- the predetermined number is selected to equal one half of the data width. For example, for a group of 16 bits of data, the predetermined number would be 8. Therefore, if more than 8 data bits would change state, the data bits are inverted and the inversion signal is asserted.
- the DBI embodiment described above reduces the amount of simultaneous switching output noise by limiting the number of bit transitions occurring on the output data bus.
- An embodiment of the decoder 124 includes an XOR circuit that performs an XOR function on the incoming data and the inversion signal. In this manner, if no inversion is indicated (the inversion signal 205 is a "0") then the incoming data is not inverted by the decoder 124. If an inversion is indicated (the inversion signal 205 is a "1") then each bit of incoming data is inverted by the decoder 124 in order to restore the original data.
- system 100 shows a single data bus and a single inversion signal
- the data bus 203 may be divided into two or more groups. For example, a 32 bit bus may be divided into two groups of 16 bits each. Other configurations are possible. Inversion decisions are then made by the encoder 200 on a group-by-group basis. Each group utilizes its own inversion signal.
- Figure 2 is a block diagram of an embodiment of the dynamic bus inversion encoder 200.
- Data to be delivered over the output data bus 203 is delivered to the encoder 200 via an internal data bus 201.
- the internal data bus 201 and the output data bus 203 are 16 bits wide.
- Other embodiments are possible with a data width of 32 bits organized into two groups of 16 bits each.
- Still other embodiments are possible with other data organizations and groupings.
- the internal data 201 is delivered to both an XOR circuit 210 and an inverter
- the XOR circuit 210 also receives output data 203.
- the output data 203 represents a current set of data bits.
- An XOR operation is performed on the input data 201 and the output data 203.
- An inversion determination circuit 240 receives the output of the XOR operation and determines whether the number of data bit transitions found by the XOR operation exceeds a predetermined number.
- the predetermined number is eight. Other embodiments are possible using other predetermined numbers. It is also possible to implement the encoder 200 using a programmable predetermined number. If the inversion determination circuit 240 determines that the number of data bit transitions exceeds the predetermined number, an internal inversion signal 209 is asserted. The internal inversion signal 209 is delivered to the multiplexor 230 and a latch
- the multiplexor 230 delivers the output of the inverter circuit 220 to a latch 250. If the internal inversion signal is not asserted, then the multiplexor 230 delivers the non-inverted internal data to the latch 250. The latch 250 then latches the output of the multiplexor 230 onto the output data bus 203. The internal inversion signal 209 is latched onto the inversion signal 205.
- the inverter 220/multiplexor 230 combination may be implemented as an XOR circuit where the internal data bus bits 201 are each XORed with the internal inversion signal 209.
- the internal inversion signal 209 When the internal inversion signal 209 is asserted, then each of the internal data bits 201 are inverted and delivered to the input of the latch 250. If the internal inversion signal 209 is not asserted, then the XOR operation will leave the internal data bits 201 unchanged.
- Figure 3 is a flow diagram of an embodiment of a method for reducing simultaneous switching output noise using dynamic bus inversion.
- a first n bits of data are delivered over a data bus.
- the number of bit transitions between the first n bits of data and a second n bits of data are counted at block 320.
- the next n bits of data are inverted at block 340.
- the inverted next n bits of data are delivered over the data bus at block 360.
- An inversion signal is also asserted at block 360. If the counted bit transitions do not exceed the predetermined number, then the next n bits of data are delivered over the data bus at block 350.
- the preceding embodiment of a method may be repeated for every subsequent n bits of data to be delivered over the data bus.
- n equals 16 and the predetermined number is eight, although other embodiments are possible using other data widths and predetermined numbers.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0312605A GB2387943A (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
DE10196834T DE10196834T1 (en) | 2000-11-07 | 2001-10-12 | Method and device for reducing simultaneous switching output noise using dynamic bus inversion |
KR10-2003-7006227A KR20040012677A (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
AU2002211646A AU2002211646A1 (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US70822100A | 2000-11-07 | 2000-11-07 | |
US09/708,221 | 2000-11-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002039290A2 true WO2002039290A2 (en) | 2002-05-16 |
WO2002039290A3 WO2002039290A3 (en) | 2003-04-03 |
Family
ID=24844882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/031816 WO2002039290A2 (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
Country Status (6)
Country | Link |
---|---|
KR (1) | KR20040012677A (en) |
CN (1) | CN1483166A (en) |
AU (1) | AU2002211646A1 (en) |
DE (1) | DE10196834T1 (en) |
GB (1) | GB2387943A (en) |
WO (1) | WO2002039290A2 (en) |
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1380961A1 (en) * | 2002-07-10 | 2004-01-14 | STMicroelectronics S.r.l. | Process and device for reducing bus switching activity and computer program product therefor |
EP1403774A1 (en) * | 2002-09-25 | 2004-03-31 | STMicroelectronics S.r.l. | Process and devices for transmitting digital signals over buses and computer program product therefor |
EP1403775A1 (en) * | 2002-09-25 | 2004-03-31 | STMicroelectronics S.r.l. | Process and devices for transmiting digital signals over buses and computer program product therefor |
EP1406388A2 (en) * | 2002-10-05 | 2004-04-07 | SAMSUNG ELECTRONICS Co. Ltd. | Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data |
GB2394088A (en) * | 2002-08-21 | 2004-04-14 | Nec Corp | Output circuit and method that inverts the data byte if the number of changed bits compared with the last byte is more than half the total number of bits. |
WO2006000944A1 (en) * | 2004-06-21 | 2006-01-05 | Koninklijke Philips Electronics N.V. | Data processing system and method for interconnect arbitration |
WO2007093906A1 (en) * | 2006-02-17 | 2007-08-23 | Ati Technologies, Inc | Dynamic bus inversion method and system |
US7408482B2 (en) | 2003-03-26 | 2008-08-05 | Samsung Electronics Co., Ltd. | Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same |
US7466608B2 (en) | 2005-11-08 | 2008-12-16 | Samsung Electronics Co., Ltd. | Data input/output circuit having data inversion determination function and semiconductor memory device having the same |
US7764792B1 (en) * | 2005-01-13 | 2010-07-27 | Marvell International Ltd. | System and method for encoding data transmitted on a bus |
CN101788967A (en) * | 2010-03-09 | 2010-07-28 | 西安电子科技大学 | Encoding and decoding method for crosstalk resistant on-chip bus and encoding and decoding device thereof |
WO2011130059A1 (en) * | 2010-04-12 | 2011-10-20 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
CN103885913A (en) * | 2014-03-26 | 2014-06-25 | 中国科学院声学研究所 | Bus encoding and decoding device and method thereof |
Families Citing this family (8)
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KR100877680B1 (en) * | 2006-04-04 | 2009-01-09 | 삼성전자주식회사 | Method and Computer readable recording media, and apparatus for interfacing between semiconductor devices using single ended parallel interface system |
KR100782327B1 (en) | 2006-05-27 | 2007-12-06 | 삼성전자주식회사 | Method and Computer readable recording media, and apparatus for interfacing between semiconductor devices using single ended parallel interface system |
US8552891B2 (en) | 2006-05-27 | 2013-10-08 | Samsung Electronics Co., Ltd. | Method and apparatus for parallel data interfacing using combined coding and recording medium therefor |
US7688102B2 (en) | 2006-06-29 | 2010-03-30 | Samsung Electronics Co., Ltd. | Majority voter circuits and semiconductor devices including the same |
KR100845141B1 (en) * | 2007-01-17 | 2008-07-10 | 삼성전자주식회사 | Single rate interface device, dual rate interface device and dual rate interfacing method |
KR20160058503A (en) * | 2014-11-17 | 2016-05-25 | 에스케이하이닉스 주식회사 | Semiconductor Memory Apparatus |
US10623200B2 (en) * | 2018-07-20 | 2020-04-14 | Nvidia Corp. | Bus-invert coding with restricted hamming distance for multi-byte interfaces |
US10963405B2 (en) | 2019-03-29 | 2021-03-30 | Intel Corporation | Minimum input/output toggling rate for interfaces |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0520650A1 (en) * | 1991-06-19 | 1992-12-30 | AT&T Corp. | Low power signaling using gray codes |
US5960468A (en) * | 1997-04-30 | 1999-09-28 | Sony Corporation | Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0969075A (en) * | 1995-08-31 | 1997-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Bus circuit |
-
2001
- 2001-10-12 DE DE10196834T patent/DE10196834T1/en not_active Withdrawn
- 2001-10-12 AU AU2002211646A patent/AU2002211646A1/en not_active Abandoned
- 2001-10-12 KR KR10-2003-7006227A patent/KR20040012677A/en not_active Application Discontinuation
- 2001-10-12 CN CNA018183921A patent/CN1483166A/en active Pending
- 2001-10-12 WO PCT/US2001/031816 patent/WO2002039290A2/en not_active Application Discontinuation
- 2001-10-12 GB GB0312605A patent/GB2387943A/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0520650A1 (en) * | 1991-06-19 | 1992-12-30 | AT&T Corp. | Low power signaling using gray codes |
US5960468A (en) * | 1997-04-30 | 1999-09-28 | Sony Corporation | Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 07, 31 July 1997 (1997-07-31) & JP 09 069075 A (NIPPON TELEGR &TELEPH CORP <NTT>), 11 March 1997 (1997-03-11) * |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
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US6933863B2 (en) | 2002-07-10 | 2005-08-23 | Stmicroelectronics S.R.L. | Process and device for reducing bus switching activity and computer program product therefor |
EP1380961A1 (en) * | 2002-07-10 | 2004-01-14 | STMicroelectronics S.r.l. | Process and device for reducing bus switching activity and computer program product therefor |
GB2394088B (en) * | 2002-08-21 | 2005-10-12 | Nippon Electric Co | Data output circuit and data output method |
US6946867B2 (en) | 2002-08-21 | 2005-09-20 | Nec Corporation | Data output circuit and data output method |
GB2394088A (en) * | 2002-08-21 | 2004-04-14 | Nec Corp | Output circuit and method that inverts the data byte if the number of changed bits compared with the last byte is more than half the total number of bits. |
US7372916B2 (en) | 2002-09-25 | 2008-05-13 | Stmicroelectronics S.R.L | Process and devices for transmitting digital signals over buses and computer program product therefore |
EP1403775A1 (en) * | 2002-09-25 | 2004-03-31 | STMicroelectronics S.r.l. | Process and devices for transmiting digital signals over buses and computer program product therefor |
US7991081B2 (en) | 2002-09-25 | 2011-08-02 | Stmicroelectronics S.R.L. | Process and devices for transmitting digital signals over buses and computer program product therefore |
US6943706B2 (en) | 2002-09-25 | 2005-09-13 | Stmicroelectronics S.R.L. | Process and devices for transmitting digital signals over buses and computer program product therefore |
EP1403774A1 (en) * | 2002-09-25 | 2004-03-31 | STMicroelectronics S.r.l. | Process and devices for transmitting digital signals over buses and computer program product therefor |
EP1406388A2 (en) * | 2002-10-05 | 2004-04-07 | SAMSUNG ELECTRONICS Co. Ltd. | Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data |
EP1406388A3 (en) * | 2002-10-05 | 2006-12-20 | SAMSUNG ELECTRONICS Co. Ltd. | Integrated circuit devices having data inversion circuits therein that reduce simultaneous switching noise and support interleaving of parallel data |
US7408482B2 (en) | 2003-03-26 | 2008-08-05 | Samsung Electronics Co., Ltd. | Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same |
WO2006000944A1 (en) * | 2004-06-21 | 2006-01-05 | Koninklijke Philips Electronics N.V. | Data processing system and method for interconnect arbitration |
US7698514B2 (en) | 2004-06-21 | 2010-04-13 | Nxp B.V. | Data processing system and method for interconnect arbitration |
US7764792B1 (en) * | 2005-01-13 | 2010-07-27 | Marvell International Ltd. | System and method for encoding data transmitted on a bus |
USRE45334E1 (en) * | 2005-01-13 | 2015-01-13 | Marvell International Ltd. | System and method for encoding data transmitted on a bus |
USRE44777E1 (en) | 2005-01-13 | 2014-02-25 | Marvell International Ltd. | System and method for encoding data transmitted on a bus |
US7869525B2 (en) | 2005-08-01 | 2011-01-11 | Ati Technologies, Inc. | Dynamic bus inversion method and system |
US7466608B2 (en) | 2005-11-08 | 2008-12-16 | Samsung Electronics Co., Ltd. | Data input/output circuit having data inversion determination function and semiconductor memory device having the same |
WO2007093906A1 (en) * | 2006-02-17 | 2007-08-23 | Ati Technologies, Inc | Dynamic bus inversion method and system |
EP2600578A1 (en) * | 2006-02-17 | 2013-06-05 | ATI Technologies Inc. | Dynamic bus inversion method and system |
CN101788967A (en) * | 2010-03-09 | 2010-07-28 | 西安电子科技大学 | Encoding and decoding method for crosstalk resistant on-chip bus and encoding and decoding device thereof |
US8260992B2 (en) | 2010-04-12 | 2012-09-04 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
WO2011130059A1 (en) * | 2010-04-12 | 2011-10-20 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
CN103885913A (en) * | 2014-03-26 | 2014-06-25 | 中国科学院声学研究所 | Bus encoding and decoding device and method thereof |
Also Published As
Publication number | Publication date |
---|---|
AU2002211646A1 (en) | 2002-05-21 |
GB2387943A (en) | 2003-10-29 |
CN1483166A (en) | 2004-03-17 |
DE10196834T1 (en) | 2003-11-13 |
WO2002039290A3 (en) | 2003-04-03 |
GB0312605D0 (en) | 2003-07-09 |
KR20040012677A (en) | 2004-02-11 |
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