AU2002211646A1 - Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion - Google Patents
Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversionInfo
- Publication number
- AU2002211646A1 AU2002211646A1 AU2002211646A AU1164602A AU2002211646A1 AU 2002211646 A1 AU2002211646 A1 AU 2002211646A1 AU 2002211646 A AU2002211646 A AU 2002211646A AU 1164602 A AU1164602 A AU 1164602A AU 2002211646 A1 AU2002211646 A1 AU 2002211646A1
- Authority
- AU
- Australia
- Prior art keywords
- switching output
- output noise
- simultaneous switching
- bus inversion
- dynamic bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US70822100A | 2000-11-07 | 2000-11-07 | |
US09/708,221 | 2000-11-07 | ||
PCT/US2001/031816 WO2002039290A2 (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2002211646A1 true AU2002211646A1 (en) | 2002-05-21 |
Family
ID=24844882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2002211646A Abandoned AU2002211646A1 (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
Country Status (6)
Country | Link |
---|---|
KR (1) | KR20040012677A (en) |
CN (1) | CN1483166A (en) |
AU (1) | AU2002211646A1 (en) |
DE (1) | DE10196834T1 (en) |
GB (1) | GB2387943A (en) |
WO (1) | WO2002039290A2 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1380961B1 (en) * | 2002-07-10 | 2006-04-05 | STMicroelectronics S.r.l. | Process and device for reducing bus switching activity and computer program product therefor |
JP2004080553A (en) * | 2002-08-21 | 2004-03-11 | Nec Corp | Circuit and method for data output |
EP1403775B1 (en) * | 2002-09-25 | 2006-03-08 | STMicroelectronics S.r.l. | Process and devices for transmiting digital signals over buses and computer program product therefor |
EP1403774B1 (en) | 2002-09-25 | 2007-07-25 | STMicroelectronics S.r.l. | Process and devices for transmitting digital signals over buses and computer program product therefor |
KR100459726B1 (en) * | 2002-10-05 | 2004-12-03 | 삼성전자주식회사 | Data inversion circuit of multi-bit pre-fetch semiconductor device and method there-of |
US6992506B2 (en) | 2003-03-26 | 2006-01-31 | Samsung Electronics Co., Ltd. | Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same |
WO2006000944A1 (en) * | 2004-06-21 | 2006-01-05 | Koninklijke Philips Electronics N.V. | Data processing system and method for interconnect arbitration |
US7764792B1 (en) * | 2005-01-13 | 2010-07-27 | Marvell International Ltd. | System and method for encoding data transmitted on a bus |
US7869525B2 (en) | 2005-08-01 | 2011-01-11 | Ati Technologies, Inc. | Dynamic bus inversion method and system |
KR100621353B1 (en) | 2005-11-08 | 2006-09-07 | 삼성전자주식회사 | Data in-out put circuit with verification for data inversion and semiconductor memory device having the same |
KR100877680B1 (en) * | 2006-04-04 | 2009-01-09 | 삼성전자주식회사 | Method and Computer readable recording media, and apparatus for interfacing between semiconductor devices using single ended parallel interface system |
US8552891B2 (en) | 2006-05-27 | 2013-10-08 | Samsung Electronics Co., Ltd. | Method and apparatus for parallel data interfacing using combined coding and recording medium therefor |
KR100782327B1 (en) | 2006-05-27 | 2007-12-06 | 삼성전자주식회사 | Method and Computer readable recording media, and apparatus for interfacing between semiconductor devices using single ended parallel interface system |
US7688102B2 (en) | 2006-06-29 | 2010-03-30 | Samsung Electronics Co., Ltd. | Majority voter circuits and semiconductor devices including the same |
KR100845141B1 (en) | 2007-01-17 | 2008-07-10 | 삼성전자주식회사 | Single rate interface device, dual rate interface device and dual rate interfacing method |
CN101788967B (en) * | 2010-03-09 | 2012-02-08 | 西安电子科技大学 | Encoding and decoding method for crosstalk resistant on-chip bus and encoding and decoding device thereof |
US8260992B2 (en) * | 2010-04-12 | 2012-09-04 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
CN103885913B (en) * | 2014-03-26 | 2017-01-04 | 中国科学院声学研究所 | Bus coding and decoding device and method thereof |
KR20160058503A (en) * | 2014-11-17 | 2016-05-25 | 에스케이하이닉스 주식회사 | Semiconductor Memory Apparatus |
US10623200B2 (en) * | 2018-07-20 | 2020-04-14 | Nvidia Corp. | Bus-invert coding with restricted hamming distance for multi-byte interfaces |
US10963405B2 (en) | 2019-03-29 | 2021-03-30 | Intel Corporation | Minimum input/output toggling rate for interfaces |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0520650A1 (en) * | 1991-06-19 | 1992-12-30 | AT&T Corp. | Low power signaling using gray codes |
JPH0969075A (en) * | 1995-08-31 | 1997-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Bus circuit |
US5960468A (en) * | 1997-04-30 | 1999-09-28 | Sony Corporation | Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters |
-
2001
- 2001-10-12 AU AU2002211646A patent/AU2002211646A1/en not_active Abandoned
- 2001-10-12 GB GB0312605A patent/GB2387943A/en not_active Withdrawn
- 2001-10-12 CN CNA018183921A patent/CN1483166A/en active Pending
- 2001-10-12 KR KR10-2003-7006227A patent/KR20040012677A/en not_active Application Discontinuation
- 2001-10-12 DE DE10196834T patent/DE10196834T1/en not_active Withdrawn
- 2001-10-12 WO PCT/US2001/031816 patent/WO2002039290A2/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
GB0312605D0 (en) | 2003-07-09 |
GB2387943A (en) | 2003-10-29 |
WO2002039290A2 (en) | 2002-05-16 |
CN1483166A (en) | 2004-03-17 |
WO2002039290A3 (en) | 2003-04-03 |
DE10196834T1 (en) | 2003-11-13 |
KR20040012677A (en) | 2004-02-11 |
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