CN1483166A - Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion - Google Patents
Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion Download PDFInfo
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- CN1483166A CN1483166A CNA018183921A CN01818392A CN1483166A CN 1483166 A CN1483166 A CN 1483166A CN A018183921 A CNA018183921 A CN A018183921A CN 01818392 A CN01818392 A CN 01818392A CN 1483166 A CN1483166 A CN 1483166A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
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- Dc Digital Transmission (AREA)
Abstract
An embodiment of a computer system implementing dynamic bus inversion includes a first system logic device having a dynamic bus inversion encoder and also includes a second system logic device having a dynamic bus inversion decoder. The first and second system logic devices are coupled via a data bus. The encoder compares a group of data bits currently placed on the data bus with a next group of data bits to be placed on the data bus. If the encoder determines that greater than a predetermined number of bit transitions would occur between the current and next group of data bits, the encoder inverts the next group of data bits before placing the next group of data bits onto the data bus. The encoder also asserts an inversion signal that is received by the decoder. In response to the assertion of the inversion signal, the decoder inverts the previously inverted next group of data bits to restore the original data.
Description
Invention field
The present invention relates to field of computer, relate in particular to the field that reduces the simultaneous switching output noise on the data bus.
Background technology
In making great efforts to improve the process of computer system performance now, the system designer manages to improve the clock frequency of various system data buss.Because bus frequency has improved, the noise on the data line becomes an important problem further.The corresponding shortening of the raising of clock frequency and its clock period, this made before receiving end receives data to have only the shorter time to solve the noise problem that appears on the data line.Noise on the data line may cause having latched invalid data when the receiving end latch data.
A noise source on the data line may be the synchro switch output noise.This noise may be all to be in the specific device on off state by several or a plurality of output driving devices at synchronization to be caused.An one example can comprise a system logical unit, and this device is sent to 32 bit data on the graphics device simultaneously by a graphics bus.This system logical unit may send 32 " 1 " in a clock period, and sends 32 " 0 " in the next clock period.In this example, all graphics bus data bit is changed to the next clock period with state from a clock period.Such variation can reduce the synchro switch output noise on some or all 32 position datawires, and can limit the possible clock frequency of graphics bus, thereby has limited the potential performance of graphics subsystem.
Description of drawings
Accompanying drawing by the following detailed description and the embodiment of the invention can more fully be understood the present invention, yet the present invention is not limited in the description of specific embodiment, and the embodiment accompanying drawing only is used for explanation and the present invention is understood in help.
Accompanying drawing 1 is the block scheme of the embodiment of a system, and this system comprises a system logical unit and a graphics device, and this system logical unit has a dynamic bus inversion scrambler, and this graphics device has a dynamic bus inversion demoder.
Accompanying drawing 2 is block schemes of the embodiment of dynamic bus inversion scrambler.
Accompanying drawing 3 is to adopt the process flow diagram of dynamic bus inversion with the embodiment of the method for minimizing synchro switch output noise.
Embodiment
Accompanying drawing 1 is the block scheme of the specific embodiment of system 100, system 100 comprises a system logical unit 120 and a graphics device 130, this system logical unit 120 has a dynamic bus inversion (DBI) scrambler 200, and this graphics device 130 has a DBI demoder 124.System 100 also comprises a processor 110 that is coupled with system logical unit 120.This system logical unit 120 also is coupled with a system storage 140 and an input/output wire collector 150.
System logical unit 120 is coupling-connected to graphics device 130 by an output data bus 203 and an inverted signal 205.DBI scrambler 200 is made comparisons the one group of data bit that is prepended to earlier on the output data bus 203 with next group data bit that will be placed on the data bus 203.How many data bit DBI scrambler 200 defines changes on data bus 203, and this transformation is to cause owing to next group data bit is sent on the data bus 203 after last group of data bit.The number that data bit is if possible changed is greater than a predetermined value, and DBI scrambler 200 is inverted each data bit in next group data bit and is sent the data that have been squeezed and arrives output data bus 203 so.DBI scrambler 200 gating inverted signals 205 are to show that to DBI demoder 124 data bit is squeezed.DBI demoder 124 is inverted the data bit that has been squeezed and is recovered raw data then.
Select predetermined value to produce minimum position conversion.In certain embodiments, the selection predetermined value is half of data bit width.For example, one group 16 data, predetermined value is 8.Therefore, if will change state more than 8 data bit, so data bit be squeezed and inverted signal by gating.
DBI embodiment as described above has reduced synchro switch output noise amount by the number that restriction occurs in the position conversion on the output data bus.
An embodiment of demoder 124 comprises an XOR circuit of input data and inverted signal being carried out an XOR (XOR) function.By this,, import the not decoded device 124 of data so and be inverted if be not inverted indication (inverted signal 205 is " 0 ").If the indication of inversion (inverted signal 205 is " 1 ") is arranged, import all decoded device 124 of each data bit of data so and be inverted so that recover raw data.
Though shown in the system 100 is individual data bus and single inverted signal, data bus 203 can be divided into two or more groups.For example, 32 buses can be divided into two groups, 16 every group.Other possible combination can also be arranged.The generation that scrambler is 200 1 groups one group the inversion result.Each group is used the inverted signal of controlling oneself.
Accompanying drawing 2 is block schemes of the embodiment of dynamic bus inversion scrambler 200.To transfer to scrambler 200 via internal data bus 201 by the data that output data bus 203 passes on.In this embodiment, internal data bus 201 and output data bus 203 all are 16 bit wides.In other embodiments, it is wide to be that the wide bus of 32 bit data is divided into two group of 16 bit data.Also having some other embodiment, may be other data combination and grouping.
Internal data 201 is transferred to an XOR circuit 210, is transferred to the combination of inversor 220/ traffic pilot 230 simultaneously.XOR circuit 210 also receives output data 203.One group of current data bit of output data 203 expressions.Input data 201 and output data 203 are carried out xor operation.One inversion confirms whether the output of circuit 240 reception xor operations and the number that definite data bit that is obtained by xor operation changes have surpassed predetermined value.In this embodiment, predetermined value is eight.In other embodiments, may be other predetermined value, also can utilize a programmable predetermined value to realize scrambler 200.Confirm that the data bit variable number exceed predetermined value if be inverted to confirm circuit 240, an inner inverted signal 209 is by gating so.
Inner inverted signal 209 is transferred to traffic pilot 230 and a latch 260.If inner inverted signal 209 gatings, expression surpasses the predetermined value that data bit changes, and what traffic pilot 230 passed on inverting circuit 220 so exports latch 250 to.If inner inverted signal does not have gating, traffic pilot 230 transmits and does not have inverted internal data to latch 250 so.What latch 250 latched traffic pilot 230 then outputs to output data bus 203.Inner inverted signal 209 is latching to inverted signal 205.
The available XOR circuit of inversor 220/ traffic pilot 230 combination realizes, in this XOR circuit, internal data bus 201 each with inner inverted signal 209 XOR mutually.When inner inverted signal 209 gatings, each of internal data 201 all is squeezed and transfers to the input end of latch 250 so.If inner inverted signal 209 does not have gating, xor operation does not change internal data position 201 so.
Accompanying drawing 3 is to adopt dynamic bus inversion to reduce the process flow diagram of embodiment of the method for synchro switch output noise.In block diagram 310, first group of n bit data passed on by data bus.At block diagram 320, calculate the position variable number between first group of n bit data and the second group of n bit data.Shown in block diagram 330, if changing, the position of calculating exceeds predetermined value, next group n bit data is squeezed in block diagram 340 so.In block diagram 360, next the group n bit data that is squeezed is passed on by data bus, and in block diagram 360, an inverted signal is also by gating.Do not exceed predetermined value if calculate bit map, in block diagram 350, next group n bit data is passed at data bus so.Repeat aforementioned concrete grammar and handle follow-up each the group n bit data that to pass on by data bus.For this embodiment, n equals 16, and predetermined value is 8, may adopt other data width and predetermined value in other embodiments.
Send data by a graphics bus to graphics device though mention a system logical unit among embodiment more discussed above, but in other embodiments, can be with any system and device as transmitter, with having other any device of DBI demoder as receiver with DBI scrambler.
In the above description, introduced the present invention with reference to example embodiment.Yet, obviously can carry out the various modifications and variations that do not depart from the described invention spirit and scope of claim.Therefore, this instructions and accompanying drawing are exemplary rather than determinate.
" embodiment " that mentions in the description, " embodiment ", " some embodiment " or " other embodiment " meaning is the description of specified features, structure or the characteristic relevant with embodiment, be included at least among some embodiment of invention, rather than all embodiment must have." embodiment ", various appellations such as " embodiment " or " some embodiment " change to differ establishes a capital the identical embodiment of finger.
Claims (26)
1. device comprises:
A position change detecting circuit, when next bus transaction is compared with current bus transaction, this circuit determines whether next bus transaction can cause changing greater than the position of predetermined number, if next bus transaction causes changing greater than the position of predetermined number when next bus transaction is compared with current bus transaction, so this change detecting circuit gating one inverted signal;
One inverting circuit is used to be inverted the position of next bus transaction to respond the gating of an inverted signal.
2. device as claimed in claim 1, institute's rheme testing circuit comprise that one first XOR circuit is to detect the number that the position changes between current bus transaction and next bus transaction.
3. device as claimed in claim 2, institute's rheme testing circuit comprises a circuit, this circuit is used for determining whether exceed predetermined number by the detected position variable number of first XOR circuit.
4. device as claimed in claim 3, described inverting circuit comprise second XOR circuit of carrying out the XOR function between next bus transaction and inverted signal.
5. device as claimed in claim 4, also comprise first latch that is used to latch the output of second XOR circuit, the output signal that first latch will latch offers an external data bus, and the output signal that further will latch offers first XOR circuit.
6. device as claimed in claim 5 also comprises one second latch, in order to latch inverted signal and the inverted signal that latchs is offered an outside inverted signal.
7. device as claimed in claim 6, described current and next bus transaction is 16 bit wides.
8. device as claimed in claim 7, the predetermined number that its meta changes is 8.
9. method comprises:
When next bus transaction is compared with current bus transaction, determine whether next bus transaction can cause changing greater than the position of predetermined number; And
The inversion result of next bus transaction is provided.
10. method as claimed in claim 9 also comprises providing an inverted signal to be squeezed to represent next bus transaction.
11. a method comprises:
Pass on first group of n bit data by data bus;
The position of calculating between first group of n bit data and the second group of n bit data changes;
Determine the position of being calculated changes whether exceed predetermined number;
Exceed predetermined number if the position of being calculated has changed, be inverted next group n bit data and gating one inverted signal;
Pass on next group n bit data by data bus.
12. method as claimed in claim 11, the step of wherein being inverted next group n position is included between next group n position and the inverted signal carries out an xor operation.
13. method as claimed in claim 12, wherein n is 16.
14. method as claimed in claim 13, wherein predetermined number is 8.
15. a system comprises:
A processor;
First logical unit that is coupled with processor, described system logical unit comprises a dynamic bus inversion scrambler, described dynamic bus inversion scrambler comprises
A position change detecting circuit, when being compared, next bus transaction and current bus transaction determine whether next bus transaction can cause changing greater than the position of predetermined number, if next bus transaction has caused changing greater than the position of predetermined number when next bus transaction and current bus transaction are compared, so position change detecting circuit gating one inverted signal; With
One inverting circuit is inverted to respond the gating of inverted signal the position of next bus transaction; And
Be coupled to second logical unit of first logical unit by a bus.
16. system as claimed in claim 15, institute's rheme testing circuit comprises that one first XOR circuit is to detect the number that the position changes between current bus transaction and next bus transaction.
17. system as claimed in claim 16, institute's rheme testing circuit comprises a circuit, and this circuit is used for determining whether the number that changes that first XOR circuit is detected has surpassed predetermined number.
18. system as claimed in claim 17, described inverting circuit comprises second XOR circuit of carrying out the XOR function between next bus transaction and inverted signal.
19. system as claimed in claim 17 also comprises first latch that is used to latch the output of second XOR circuit, first latch offers described bus with the output of being latched, and further the output of being latched is offered first XOR circuit.
20. system as claimed in claim 19 comprises that also one second latch is to latch inverted signal and the inverted signal that is latched is offered an outside inverted signal, outside inverted signal and the coupling of second logical unit.
21. system as claimed in claim 20, wherein second logical unit comprises a dynamic bus inversion demoder.
21. a device comprises:
The input of one data bus is used to receive the n bit data;
The input of one inverted signal is used to receive an inverted signal; With
One inverting circuit is if inverted signal by gating, is inverted the received n bit data of data bus input.
22. device as claimed in claim 21, described inverting circuit comprise an XOR circuit, carry out xor operation to import between received n bit data and the inverted signal at data bus.
23. device as claimed in claim 22, described n is 16.
24. a method comprises:
Receive the n bit data at receiving trap; With
Be inverted the n bit data to respond the gating of an inverted signal, this inverted signal is by the dispensing device gating.
25. method as claimed in claim 24 is wherein carried out inverted step to the n bit data and is included in XOR function of execution between n bit data and the inverted signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US70822100A | 2000-11-07 | 2000-11-07 | |
| US09/708,221 | 2000-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1483166A true CN1483166A (en) | 2004-03-17 |
Family
ID=24844882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA018183921A Pending CN1483166A (en) | 2000-11-07 | 2001-10-12 | Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion |
Country Status (6)
| Country | Link |
|---|---|
| KR (1) | KR20040012677A (en) |
| CN (1) | CN1483166A (en) |
| AU (1) | AU2002211646A1 (en) |
| DE (1) | DE10196834T1 (en) |
| GB (1) | GB2387943A (en) |
| WO (1) | WO2002039290A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609128A (en) * | 2014-11-17 | 2016-05-25 | 爱思开海力士有限公司 | Semiconductor memory apparatus and system including the same |
| CN110737620A (en) * | 2018-07-20 | 2020-01-31 | 辉达公司 | Bus flip coding with limited hamming distance for multi-byte interfaces |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1380961B1 (en) * | 2002-07-10 | 2006-04-05 | STMicroelectronics S.r.l. | Process and device for reducing bus switching activity and computer program product therefor |
| JP2004080553A (en) | 2002-08-21 | 2004-03-11 | Nec Corp | Circuit and method for data output |
| DE60209690D1 (en) * | 2002-09-25 | 2006-05-04 | St Microelectronics Srl | Method and apparatus for transmitting a digital signal over a computer bus and computer program product therefor |
| DE60221396D1 (en) | 2002-09-25 | 2007-09-06 | St Microelectronics Srl | Method and apparatus for transmitting digital signal over a computer bus and computer program product therefor |
| KR100459726B1 (en) * | 2002-10-05 | 2004-12-03 | 삼성전자주식회사 | Data inversion circuit of multi-bit pre-fetch semiconductor device and method there-of |
| US6992506B2 (en) | 2003-03-26 | 2006-01-31 | Samsung Electronics Co., Ltd. | Integrated circuit devices having data inversion circuits therein with multi-bit prefetch structures and methods of operating same |
| DE602005004408T2 (en) * | 2004-06-21 | 2008-05-21 | Nxp B.V. | DATA PROCESSING SYSTEM AND METHOD FOR CONNECTING ARBITRATION |
| US7764792B1 (en) | 2005-01-13 | 2010-07-27 | Marvell International Ltd. | System and method for encoding data transmitted on a bus |
| US7869525B2 (en) * | 2005-08-01 | 2011-01-11 | Ati Technologies, Inc. | Dynamic bus inversion method and system |
| KR100621353B1 (en) | 2005-11-08 | 2006-09-07 | 삼성전자주식회사 | Data in-out put circuit with verification for data inversion and semiconductor memory device having the same |
| KR100877680B1 (en) * | 2006-04-04 | 2009-01-09 | 삼성전자주식회사 | Method and Computer readable recording media, and apparatus for interfacing between semiconductor devices using single ended parallel interface system |
| US8552891B2 (en) | 2006-05-27 | 2013-10-08 | Samsung Electronics Co., Ltd. | Method and apparatus for parallel data interfacing using combined coding and recording medium therefor |
| KR100782327B1 (en) | 2006-05-27 | 2007-12-06 | 삼성전자주식회사 | Method and Computer readable recording media, and apparatus for interfacing between semiconductor devices using single ended parallel interface system |
| US7688102B2 (en) | 2006-06-29 | 2010-03-30 | Samsung Electronics Co., Ltd. | Majority voter circuits and semiconductor devices including the same |
| KR100845141B1 (en) | 2007-01-17 | 2008-07-10 | 삼성전자주식회사 | Single rate interface device, dual rate interface device and dual rate interfacing method |
| CN101788967B (en) * | 2010-03-09 | 2012-02-08 | 西安电子科技大学 | Encoding and decoding method for crosstalk resistant on-chip bus and encoding and decoding device thereof |
| US8260992B2 (en) * | 2010-04-12 | 2012-09-04 | Advanced Micro Devices, Inc. | Reducing simultaneous switching outputs using data bus inversion signaling |
| CN103885913B (en) * | 2014-03-26 | 2017-01-04 | 中国科学院声学研究所 | Bus coding and decoding device and method thereof |
| US10963405B2 (en) * | 2019-03-29 | 2021-03-30 | Intel Corporation | Minimum input/output toggling rate for interfaces |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0520650A1 (en) * | 1991-06-19 | 1992-12-30 | AT&T Corp. | Low power signaling using gray codes |
| JPH0969075A (en) * | 1995-08-31 | 1997-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Bus circuit |
| US5960468A (en) * | 1997-04-30 | 1999-09-28 | Sony Corporation | Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters |
-
2001
- 2001-10-12 CN CNA018183921A patent/CN1483166A/en active Pending
- 2001-10-12 GB GB0312605A patent/GB2387943A/en not_active Withdrawn
- 2001-10-12 AU AU2002211646A patent/AU2002211646A1/en not_active Abandoned
- 2001-10-12 KR KR10-2003-7006227A patent/KR20040012677A/en not_active Application Discontinuation
- 2001-10-12 DE DE10196834T patent/DE10196834T1/en not_active Withdrawn
- 2001-10-12 WO PCT/US2001/031816 patent/WO2002039290A2/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609128A (en) * | 2014-11-17 | 2016-05-25 | 爱思开海力士有限公司 | Semiconductor memory apparatus and system including the same |
| TWI668576B (en) * | 2014-11-17 | 2019-08-11 | 韓商愛思開海力士有限公司 | Semiconductor memory apparatus and system including the same |
| CN105609128B (en) * | 2014-11-17 | 2019-09-24 | 爱思开海力士有限公司 | Semiconductor storage and system including it |
| CN110737620A (en) * | 2018-07-20 | 2020-01-31 | 辉达公司 | Bus flip coding with limited hamming distance for multi-byte interfaces |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040012677A (en) | 2004-02-11 |
| WO2002039290A2 (en) | 2002-05-16 |
| GB0312605D0 (en) | 2003-07-09 |
| WO2002039290A3 (en) | 2003-04-03 |
| DE10196834T1 (en) | 2003-11-13 |
| GB2387943A (en) | 2003-10-29 |
| AU2002211646A1 (en) | 2002-05-21 |
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