USRE45334E1 - System and method for encoding data transmitted on a bus - Google Patents

System and method for encoding data transmitted on a bus Download PDF

Info

Publication number
USRE45334E1
USRE45334E1 US14/031,881 US201314031881A USRE45334E US RE45334 E1 USRE45334 E1 US RE45334E1 US 201314031881 A US201314031881 A US 201314031881A US RE45334 E USRE45334 E US RE45334E
Authority
US
United States
Prior art keywords
data
address
circuit
encoded data
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/031,881
Inventor
Amit Avivi
Aron Wohlgemuth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cavium International
Marvell Asia Pte Ltd
Original Assignee
Marvell International Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marvell International Ltd filed Critical Marvell International Ltd
Priority to US14/031,881 priority Critical patent/USRE45334E1/en
Application granted granted Critical
Publication of USRE45334E1 publication Critical patent/USRE45334E1/en
Assigned to CAVIUM INTERNATIONAL reassignment CAVIUM INTERNATIONAL ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MARVELL INTERNATIONAL LTD.
Assigned to MARVELL ASIA PTE, LTD. reassignment MARVELL ASIA PTE, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CAVIUM INTERNATIONAL
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0894—Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms

Definitions

  • the present invention relates generally to mitigating data bus noise. More particularly, the present invention relates to preventing data bus noise associated with simultaneous switching output.
  • SSO Simultaneous switching output
  • the invention features an apparatus comprising: a transmit circuit to transmit data, the transmit circuit comprising a transmit input circuit to input the data, and an address for the data, to the transmit circuit, an encoder to encode the data according to the address for the data, comprising an encode select circuit to select one of a plurality of keys based on the address for the data, and an encoding circuit to encode the data using the key selected by the encode select circuit, and a transmit output circuit to output the encoded data.
  • the apparatus further comprises: a receive circuit to receive the encoded data, the receive circuit comprising a receive input circuit to input the encoded data, and an address for the encoded data, to the receive circuit, a decoder to decode the encoded data according to the address for the encoded data, comprising a decode select circuit to select a second one of the plurality of keys based on the address for the encoded data, and a decoding circuit to decode the encoded data using the key selected by the decode select circuit, and a receive output circuit to output the data.
  • the encoding circuit comprises a plurality of exclusive-or (XOR) gates each comprising a first input to input a respective bit of the data, a second input to input a respective bit of the key selected by the encode select circuit, and an output to output a respective bit of the encoded data.
  • the decoding circuit comprises a plurality of exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the key selected by the decode select circuit, and an output to output a respective bit of the data.
  • the apparatus further comprises: a memory; wherein the encoder further comprises a random number generator to generate random numbers; wherein the encode select circuit selects the one of the plurality of keys according to one of the random numbers; and wherein the memory stores an association between the address for the data and the one of the random numbers.
  • the decode select circuit retrieves, from the memory, a second association between an address for the encoded data and a second one of the random numbers based on the address for the encoded data; and wherein the decode select circuit selects the second one of the plurality of keys according to the second one of the random numbers.
  • the apparatus further comprises: a memory; wherein the address for the data, and the address for the encoded data, comprise at least one of the group consisting of an address in the memory, and a buffer number in the memory.
  • An integrated circuit comprises the apparatus.
  • the invention features a method comprising: inputting data and an address for the data; encoding the data according to the address for the data, comprising selecting one of a plurality of keys based on the address for the data, and encoding the data using the key selected based on the address for the data; and outputting the encoded data.
  • the method further comprises: inputting the encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data, comprising selecting one of the plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data; and outputting the data.
  • Encoding the data using the key selected based on the address for the data comprises generating a bitwise exclusive-or (XOR) of the data and the key selected based on the address for the data.
  • Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
  • the invention features an apparatus comprising: a receive circuit to receive encoded data, the receive circuit comprising a receive input circuit to input the encoded data, and an address for the encoded data, to the receive circuit, a decoder to decode the encoded data according to the address for the encoded data, comprising a decode select circuit to select one of the plurality of keys based on the address for the encoded data, and a decoding circuit to decode the encoded data using the key selected by the decode select circuit, and a receive output circuit to output the data.
  • the decoding circuit comprises a plurality of exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the key selected by the decode select circuit; and an output to output a respective bit of the data.
  • the apparatus further comprises: a memory; wherein the address of the encoded data comprises at least one of the group consisting of an address in the memory, and a buffer number in the memory.
  • An integrated circuit comprising the apparatus.
  • the invention features a method comprising: inputting encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data; and outputting the data.
  • Decoding comprises selecting one of a plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data.
  • Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
  • the invention features an apparatus comprising: transmit means for transmitting data, the transmit means comprising transmit input means for inputting the data, and an address for the data, to the transmit means, encode means for encoding the data according to the address for the data, comprising encode select means for selecting one of a plurality of keys based on the address for the data, and encoding, means for encoding the data using the key selected by the encode means, and transmit output means for outputting the encoded data.
  • the apparatus further comprises: receive means for receiving the encoded data, the receive means comprising receive input means for inputting the encoded data, and an address for the encoded data, to the receive means, decode means for decoding the encoded data according to the address for the encoded data, comprising decode select means for selecting a second one of the plurality of keys based on the address for the encoded data, and decoding means for decoding the encoded data using the key selected by the decode select means, and receive output means for outputting the data.
  • the apparatus further comprises: memory means for storing the encoded data; wherein the encode means further comprises random number means for generating random numbers; wherein the encode select means selects the one of the plurality of keys according to one of the random numbers; and wherein the memory means stores an association between the address for the data and the one of the random numbers.
  • the decode select means retrieves, from the memory means, a second association between an address for the encoded data and a second one of the random numbers based on the address for the encoded data; and wherein the decode select means selects the second one of the plurality of keys according to the second one of the random numbers.
  • the apparatus further comprises: memory means for storing the encoded data; wherein the address for the data, and the address for the encoded data, comprise at least one of the group consisting of an address in the memory means, and a buffer number in the memory means.
  • An integrated circuit comprising the apparatus.
  • the invention features a computer program comprising: inputting data and an address for the data; encoding the data according to the address for the data, comprising selecting one of a plurality of keys based on the address for the data, and encoding the data using the key selected based on the address for the data; and outputting the encoded data.
  • the computer program further comprises: inputting the encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data, comprising selecting one of the plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data; and outputting the data.
  • Encoding the data using the key selected based on the address for the data comprises generating a bitwise exclusive-or (XOR) of the data and the key selected based on the address for the data.
  • Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
  • the invention features an apparatus comprising: receive means for receiving encoded data, the receive means comprising receive input means for inputting the encoded data, and an address for the encoded data, to the receive means, decode means for decoding the encoded data according to the address for the encoded data, comprising decode select means for selecting one of the plurality of keys based on the address for the encoded data, and decoding means for decoding the encoded data using the key selected by the decode select means, and receive output means for outputting the data.
  • the apparatus further comprises: memory means for storing the encoded data; wherein the address of the encoded data comprises at least one of the group consisting of an address in the memory means, and a buffer number in the memory means.
  • An integrated circuit comprising the apparatus.
  • the invention features a computer program comprising: inputting encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data; and outputting the data.
  • Decoding comprises selecting one of a plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data.
  • Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
  • FIG. 1 shows a memory system comprising a memory in communication with a memory controller over a memory bus according to a preferred embodiment of the present invention.
  • FIG. 2 shows a write process for the memory system of FIG. 1 according to a preferred embodiment of the present invention.
  • FIG. 3 shows a read process for the memory system of FIG. 1 according to a preferred embodiment of the present invention.
  • FIG. 4 shows a data transmission system comprising a transmit circuit in communication with a receive circuit over a data bus according to a preferred embodiment of the present invention.
  • FIG. 5 shows a transmit process for the data transmission system of FIG. 4 according to a preferred embodiment of the present invention.
  • FIG. 6 shows a receive process for the data transmission system of FIG. 4 according to a preferred embodiment of the present invention.
  • Embodiments of the present invention encode the data to be placed on a data bus in a random fashion so that any simultaneous switching output (SSO) conditions that occur in the data do not occur on the data bus.
  • the encoding is based on an address for the data.
  • the address is hashed to identify a key that is used to encode the data, for example using a bitwise exclusive-or (XOR).
  • the bus is a memory bus, and the address is a memory address for the data, such as all or part of a memory address or buffer number.
  • FIG. 1 shows a memory system 100 comprising a memory 102 in communication with a memory controller 104 over a memory bus 106 according to a preferred embodiment of the present invention.
  • Memory 102 can be any sort of memory or storage device.
  • Memory controller 104 comprises a write circuit 108 and a read circuit 110 , and can be fabricated as one or more integrated circuits.
  • Write circuit 108 comprises an input circuit 112 , an output circuit 114 , and an encoder 116 .
  • Encoder 116 comprises an encoding circuit 118 , a select circuit 120 , and a key circuit 122 , which can be implemented as a memory.
  • Read circuit 110 comprises an input circuit 124 , an output circuit 126 , and a decoder 128 .
  • Decoder 128 comprises a decoding circuit 130 , a select circuit 132 , and a key circuit 134 , which can be implemented as a memory.
  • FIG. 2 shows a write process 200 for memory system 100 of FIG. 1 according to a preferred embodiment of the present invention.
  • Input circuit 112 of write circuit 108 receives data and an address for the data (step 202 ).
  • the address for the data can include an address in memory 102 to which the data is to be written, a buffer number in memory 102 to which the data is to be written, and the like.
  • Select circuit 120 of encoder 116 receives the address for the data, and selects one of a group of keys stored in key circuit 122 based on all or part of the address (step 204 ). Preferably select circuit 120 hashes all or part of the address to obtain an index to a table containing the keys. Key circuit 122 provides the selected key to encoding circuit 118 .
  • Encoding circuit 118 also receives the data, and encodes the data using the key provided by key circuit 122 (step 206 ).
  • the data is N bits in width
  • each of the keys is N bits in width
  • encoding circuit 118 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the encoded data. That is, encoding circuit 118 encodes the data by generating a bitwise XOR of the data and the selected key.
  • XOR exclusive-or
  • Output circuit 114 of write circuit 108 outputs the encoded data to memory bus 106 (step 208 ).
  • Memory 102 stores the encoded data according to the address (step 210 ).
  • FIG. 3 shows a read process 300 for memory system 100 of FIG. 1 according to a preferred embodiment of the present invention.
  • Input circuit 124 of read circuit 110 receives encoded data from memory bus 106 , and an address for the data (step 302 ).
  • the address for the data can include an address in memory 102 from which the data is read, a buffer number in memory 102 from which the data is read, and the like.
  • Select circuit 132 of decoder 128 receives the address for the data, and selects one of a group of keys stored in key circuit 134 based on all or part of the address (step 304 ).
  • select circuit 132 hashes all or part of the address to obtain an index to a table containing the keys.
  • Key circuit 134 provides the selected key to decoding circuit 130 .
  • select circuits 120 and 132 perform the same selection algorithm, and key circuits 122 and 134 contain the same keys.
  • a single select circuit and/or key circuit can be shared by write circuit 108 and read circuit 110 .
  • Decoding circuit 130 also receives the encoded data, and decodes the encoded data using the key provided by key circuit 134 (step 306 ).
  • the encoded data is N bits in width
  • each of the keys is N bits in width
  • decoding circuit 130 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the data. That is, decoding circuit 130 decodes the encoded data by generating a bitwise XOR of the encoded data and the selected key.
  • XOR exclusive-or
  • Some embodiments select the keys according to random numbers that are associated with the addresses. These embodiments further reduce the likelihood of a SSO condition on the bus. And because the random numbers are stored and used only within memory controller 104 , no additional burden to memory bus 106 is incurred.
  • these embodiments comprise an optional random number generator 136 and an optional internal memory 138 .
  • Random number generator 138 generates a random number for data to be encoded.
  • Select circuit 120 selects the one of the keys according to the random numbers, and stores an association between the address and the random number or key.
  • select circuit 132 uses the address of the encoded data to retrieve the association between the address and the associated random number or key. If the retrieved association is between the address and a key, decoding circuit 130 decodes the encoded data using the key. If the retrieved association is between the address and a random number, decoding circuit 130 selects on of the keys using the random number, and decodes the encoded data using the selected key.
  • FIG. 4 shows a data transmission system 400 comprising a transmit circuit 408 in communication with a receive circuit 410 over a data bus 406 according to a preferred embodiment of the present invention.
  • Transmit circuit 408 and receive circuit 410 can be fabricated as one or more integrated circuits.
  • Transmit circuit 408 comprises an input circuit 412 , an output circuit 414 , and an encoder 416 .
  • Encoder 416 comprises an encoding circuit 418 , a select circuit 420 , and a key circuit 422 , which can be implemented as a memory.
  • Receive circuit 410 comprises an input circuit 424 , an output circuit 426 , and a decoder 428 .
  • Decoder 428 comprises a decoding circuit 430 , a select circuit 432 , and a key circuit 434 , which can be implemented as a memory.
  • FIG. 5 shows a transmit process 500 for data transmission system 400 of FIG. 4 according to a preferred embodiment of the present invention.
  • Input circuit 412 of transmit circuit 408 receives data and an address for the data (step 502 ).
  • the address for the data is not encoded, and can include a destination address to which the data is to be transmitted, a source address from which the data was sent, and the like.
  • Select circuit 420 of encoder 416 receives the address for the data, and selects one of a group of keys stored in key circuit 422 based on all or part of the address (step 504 ). Preferably select circuit 420 hashes all or part of the address to obtain an index to a table containing the keys. Key circuit 422 provides the selected key to encoding circuit 418 .
  • Encoding circuit 418 also receives the data, and encodes the data using the key provided by key circuit 422 (step 506 ).
  • the data is N bits in width
  • each of the keys is N bits in width
  • encoding circuit 418 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the encoded data. That is, encoding circuit 418 encodes the data by generating a bitwise XOR of the data and the selected key.
  • XOR exclusive-or
  • FIG. 6 shows a receive process 600 for data transmission system 400 of FIG. 4 according to a preferred embodiment of the present invention.
  • Input circuit 424 of receive circuit 410 receives encoded data from data bus 406 , and an address for the data (step 602 ).
  • the address for the data can include a destination address to which the data is to be transmitted, a source address from which the data was sent, and the like.
  • Select circuit 432 of decoder 428 receives the address for the data, and selects one of a group of keys stored in key circuit 434 based on all or part of the address (step 604 ).
  • select circuit 432 hashes all or part of the address to obtain an index to a table containing the keys.
  • Key circuit 434 provides the selected key to decoding circuit 430 .
  • select circuits 420 and 432 perform the same selection algorithm, and key circuits 422 and 434 contain the same keys.
  • a single select circuit and/or key circuit can be shared by transmit circuit 408 and receive circuit 410 .
  • Decoding circuit 430 also receives the encoded data, and decodes the encoded data using the key provided by key circuit 434 (step 606 ).
  • the encoded data is N bits in width
  • each of the keys is N bits in width
  • decoding circuit 430 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the data. That is, decoding circuit 430 decodes the encoded data by generating a bitwise XOR of the encoded data and the selected key.
  • XOR exclusive-or
  • the invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them.
  • Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output.
  • the invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor, coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device.
  • Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language.
  • Suitable processors include, by way of example, both general and special purpose microprocessors.
  • a processor will receive instructions and data from a read-only memory and/or a random access memory.
  • a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks.
  • Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits).
  • semiconductor memory devices such as EPROM, EEPROM, and flash memory devices
  • magnetic disks such as internal hard disks and removable disks
  • magneto-optical disks magneto-optical disks
  • CD-ROM disks CD-ROM disks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)

Abstract

An apparatus having a corresponding method comprises a transmit circuit to transmit data, the transmit circuit comprising a transmit input circuit to input the data, and an address for the data, to the transmit circuit, an encoder to encode the data according to the address for the data, comprising an encode select circuit to select one of a plurality of keys based on the address for the data, and an encoding circuit to encode the data using the key selected by the encode select circuit, and a transmit output circuit to output the encoded data.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application is a divisional application of U.S. application Ser. No. 13/558,734, filed on Jul. 26, 2012. U.S. application Ser. No. 13/558,734 is a reissue application of U.S. Pat. No. 7,764,792, which issued on Jul. 27, 2010. U.S. Pat. No. 7,764,792 was filed as U.S. application Ser. No. 11/034,664 on Jan. 13, 2005. The complete disclosures of the above applications are incorporated herein by reference. Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 7,764,792. The reissue applications are the present application and Ser. No. 13/558,734, both of which are reissues of U.S. Pat. No. 7,764,792.
BACKGROUND
The present invention relates generally to mitigating data bus noise. More particularly, the present invention relates to preventing data bus noise associated with simultaneous switching output.
Simultaneous switching output (SSO) describes the circumstance where many or all of the data bits on a data bus transition simultaneously. While SSO is rare in actual operation, it occurs more often in data bus testing situations. SSO causes large power swings that produce significant data bus noise that can affect data bus performance.
SUMMARY
In general, in one aspect, the invention features an apparatus comprising: a transmit circuit to transmit data, the transmit circuit comprising a transmit input circuit to input the data, and an address for the data, to the transmit circuit, an encoder to encode the data according to the address for the data, comprising an encode select circuit to select one of a plurality of keys based on the address for the data, and an encoding circuit to encode the data using the key selected by the encode select circuit, and a transmit output circuit to output the encoded data.
Particular implementations can include one or more of the following features. The apparatus further comprises: a receive circuit to receive the encoded data, the receive circuit comprising a receive input circuit to input the encoded data, and an address for the encoded data, to the receive circuit, a decoder to decode the encoded data according to the address for the encoded data, comprising a decode select circuit to select a second one of the plurality of keys based on the address for the encoded data, and a decoding circuit to decode the encoded data using the key selected by the decode select circuit, and a receive output circuit to output the data. The encoding circuit comprises a plurality of exclusive-or (XOR) gates each comprising a first input to input a respective bit of the data, a second input to input a respective bit of the key selected by the encode select circuit, and an output to output a respective bit of the encoded data. The decoding circuit comprises a plurality of exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the key selected by the decode select circuit, and an output to output a respective bit of the data. The apparatus further comprises: a memory; wherein the encoder further comprises a random number generator to generate random numbers; wherein the encode select circuit selects the one of the plurality of keys according to one of the random numbers; and wherein the memory stores an association between the address for the data and the one of the random numbers. The decode select circuit retrieves, from the memory, a second association between an address for the encoded data and a second one of the random numbers based on the address for the encoded data; and wherein the decode select circuit selects the second one of the plurality of keys according to the second one of the random numbers. The apparatus further comprises: a memory; wherein the address for the data, and the address for the encoded data, comprise at least one of the group consisting of an address in the memory, and a buffer number in the memory. An integrated circuit comprises the apparatus.
In general, in one aspect, the invention features a method comprising: inputting data and an address for the data; encoding the data according to the address for the data, comprising selecting one of a plurality of keys based on the address for the data, and encoding the data using the key selected based on the address for the data; and outputting the encoded data.
Particular implementations can include one or more of the following features. The method further comprises: inputting the encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data, comprising selecting one of the plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data; and outputting the data. Encoding the data using the key selected based on the address for the data comprises generating a bitwise exclusive-or (XOR) of the data and the key selected based on the address for the data. Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
In general, in one aspect, the invention features an apparatus comprising: a receive circuit to receive encoded data, the receive circuit comprising a receive input circuit to input the encoded data, and an address for the encoded data, to the receive circuit, a decoder to decode the encoded data according to the address for the encoded data, comprising a decode select circuit to select one of the plurality of keys based on the address for the encoded data, and a decoding circuit to decode the encoded data using the key selected by the decode select circuit, and a receive output circuit to output the data.
Particular implementations can include one or more of the following features. The decoding circuit comprises a plurality of exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the key selected by the decode select circuit; and an output to output a respective bit of the data. The apparatus further comprises: a memory; wherein the address of the encoded data comprises at least one of the group consisting of an address in the memory, and a buffer number in the memory. An integrated circuit comprising the apparatus.
In general, in one aspect, the invention features a method comprising: inputting encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data; and outputting the data.
Particular implementations can include one or more of the following features. Decoding comprises selecting one of a plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data. Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
In general, in one aspect, the invention features an apparatus comprising: transmit means for transmitting data, the transmit means comprising transmit input means for inputting the data, and an address for the data, to the transmit means, encode means for encoding the data according to the address for the data, comprising encode select means for selecting one of a plurality of keys based on the address for the data, and encoding, means for encoding the data using the key selected by the encode means, and transmit output means for outputting the encoded data.
Particular implementations can include one or more of the following features. The apparatus further comprises: receive means for receiving the encoded data, the receive means comprising receive input means for inputting the encoded data, and an address for the encoded data, to the receive means, decode means for decoding the encoded data according to the address for the encoded data, comprising decode select means for selecting a second one of the plurality of keys based on the address for the encoded data, and decoding means for decoding the encoded data using the key selected by the decode select means, and receive output means for outputting the data.
Particular implementations can include one or more of the following features. The apparatus further comprises: memory means for storing the encoded data; wherein the encode means further comprises random number means for generating random numbers; wherein the encode select means selects the one of the plurality of keys according to one of the random numbers; and wherein the memory means stores an association between the address for the data and the one of the random numbers. The decode select means retrieves, from the memory means, a second association between an address for the encoded data and a second one of the random numbers based on the address for the encoded data; and wherein the decode select means selects the second one of the plurality of keys according to the second one of the random numbers. The apparatus further comprises: memory means for storing the encoded data; wherein the address for the data, and the address for the encoded data, comprise at least one of the group consisting of an address in the memory means, and a buffer number in the memory means. An integrated circuit comprising the apparatus.
In general, in one aspect, the invention features a computer program comprising: inputting data and an address for the data; encoding the data according to the address for the data, comprising selecting one of a plurality of keys based on the address for the data, and encoding the data using the key selected based on the address for the data; and outputting the encoded data.
Particular implementations can include one or more of the following features. The computer program further comprises: inputting the encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data, comprising selecting one of the plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data; and outputting the data. Encoding the data using the key selected based on the address for the data comprises generating a bitwise exclusive-or (XOR) of the data and the key selected based on the address for the data. Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
In general, in one aspect, the invention features an apparatus comprising: receive means for receiving encoded data, the receive means comprising receive input means for inputting the encoded data, and an address for the encoded data, to the receive means, decode means for decoding the encoded data according to the address for the encoded data, comprising decode select means for selecting one of the plurality of keys based on the address for the encoded data, and decoding means for decoding the encoded data using the key selected by the decode select means, and receive output means for outputting the data.
Particular implementations can include one or more of the following features. The apparatus further comprises: memory means for storing the encoded data; wherein the address of the encoded data comprises at least one of the group consisting of an address in the memory means, and a buffer number in the memory means. An integrated circuit comprising the apparatus.
In general, in one aspect, the invention features a computer program comprising: inputting encoded data, and an address for the encoded data; decoding the encoded data according to the address for the encoded data; and outputting the data.
Particular implementations can include one or more of the following features. Decoding comprises selecting one of a plurality of keys based on the address for the encoded data, and decoding the encoded data using the key selected based on the address for the encoded data. Decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.
DESCRIPTION OF DRAWINGS
FIG. 1 shows a memory system comprising a memory in communication with a memory controller over a memory bus according to a preferred embodiment of the present invention.
FIG. 2 shows a write process for the memory system of FIG. 1 according to a preferred embodiment of the present invention.
FIG. 3 shows a read process for the memory system of FIG. 1 according to a preferred embodiment of the present invention.
FIG. 4 shows a data transmission system comprising a transmit circuit in communication with a receive circuit over a data bus according to a preferred embodiment of the present invention.
FIG. 5 shows a transmit process for the data transmission system of FIG. 4 according to a preferred embodiment of the present invention.
FIG. 6 shows a receive process for the data transmission system of FIG. 4 according to a preferred embodiment of the present invention.
The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears.
DETAILED DESCRIPTION
Embodiments of the present invention encode the data to be placed on a data bus in a random fashion so that any simultaneous switching output (SSO) conditions that occur in the data do not occur on the data bus. The encoding is based on an address for the data. In some embodiments the address is hashed to identify a key that is used to encode the data, for example using a bitwise exclusive-or (XOR). In some embodiments the bus is a memory bus, and the address is a memory address for the data, such as all or part of a memory address or buffer number.
FIG. 1 shows a memory system 100 comprising a memory 102 in communication with a memory controller 104 over a memory bus 106 according to a preferred embodiment of the present invention. Memory 102 can be any sort of memory or storage device. Memory controller 104 comprises a write circuit 108 and a read circuit 110, and can be fabricated as one or more integrated circuits.
Write circuit 108 comprises an input circuit 112, an output circuit 114, and an encoder 116. Encoder 116 comprises an encoding circuit 118, a select circuit 120, and a key circuit 122, which can be implemented as a memory.
Read circuit 110 comprises an input circuit 124, an output circuit 126, and a decoder 128. Decoder 128 comprises a decoding circuit 130, a select circuit 132, and a key circuit 134, which can be implemented as a memory.
FIG. 2 shows a write process 200 for memory system 100 of FIG. 1 according to a preferred embodiment of the present invention. Input circuit 112 of write circuit 108 receives data and an address for the data (step 202). The address for the data can include an address in memory 102 to which the data is to be written, a buffer number in memory 102 to which the data is to be written, and the like.
Select circuit 120 of encoder 116 receives the address for the data, and selects one of a group of keys stored in key circuit 122 based on all or part of the address (step 204). Preferably select circuit 120 hashes all or part of the address to obtain an index to a table containing the keys. Key circuit 122 provides the selected key to encoding circuit 118.
Encoding circuit 118 also receives the data, and encodes the data using the key provided by key circuit 122 (step 206). Preferably the data is N bits in width, each of the keys is N bits in width, and encoding circuit 118 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the encoded data. That is, encoding circuit 118 encodes the data by generating a bitwise XOR of the data and the selected key. Of course, other encoding methods can be used.
Output circuit 114 of write circuit 108 outputs the encoded data to memory bus 106 (step 208). Memory 102 stores the encoded data according to the address (step 210).
Because the data is encoded in a random fashion before it is written to memory bus 106, the likelihood that an SSO condition will appear on memory bus 106 is exceedingly small. Any detrimental SSO effects on memory bus 106 and memory 102 are thereby avoided.
FIG. 3 shows a read process 300 for memory system 100 of FIG. 1 according to a preferred embodiment of the present invention. Input circuit 124 of read circuit 110 receives encoded data from memory bus 106, and an address for the data (step 302). The address for the data can include an address in memory 102 from which the data is read, a buffer number in memory 102 from which the data is read, and the like.
Select circuit 132 of decoder 128 receives the address for the data, and selects one of a group of keys stored in key circuit 134 based on all or part of the address (step 304). Preferably select circuit 132 hashes all or part of the address to obtain an index to a table containing the keys. Key circuit 134 provides the selected key to decoding circuit 130. Preferably select circuits 120 and 132 perform the same selection algorithm, and key circuits 122 and 134 contain the same keys. In some embodiments, a single select circuit and/or key circuit can be shared by write circuit 108 and read circuit 110.
Decoding circuit 130 also receives the encoded data, and decodes the encoded data using the key provided by key circuit 134 (step 306). Preferably the encoded data is N bits in width, each of the keys is N bits in width, and decoding circuit 130 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the data. That is, decoding circuit 130 decodes the encoded data by generating a bitwise XOR of the encoded data and the selected key. Of course, other decoding methods can be used. Output circuit 126 of read circuit 110 outputs the data (step 308).
Some embodiments select the keys according to random numbers that are associated with the addresses. These embodiments further reduce the likelihood of a SSO condition on the bus. And because the random numbers are stored and used only within memory controller 104, no additional burden to memory bus 106 is incurred.
Referring again to FIG. 1, these embodiments comprise an optional random number generator 136 and an optional internal memory 138. Random number generator 138 generates a random number for data to be encoded. Select circuit 120 selects the one of the keys according to the random numbers, and stores an association between the address and the random number or key.
To decode data according to these embodiments, select circuit 132 uses the address of the encoded data to retrieve the association between the address and the associated random number or key. If the retrieved association is between the address and a key, decoding circuit 130 decodes the encoded data using the key. If the retrieved association is between the address and a random number, decoding circuit 130 selects on of the keys using the random number, and decodes the encoded data using the selected key.
FIG. 4 shows a data transmission system 400 comprising a transmit circuit 408 in communication with a receive circuit 410 over a data bus 406 according to a preferred embodiment of the present invention. Transmit circuit 408 and receive circuit 410 can be fabricated as one or more integrated circuits.
Transmit circuit 408 comprises an input circuit 412, an output circuit 414, and an encoder 416. Encoder 416 comprises an encoding circuit 418, a select circuit 420, and a key circuit 422, which can be implemented as a memory.
Receive circuit 410 comprises an input circuit 424, an output circuit 426, and a decoder 428. Decoder 428 comprises a decoding circuit 430, a select circuit 432, and a key circuit 434, which can be implemented as a memory.
FIG. 5 shows a transmit process 500 for data transmission system 400 of FIG. 4 according to a preferred embodiment of the present invention. Input circuit 412 of transmit circuit 408 receives data and an address for the data (step 502). The address for the data is not encoded, and can include a destination address to which the data is to be transmitted, a source address from which the data was sent, and the like.
Select circuit 420 of encoder 416 receives the address for the data, and selects one of a group of keys stored in key circuit 422 based on all or part of the address (step 504). Preferably select circuit 420 hashes all or part of the address to obtain an index to a table containing the keys. Key circuit 422 provides the selected key to encoding circuit 418.
Encoding circuit 418 also receives the data, and encodes the data using the key provided by key circuit 422 (step 506). Preferably the data is N bits in width, each of the keys is N bits in width, and encoding circuit 418 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the encoded data. That is, encoding circuit 418 encodes the data by generating a bitwise XOR of the data and the selected key. Of course, other encoding methods can be used. Output circuit 414 of transmit circuit 408 outputs the encoded data to data bus 406 (step 508).
Because the data is encoded in a random fashion before it is written to data bus 406, the likelihood that an SSO condition will appear on data bus 406 is exceedingly small. Any detrimental SSO effects on data bus 406 are thereby avoided.
FIG. 6 shows a receive process 600 for data transmission system 400 of FIG. 4 according to a preferred embodiment of the present invention. Input circuit 424 of receive circuit 410 receives encoded data from data bus 406, and an address for the data (step 602). The address for the data can include a destination address to which the data is to be transmitted, a source address from which the data was sent, and the like.
Select circuit 432 of decoder 428 receives the address for the data, and selects one of a group of keys stored in key circuit 434 based on all or part of the address (step 604). Preferably select circuit 432 hashes all or part of the address to obtain an index to a table containing the keys. Key circuit 434 provides the selected key to decoding circuit 430. Preferably select circuits 420 and 432 perform the same selection algorithm, and key circuits 422 and 434 contain the same keys. In some embodiments, a single select circuit and/or key circuit can be shared by transmit circuit 408 and receive circuit 410.
Decoding circuit 430 also receives the encoded data, and decodes the encoded data using the key provided by key circuit 434 (step 606). Preferably the encoded data is N bits in width, each of the keys is N bits in width, and decoding circuit 430 comprises N exclusive-or (XOR) gates each comprising a first input to input a respective bit of the encoded data, a second input to input a respective bit of the selected key, and an output to output a respective bit of the data. That is, decoding circuit 430 decodes the encoded data by generating a bitwise XOR of the encoded data and the selected key. Of course, other decoding methods can be used. Output circuit 426 of receive circuit 410 outputs the data (step 608).
The invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor, coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits).
A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims.

Claims (25)

What is claimed is:
1. An apparatus comprising:
a transmit circuit to transmit data from a first device to a second device on a bus, the bus connecting the first device and the second device, the transmit circuit comprising:
a transmit input circuit to input the data and an address for the data to the transmit circuit,
an encoder to encode the data according to the address for the data, the encoder comprising:
an encode select circuit to (i) select one of a plurality of keys based on the address for the data and (ii) hash at least a portion of the address to obtain an index to a table containing the plurality of keys, wherein different keys are selected for different addresses when transmitting data from the first device to the second device, and
an encoding circuit to encode the data using the key selected by the encode select circuit, and
a transmit output circuit to output the encoded data on the bus.
2. The apparatus of claim 1, further comprising:
a receive circuit to receive the encoded data from the bus, the receive circuit comprising:
a receive input circuit to input the encoded data and an address for the encoded data to the receive circuit,
a decoder to decode the encoded data according to the address for the encoded data, the decoder comprising:
a decode select circuit to select a second one of the plurality of keys based on the address for the encoded data, and
a decoding circuit to decode the encoded data using the second one of the plurality of keys selected by the decode select circuit, and
a receive output circuit to output the decoded data.
3. The apparatus of claim 1:
wherein the encoding circuit comprises
a plurality of exclusive-or (XOR) gates each comprising
a first input to input a respective bit of the data,
a second input to input a respective bit of the key selected by the encode select circuit, and
an output to output a respective bit of the encoded data.
4. The apparatus of claim 2:
wherein the decoding circuit comprises
a plurality of exclusive-or (XOR) gates each comprising
a first input to input a respective bit of the encoded data,
a second input to input a respective bit of the second one of the plurality of keys selected by the decode select circuit, and
an output to output a respective bit of the data.
5. The apparatus of claim 2, further comprising:
a memory;
wherein the encoder further comprises a random number generator to generate random numbers;
wherein the encode select circuit selects the one of the plurality of keys according to one of the random numbers; and
wherein the memory stores an association between the address for the data and the one of the random numbers.
6. The apparatus of claim 5:
wherein the decode select circuit retrieves from the memory a second association between the address for the encoded data and a second one of the random numbers based on the address for the encoded data; and
wherein the decode select circuit selects the second one of the plurality of keys according to the second one of the random numbers.
7. The apparatus of claim 2, further comprising:
a memory;
wherein the address for the data, and the address for the encoded data, comprise at least one of the group consisting of
an address in the memory, and
a buffer number in the memory.
8. An integrated circuit comprising the apparatus of claim 1.
9. A method comprising:
transmitting (i) data and (ii) an address for the data from a first device to a second device on a bus, the bus connecting the first device and the second device;
encoding the data according to the address for the data by:
selecting one of a plurality of keys based on the address for the data;
hashing at least a portion of the address to obtain an index to a table containing the plurality of keys, wherein different keys are selected for different addresses when transmitting data from the first device to the second device; and
encoding the data using the key selected based on the address for the data; and
outputting the encoded data on the bus.
10. The method of claim 9, further comprising:
decoding the encoded data according to the address for the encoded data by:
selecting a second one of the plurality of keys based on the address for the encoded data; and
decoding the encoded data using the second one of the plurality of keys selected based on the address for the encoded data.
11. The method of claim 9:
wherein encoding the data using the key selected based on the address for the data comprises generating a bitwise exclusive-or (XOR) of the data and the key selected based on the address for the data.
12. The method of claim 10:
wherein decoding the encoded data using the second one of the plurality of keys selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the second one of the plurality of keys selected based on the address for the encoded data.
13. An apparatus comprising:
a receive circuit to receive data that is encoded from a bus, the receive circuit comprising:
a receive input circuit to input the encoded data and an address for the encoded data received from the bus to the receive circuit,
a decoder to decode the encoded data according to the address for the encoded data, the decoder comprising:
a decode select circuit to select one of the plurality of keys based on the address for the encoded data, and
a decoding circuit to decode the encoded data using the key selected by the decode select circuit, and
a receive output circuit to output the decoded data.
14. The apparatus of claim 13:
wherein the decoding circuit comprises
a plurality of exclusive-or (XOR) gates each comprising
a first input to input a respective bit of the encoded data,
a second input to input a respective bit of the key selected by the decode select circuit, and
an output to output a respective bit of the data.
15. The apparatus of claim 13, further comprising:
a memory;
wherein the address of the encoded data comprises at least one of the group consisting of
an address in the memory, and
a buffer number in the memory.
16. An integrated circuit comprising the apparatus of claim 13.
17. A method comprising:
inputting encoded data and an address for the encoded data received from a bus;
decoding the encoded data according to the address for the encoded data; and
outputting the decoded data.
18. The method of claim 17:
wherein decoding comprises
selecting one of a plurality of keys based on the address for the encoded data, and
decoding the encoded data using the key selected based on the address for the encoded data.
19. The method of claim 18:
wherein decoding the encoded data using the key selected based on the address for the encoded data comprises generating a bitwise exclusive-or (XOR) of the encoded data and the key selected based on the address for the encoded data.
20. A method of reducing an amount of simultaneously switched outputs of a memory device, comprising:
driving outputs of the memory device to a set of values;
randomly encoding the set of values based on a random number to reduce an amount of simultaneously switched outputs resulting from switching of the set of values to another set of values; and
driving the outputs of the memory device to the randomly encoded set of values.
21. The method according to claim 20, further comprising:
decoding the randomly encoded set of values back to the set of values.
22. An interface of a device that is coupled to a memory, comprising:
an output driving circuit that is coupled to outputs of the device, the output driving circuit being configured to drive the outputs of the device to a set of values;
a random number generator configured to generate a random number; and
an encoder that is coupled to the output driving circuit, the encoder being configured to receive the set of values and to randomly encode the set of values based on the random number to reduce an amount of simultaneously switched outputs resulting from switching of the set of values to another set of values,
wherein the output driving circuit drives the outputs of the device to the randomly encoded set of values.
23. The interface according to claim 22, wherein the memory comprises:
a decoder configured to decode the randomly encoded set of values back to the set of values.
24. A semiconductor device having reduced simultaneously switched outputs, comprising:
an output driving circuit that is coupled to outputs of the semiconductor device, the output driving circuit being configured to drive the outputs to a set of values;
a random number generator configured to generate a random number; and
an encoder that is coupled between the semiconductor device and the output driving circuit, the encoder being configured to receive the set of values from the output driving circuit and to randomly encode the set of values based on the random number to reduce an amount of simultaneously switched outputs resulting from switching of the set of values to another set of values.
25. The semiconductor device according to claim 24, wherein the outputs of the semiconductor device are coupled to a memory to store the set of values, the memory comprises:
a decoder configured to decode the randomly encoded set of values back to the set of values.
US14/031,881 2005-01-13 2013-09-19 System and method for encoding data transmitted on a bus Active 2027-11-19 USRE45334E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/031,881 USRE45334E1 (en) 2005-01-13 2013-09-19 System and method for encoding data transmitted on a bus

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/034,664 US7764792B1 (en) 2005-01-13 2005-01-13 System and method for encoding data transmitted on a bus
US13/558,734 USRE44777E1 (en) 2005-01-13 2012-07-26 System and method for encoding data transmitted on a bus
US14/031,881 USRE45334E1 (en) 2005-01-13 2013-09-19 System and method for encoding data transmitted on a bus

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/034,664 Reissue US7764792B1 (en) 2005-01-13 2005-01-13 System and method for encoding data transmitted on a bus

Publications (1)

Publication Number Publication Date
USRE45334E1 true USRE45334E1 (en) 2015-01-13

Family

ID=42341928

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/034,664 Ceased US7764792B1 (en) 2005-01-13 2005-01-13 System and method for encoding data transmitted on a bus
US13/558,734 Active 2027-11-19 USRE44777E1 (en) 2005-01-13 2012-07-26 System and method for encoding data transmitted on a bus
US14/031,881 Active 2027-11-19 USRE45334E1 (en) 2005-01-13 2013-09-19 System and method for encoding data transmitted on a bus

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US11/034,664 Ceased US7764792B1 (en) 2005-01-13 2005-01-13 System and method for encoding data transmitted on a bus
US13/558,734 Active 2027-11-19 USRE44777E1 (en) 2005-01-13 2012-07-26 System and method for encoding data transmitted on a bus

Country Status (1)

Country Link
US (3) US7764792B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8205047B2 (en) * 2007-03-14 2012-06-19 Marvell Israel (M.I.S.L.) Ltd. Method and apparatus for reducing simultaneous switching outputs
US8000161B2 (en) * 2007-06-28 2011-08-16 University Of Virginia Patent Foundation Method and system for encoding to eliminate parasitics in crossbar array memories
US8549367B1 (en) * 2010-12-29 2013-10-01 Cadence Design Systems, Inc. Method and system for accelerating memory randomization
US9406364B2 (en) 2013-07-15 2016-08-02 Oracle International Corporation Codec to reduce simultaneously switching outputs
US9966970B2 (en) 2015-04-09 2018-05-08 Oracle International Corporation Efficient silent code assignment to a set of logical codes

Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4431865A (en) 1979-10-10 1984-02-14 Telediffusion De France Digital signal enciphering and deciphering apparatus and system
US4791669A (en) * 1985-11-30 1988-12-13 Nec Corporation Encryption/decryption system
US5142167A (en) * 1991-05-01 1992-08-25 International Business Machines Corporation Encoding for simultaneous switching output noise reduction
US5390359A (en) * 1992-03-20 1995-02-14 International Business Machines Corporation Storing and retrieving records in a computer system
US5481555A (en) * 1990-06-29 1996-01-02 Digital Equipment Corporation System and method for error detection and reducing simultaneous switching noise
US5483598A (en) 1993-07-01 1996-01-09 Digital Equipment Corp., Patent Law Group Message encryption using a hash function
US5917364A (en) * 1996-12-25 1999-06-29 Nec Corporation Bi-directional interface circuit of reduced signal alteration
US6035040A (en) * 1997-10-17 2000-03-07 Nortel Networks Corporation System and method for decryption in the symbol domain
US6061453A (en) 1996-03-08 2000-05-09 Societe D'applications Mecaniques Et Electriques De Boulogne Billancourt, Sappel Communication system by radio connection
US6249521B1 (en) 1997-02-14 2001-06-19 Advanced Micro Devices, Inc. Method and apparatus for creating a port vector
US20010005682A1 (en) * 1999-12-27 2001-06-28 Masayuki Terao Communication device, communication device set, authentication method and method of wireless-connecting terminals
US6304482B1 (en) 2000-11-21 2001-10-16 Silicon Integrated Systems Corp. Apparatus of reducing power consumption of single-ended SRAM
WO2002039290A2 (en) * 2000-11-07 2002-05-16 Intel Corporation Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion
US20020073316A1 (en) * 1998-02-03 2002-06-13 Thomas Collins Cryptographic system enabling ownership of a secure process
US20020141578A1 (en) * 2001-03-29 2002-10-03 Ripley Michael S. Method and apparatus for content protection across a source-to-destination interface
US6526145B2 (en) * 1997-01-29 2003-02-25 David M. Marzahn Data encryptor/decryptor using variable in-place I/O
US20030125015A1 (en) 2001-12-27 2003-07-03 Mastsushita Electric Industrial Co., Ltd. Data transfer system
US6721918B2 (en) * 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US6734811B1 (en) * 2003-05-21 2004-05-11 Apple Computer, Inc. Single-ended balance-coded interface with embedded-timing
US6810387B1 (en) 1999-09-14 2004-10-26 Samsung Electronics Co., Ltd. Copy prevention apparatus and method in digital broadcasting receiving system
US20050076194A1 (en) 2000-01-31 2005-04-07 Ruban Kanapathippillai Unified instruction pipeline for power reduction in a digital signal processor integrated circuit
US20050078016A1 (en) 2003-10-14 2005-04-14 Neff Robert M. R. Power consumption stabilization system & method
US20060171233A1 (en) 2005-01-18 2006-08-03 Khaled Fekih-Romdhane Near pad ordering logic
US7120696B1 (en) * 2000-05-19 2006-10-10 Stealthkey, Inc. Cryptographic communications using pseudo-randomly generated cryptography keys
US7139691B1 (en) 2003-10-21 2006-11-21 Xilinx, Inc. Method for calculating weighted average ground bounce noise generated by simultaneous switching outputs in a digital system
US7248696B2 (en) * 2002-09-12 2007-07-24 International Business Machines Corporation Dynamic system bus encryption using improved differential transitional encoding

Patent Citations (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4431865A (en) 1979-10-10 1984-02-14 Telediffusion De France Digital signal enciphering and deciphering apparatus and system
US4791669A (en) * 1985-11-30 1988-12-13 Nec Corporation Encryption/decryption system
US5481555A (en) * 1990-06-29 1996-01-02 Digital Equipment Corporation System and method for error detection and reducing simultaneous switching noise
US5142167A (en) * 1991-05-01 1992-08-25 International Business Machines Corporation Encoding for simultaneous switching output noise reduction
US5390359A (en) * 1992-03-20 1995-02-14 International Business Machines Corporation Storing and retrieving records in a computer system
US5483598A (en) 1993-07-01 1996-01-09 Digital Equipment Corp., Patent Law Group Message encryption using a hash function
US6061453A (en) 1996-03-08 2000-05-09 Societe D'applications Mecaniques Et Electriques De Boulogne Billancourt, Sappel Communication system by radio connection
US5917364A (en) * 1996-12-25 1999-06-29 Nec Corporation Bi-directional interface circuit of reduced signal alteration
US6526145B2 (en) * 1997-01-29 2003-02-25 David M. Marzahn Data encryptor/decryptor using variable in-place I/O
US6249521B1 (en) 1997-02-14 2001-06-19 Advanced Micro Devices, Inc. Method and apparatus for creating a port vector
US6035040A (en) * 1997-10-17 2000-03-07 Nortel Networks Corporation System and method for decryption in the symbol domain
US20020073316A1 (en) * 1998-02-03 2002-06-13 Thomas Collins Cryptographic system enabling ownership of a secure process
US6810387B1 (en) 1999-09-14 2004-10-26 Samsung Electronics Co., Ltd. Copy prevention apparatus and method in digital broadcasting receiving system
US20010005682A1 (en) * 1999-12-27 2001-06-28 Masayuki Terao Communication device, communication device set, authentication method and method of wireless-connecting terminals
US20050076194A1 (en) 2000-01-31 2005-04-07 Ruban Kanapathippillai Unified instruction pipeline for power reduction in a digital signal processor integrated circuit
US7120696B1 (en) * 2000-05-19 2006-10-10 Stealthkey, Inc. Cryptographic communications using pseudo-randomly generated cryptography keys
WO2002039290A2 (en) * 2000-11-07 2002-05-16 Intel Corporation Method and apparatus for reducing simultaneous switching output noise using dynamic bus inversion
US6304482B1 (en) 2000-11-21 2001-10-16 Silicon Integrated Systems Corp. Apparatus of reducing power consumption of single-ended SRAM
US6721918B2 (en) * 2000-12-29 2004-04-13 Intel Corporation Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect
US20020141578A1 (en) * 2001-03-29 2002-10-03 Ripley Michael S. Method and apparatus for content protection across a source-to-destination interface
US20030125015A1 (en) 2001-12-27 2003-07-03 Mastsushita Electric Industrial Co., Ltd. Data transfer system
US7248696B2 (en) * 2002-09-12 2007-07-24 International Business Machines Corporation Dynamic system bus encryption using improved differential transitional encoding
US6734811B1 (en) * 2003-05-21 2004-05-11 Apple Computer, Inc. Single-ended balance-coded interface with embedded-timing
US20050078016A1 (en) 2003-10-14 2005-04-14 Neff Robert M. R. Power consumption stabilization system & method
US7139691B1 (en) 2003-10-21 2006-11-21 Xilinx, Inc. Method for calculating weighted average ground bounce noise generated by simultaneous switching outputs in a digital system
US20060171233A1 (en) 2005-01-18 2006-08-03 Khaled Fekih-Romdhane Near pad ordering logic

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Nakamura et al., "A 50% Noise Reduction Interface Using Low-Weight Coding," IEEE, 1996, pp. 144-145.
Office Action issued Apr. 11, 2011 in Israel Patent Application No. 190185.

Also Published As

Publication number Publication date
US7764792B1 (en) 2010-07-27
USRE44777E1 (en) 2014-02-25

Similar Documents

Publication Publication Date Title
USRE45334E1 (en) System and method for encoding data transmitted on a bus
JP3815562B2 (en) Data processing method, communication system using the same, data transmission device, data reception device, and program
US6411223B1 (en) Generating high weight encoding symbols using a basis
CA2359534A1 (en) Information additive group code generator and decoder for communication systems
JP2012090286A (en) Memory system having encryption/decryption function of in stream data
US20160344428A1 (en) Joint encryption and error correction encoding
CN111310222A (en) File encryption method
US10742400B2 (en) Datastream block encryption
CN1290069C (en) Block encoding/decoding method, circuit, and device
JPH11510036A (en) Decryption of retransmitted data in encrypted communication systems
US10193579B2 (en) Storage control device, storage system, and storage control method
US7003111B2 (en) Method, system, and program, for encoding and decoding input data
US7719442B2 (en) Multi-mode multi-parallelism data exchange method and device thereof
US7181668B2 (en) Method and system of decoding an encoded data block
JP4079965B2 (en) Decryption system
US7085988B1 (en) Hashing system utilizing error correction coding techniques
JP6273226B2 (en) Encryption system, authentication system, encryption device, decryption device, authenticator generation device, verification device, encryption method, authentication method
US7558968B2 (en) Information processing apparatus and method
US20040160983A1 (en) Method and apparatus for transmitting and receiving compressed frame of data over a wireless channel
US20210152326A1 (en) White-box encryption method for prevention of fault injection attack and apparatus therefor
US7256715B1 (en) Data compression using dummy codes
JP2022086403A (en) Memory system and information processing system
JP2003264533A (en) Turbo decoder, turbo encoder, and radio base station including turbo encoder and decoder
JP3256121B2 (en) Data encoding device and data decoding device and method therefor
JP2007510959A (en) Random access memory and method for storing data in encryption device and decryption device

Legal Events

Date Code Title Description
MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8

AS Assignment

Owner name: CAVIUM INTERNATIONAL, CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MARVELL INTERNATIONAL LTD.;REEL/FRAME:052918/0001

Effective date: 20191231

AS Assignment

Owner name: MARVELL ASIA PTE, LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CAVIUM INTERNATIONAL;REEL/FRAME:053475/0001

Effective date: 20191231

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12