JP5668758B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 196
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000000758 substrate Substances 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 238000001312 dry etching Methods 0.000 description 11
- 230000005669 field effect Effects 0.000 description 9
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 9
- 239000003960 organic solvent Substances 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 238000001771 vacuum deposition Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 7
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 6
- 229910052731 fluorine Inorganic materials 0.000 description 6
- 239000011737 fluorine Substances 0.000 description 6
- 238000000927 vapour-phase epitaxy Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
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Description
(半導体装置)
次に、本実施の形態における半導体装置について説明する。図2に示されるように、本実施の形態における半導体装置は、縦型構造の電界効果型トランジスタである。具体的には、n+−SiCまたは、n+−GaN等からなる基板11上に、n−GaN層12、p−GaN層13、n−GaN層14が形成されており、n−GaN層14の表面の一部には、ソース電極21が形成されている。また、n−GaN層14の表面より、p−GaN層13、n−GaN層12の一部をエッチングすることにより開口部が形成されており、n−GaN層14の表面及び開口部の内部表面を覆うようにゲート絶縁膜15が形成されている。開口部には、ゲート絶縁膜15を介しゲート電極22が形成されている。
次に、本実施の形態における半導体装置の製造方法について図3から図5に基づき説明する。
次に、第2の実施の形態における半導体装置の製造方法について、図6から図8に基づき説明する。
次に、第3の実施の形態における半導体装置の製造方法について、図9から図11に基づき説明する。
次に、第4の実施の形態における半導体装置の製造方法について、図12から図14に基づき説明する。
次に、第5の実施の形態における半導体装置の製造方法について、図15から図17に基づき説明する。
12 n−GaN層
13 p−GaN層
14 n−GaN層
15 ゲート絶縁膜
21 ソース電極
22 ゲート電極
23 ドレイン電極
31 第4の電極
32 絶縁膜(裏面絶縁膜)
42 絶縁膜
43 開口部
Claims (10)
- 導電性を有する半導体基板の一方の面上に形成された第1の導電型の第1の半導体層と、
前記第1の半導体層上に形成された第2の導電型の第2の半導体層と、
前記第2の半導体層上に形成された第1の導電型の第3の半導体層と、
前記第3の半導体層、前記第2の半導体層及び前記第1の半導体層の一部を除去することにより形成された開口部と、
前記開口部の内壁を覆うように形成されたゲート絶縁膜と、
前記ゲート絶縁膜を介し前記開口部内に形成されたゲート電極と、
前記第3の半導体層の表面に形成されたソース電極と、
前記半導体基板の他方の面において、前記ゲート電極に対応する部分に形成されたドレイン電極と、
前記半導体基板の他方の面において、前記ソース電極に対応する部分に形成された第4の電極と、
を有することを特徴とする半導体装置。 - 前記第4の電極は、前記半導体基板の他方の面に形成された裏面絶縁膜上に形成されているものであることを特徴とする請求項1に記載の半導体装置。
- 導電性を有する半導体基板の一方の面上に形成された第1の導電型の第1の半導体層と、
前記第1の半導体層上に形成された第2の導電型の第2の半導体層と、
前記第2の半導体層上に形成された第1の導電型の第3の半導体層と、
前記第3の半導体層、前記第2の半導体層及び前記第1の半導体層の一部を除去することにより形成された開口部と、
前記開口部の内壁を覆うように形成されたゲート絶縁膜と、
前記ゲート絶縁膜を介し前記開口部内に形成されたゲート電極と、
前記第3の半導体層の表面に形成されたソース電極と、
前記半導体基板の他方の面より、前記ソース電極に対応する部分の前記半導体基板及び前記第1の半導体層の一部を除去することにより形成された裏面除去領域と、
前記第1の半導体層が露出している前記裏面除去領域に形成された第4の電極と、
前記半導体基板の他方の面において、前記ゲート電極に対応する部分に形成されたドレイン電極と、
を有することを特徴とする半導体装置。 - 前記第4の電極は、前記第1の半導体層が露出している裏面絶縁膜上に形成されているものであることを特徴とする請求項3に記載の半導体装置。
- 前記第4の電極に印加される電位は、前記ドレイン電極に印加される電位から前記ソース電極に印加される電位の間の電位であることを特徴とする請求項1から4のいずれかに記載の半導体装置。
- 前記第4の電極に印加される電位は、前記ソース電極に印加される電位であることを特徴とする請求項1から5のいずれかに記載の半導体装置。
- 前記第1の半導体層、前記第2の半導体層及び前記第3の半導体層は、GaNを含む材料により形成されているものであることを特徴とする請求項1から6のいずれかに記載の半導体装置。
- 導電性を有する半導体基板の一方の面上に、第1の導電型の第1の半導体層、第2の導電型の第2の半導体層、第1の導電型の第3の半導体層を積層形成する工程と、
前記第2の半導体層、前記第3の半導体層及び前記第1の半導体層の一部を除去し開口部を形成する工程と、
前記開口部内にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を介し前記開口部内にゲート電極を形成する工程と、
前記第3の半導体層上にソース電極を形成する工程と、
前記半導体基板の他方の面において、前記ゲート電極に対応する部分にドレイン電極を形成する工程と、
前記半導体基板の他方の面において、前記ソース電極に対応する部分に第4の電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 導電性を有する半導体基板の一方の面上に、第1の導電型の第1の半導体層、第2の導電型の第2の半導体層、第1の導電型の第3の半導体層を積層形成する工程と、
前記第2の半導体層、前記第3の半導体層及び前記第1の半導体層の一部を除去し開口部を形成する工程と、
前記開口部内にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を介し前記開口部内にゲート電極を形成する工程と、
前記第3の半導体層上にソース電極を形成する工程と、
前記半導体基板の他方の面より、前記ソース電極に対応する部分の前記半導体基板及び前記第1の半導体層の一部を除去することにより裏面除去領域を形成する工程と、
前記裏面除去領域に第4の電極を形成する工程と、
前記半導体基板の他方の面において、前記ゲート電極に対応する部分にドレイン電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記第4の電極に印加される電位は、前記ソース電極に印加される電位であることを特徴とする請求項8または9に記載の半導体装置の製造方法。
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US (2) | US9564527B2 (ja) |
JP (1) | JP5668758B2 (ja) |
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JP2012175089A (ja) * | 2011-02-24 | 2012-09-10 | Fujitsu Ltd | 半導体装置及び半導体装置の製造方法 |
JP6054621B2 (ja) * | 2012-03-30 | 2016-12-27 | トランスフォーム・ジャパン株式会社 | 化合物半導体装置及びその製造方法 |
JP2015130374A (ja) * | 2014-01-06 | 2015-07-16 | 日本電信電話株式会社 | 窒化物半導体装置の製造方法 |
US10608102B2 (en) * | 2017-09-29 | 2020-03-31 | Electronics And Telecommunications Research Institute | Semiconductor device having a drain electrode contacting an epi material inside a through-hole and method of manufacturing the same |
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- 2010-11-05 JP JP2012541698A patent/JP5668758B2/ja not_active Expired - Fee Related
- 2010-11-05 CN CN201080069927.0A patent/CN103201841B/zh not_active Expired - Fee Related
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JPH08321611A (ja) * | 1995-05-26 | 1996-12-03 | Matsushita Electric Works Ltd | 半導体装置 |
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Also Published As
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US20130228795A1 (en) | 2013-09-05 |
JPWO2012060014A1 (ja) | 2014-05-12 |
US20170104098A1 (en) | 2017-04-13 |
CN103201841A (zh) | 2013-07-10 |
US9564527B2 (en) | 2017-02-07 |
WO2012060014A1 (ja) | 2012-05-10 |
CN103201841B (zh) | 2016-06-22 |
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