US20170104098A1 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US20170104098A1 US20170104098A1 US15/386,004 US201615386004A US2017104098A1 US 20170104098 A1 US20170104098 A1 US 20170104098A1 US 201615386004 A US201615386004 A US 201615386004A US 2017104098 A1 US2017104098 A1 US 2017104098A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 239000000758 substrate Substances 0.000 claims abstract description 73
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H01L29/0843—Source or drain regions of field-effect devices
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- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Definitions
- Nitride semiconductors such as GaN, AlN, and InN have a wide band gap and good material properties, and may therefore be used for high breakdown voltage electronic devices or short-wavelength light emitting devices.
- FET field effect transistors
- HEMT High Electron Mobility Transistors
- a horizontal structure a structure in which the current flows substantially parallel to the substrate surface
- a long inter-electrode length is to be formed.
- the chip size of the device to be formed is increased, and the number of chips that may be manufactured from one wafer is decreased, which leads to an increase in the manufacturing cost, resulting in high cost.
- a field effect transistor having a vertical structure (a structure in which the current flows substantially perpendicular to the substrate surface) is garnering attention, because the chip size may be decreased with such a structure.
- Patent document 1 Japanese Laid-Open Patent Publication No. 2002-359256
- Patent document 2 Japanese Laid-Open Patent Publication No. 2008-53448
- Non-patent document 1 Applied Physics Express 1 (2008) 011105
- Non-patent document 2 Applied Physics Express 1 (2008) 021104
- a field effect transistor having a vertical structure has a source electrode formed on one side of a substrate and a drain electrode formed on the other side of the substrate.
- a description is given of a field effect transistor having a vertical structure, with reference to FIG. 1 .
- a n-GaN layer 612 On a substrate 611 constituted by n + -SiC or n + -GaN, a n-GaN layer 612 , a p-GaN layer 613 , and a n-GaN layer 614 are formed. On part of the surface of the n-GaN layer 614 , a source electrode 621 is formed. Furthermore, an opening part is formed by etching part of the n-GaN layer 614 , the p-GaN layer 613 , and the GaN layer 612 from the surface of the n-GaN layer 614 .
- An insulating film 615 is formed so as to cover the surface of the n-GaN layer 614 and the surface of the inside of the opening part. Furthermore, in the opening part, a gate electrode 622 is formed via the insulating film 615 . On the back side of the substrate 611 , i.e., on the side opposite to the side on which the semiconductor layer is formed, a drain electrode 623 is formed.
- a leakage current passing the p-GaN layer 613 is generated. That is to say, in an area other than the area that is the current path indicated by a dashed-line arrow A, a leakage current flowing through the p-GaN layer 613 indicated by a dashed-line arrow B is generated. When such a leakage current is generated, properties of the field effect transistor are degraded.
- a semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
- FIG. 1 is a structural diagram of a field effect transistor having a vertical structure
- FIG. 2 is a structural diagram of a semiconductor device according to a first embodiment
- FIGS. 3A through 3C are manufacturing procedure diagrams of a semiconductor device according to a first embodiment (1);
- FIGS. 4A through 4C are manufacturing procedure diagrams of a semiconductor device according to the first embodiment (2);
- FIGS. 5A and 5B are manufacturing procedure diagrams of a semiconductor device according to the first embodiment (3);
- FIGS. 6A through 6C are manufacturing procedure diagrams of a semiconductor device according to a second embodiment (1).
- FIGS. 7A through 7C are manufacturing procedure diagrams of a semiconductor device according to the second embodiment (2).
- FIGS. 8A and 8B are manufacturing procedure diagrams of a semiconductor device according to the second embodiment (3);
- FIGS. 9A through 9C are manufacturing procedure diagrams of a semiconductor device according to a third embodiment (1).
- FIGS. 10A through 10C are manufacturing procedure diagrams of a semiconductor device according to the third embodiment (2).
- FIGS. 11A through 11C are manufacturing procedure diagrams of a semiconductor device according to the third embodiment (3).
- FIGS. 12A through 12C are manufacturing procedure diagrams of a semiconductor device according to a fourth embodiment (1).
- FIGS. 13A through 13C are manufacturing procedure diagrams of a semiconductor device according to the fourth embodiment (2).
- FIG. 14 is a manufacturing procedure diagram of a semiconductor device according to the fourth embodiment (3).
- FIGS. 15A through 15C are manufacturing procedure diagrams of a semiconductor device according to a fifth embodiment (1).
- FIGS. 16A through 16C are manufacturing procedure diagrams of a semiconductor device according to the fifth embodiment (2).
- FIGS. 17A and 17B are manufacturing procedure diagrams of a semiconductor device according to the fifth embodiment (3).
- a semiconductor device is a field effect transistor having a vertical structure. Specifically, on a substrate 11 constituted by n + -SiC or n + -GaN, a n-GaN layer 12 , a p-GaN layer 13 , and a n-GaN layer 14 are formed. On part of the surface of the n-GaN layer 14 , a source electrode 21 is formed. Furthermore, an opening part is formed by etching part of the p-GaN layer 13 and the n-GaN layer 12 from the surface of the n-GaN layer 14 . A gate insulating film 15 is formed so as to cover the surface of the n-GaN layer 14 and the surface of the inside of the opening part. In the opening part, a gate electrode 22 is formed via the gate insulating film 15 .
- a drain electrode 23 is formed in a part corresponding to the area where the gate electrode 22 is formed and an area surrounding the gate electrode 22 . Furthermore, in a part corresponding to an area other than where the drain electrode 23 , and the area where the source electrode 21 is formed and areas surrounding the source electrode 21 , a fourth electrode 31 is formed via an insulating film 32 which acts as a back side insulating film. Between the drain electrode 23 and the fourth electrode 31 , insulation properties are maintained by the insulating film 32 .
- a potential which is substantially the same as the potential applied to the source electrode 21 or the gate electrode 22 , is applied to the fourth electrode 31 . Accordingly, when a potential that causes an on state is applied to the gate electrode 22 , a current flows through the p-GaN layer 13 near the gate electrode 22 via the gate insulating film 15 , as indicated by a dashed-line arrow C. However, a leakage current hardly flows in the p-GaN layer 13 in areas outside the above area.
- the fourth electrode 31 When the same potential as that of the source electrode 21 is applied to the fourth electrode 31 , and a potential that causes an on state is applied to the gate electrode 22 , a current flows from the source electrode 21 to the drain electrode 23 in the p-GaN layer 13 near the gate electrode 22 via the gate insulating film 15 .
- the fourth electrode 31 and the source electrode 21 have the same potential, and the insulating film 32 is formed, and therefore a current does not flow from the source electrode 21 to the fourth electrode 31 .
- a current hardly flows between the source electrode 21 and the drain electrode 23 . That is to say, in the semiconductor device according to the present embodiment, in the on state, as indicated by a dashed-line arrow C, a current flows in an area of the p-GaN layer 13 via the gate insulating film 15 near the gate electrode 22 , but a current does not flow in areas other than this area. Therefore, the leakage current is significantly decreased in the off state, and therefore device properties are improved.
- the potential applied to the fourth electrode 31 is less than or equal to the potential applied to the drain electrode 23 and greater than or equal to the potential applied to the source electrode 21 or the gate electrode 22 , the same effects are achieved.
- a buffer layer (not illustrated) is formed on the substrate 11 made of n + -SiC.
- MOVPE Metal-Organic Vapor Phase Epitaxy
- the n-GaN layer 12 is formed to have a thickness of 1 ⁇ m through 10 ⁇ m, and 1 ⁇ 10 17 cm ⁇ 3 through 1 ⁇ 10 20 cm ⁇ 3 of Si is doped as an impurity element.
- the p-GaN layer 13 is formed to have a thickness of 10 nm through 1 ⁇ m, and approximately 1 ⁇ 10 19 cm ⁇ 3 of Mg is doped as an impurity element.
- the n-GaN layer 14 is formed to have a thickness of 10 nm through 1 ⁇ m, and 1 ⁇ 10 17 cm ⁇ 3 through 1 ⁇ 10 20 cm ⁇ 3 of Si is doped as an impurity element.
- an opening part 41 is formed in an area where the gate electrode 22 is formed as described below.
- photoresist is applied on the n-GaN layer 14 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part 41 is to be formed.
- dry etching such as RIE (Reactive Ion Etching) is performed with the use of gas including chlorine, to remove part of the n-GaN layer 14 , the p-GaN layer 13 , and the n-GaN layer 12 , and form the opening part 41 .
- the gate insulating film 15 is formed inside the opening part 41 and on the surface of the n-GaN layer 14 , and the gate electrode 22 is formed inside the opening part 41 via the gate insulating film 15 .
- the gate insulating film 15 made of SiN is formed to have a thickness of 1 nm through 1 ⁇ m, inside the opening part 41 and on the surface of the n-GaN layer 14 .
- photoresist is applied on the surface of the gate insulating film 15 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the gate electrode 22 is to be formed.
- a metal film made of Ni is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the gate electrode 22 is formed in the opening part 41 via the gate insulating film 15 .
- the source electrode 21 is formed. Specifically, photoresist is applied on the surface of the gate insulating film 15 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the source electrode 21 is to be formed. Subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove the gate insulating film 15 so that the surface of the n-GaN layer 14 is exposed. Furthermore, subsequently, a metal film made of Ti/Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the source electrode 21 is formed on the n-GaN layer 14 , and subsequently, ohmic contact is realized by performing a heat treatment in a nitrogen atmosphere.
- the drain electrode 23 is formed at a part corresponding to the area where the gate electrode 22 is formed. Specifically, photoresist is applied on the back side of the substrate 11 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where the drain electrode 23 is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, on the back side of the substrate 11 , the drain electrode 23 is formed at a part corresponding to the area where the gate electrode 22 is formed. At this time, the drain electrode 23 is not formed at the part corresponding to the area where the source electrode 21 is formed.
- the insulating film 32 is formed on the back side of the substrate 11 and on the drain electrode 23 .
- the insulating film 32 made of SiN is formed to have a thickness of 10 nm through 10 ⁇ m by plasma CVD.
- the fourth electrode 31 is formed in an area on the insulating film 32 where the drain electrode 23 is not formed. Specifically, photoresist is applied on the surface of the insulating film 32 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the fourth electrode 31 is to be formed. Subsequently, a metal laminated film made of Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the fourth electrode 31 is formed on the insulating film 32 , at a part corresponding to the area where the drain electrode 23 is not formed and the area where the source electrode 21 is formed.
- the insulating film 42 is formed in an area including the fourth electrode 31 , and then by removing part of the insulating films 32 and 42 in the area where the drain electrode 23 is formed, an opening part 43 is formed.
- the insulating film 42 made of SiN is formed by plasma CVD.
- photoresist is applied on the insulating film 42 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part 43 is to be formed.
- dry etching such as RIE is performed by using gas including fluorine to remove part of the insulating films 32 and 42 , so that the surface of the drain electrode 23 is exposed.
- the semiconductor device according to the present embodiment is manufactured.
- the semiconductor device according to the present embodiment has a structure in which the source electrode 21 and the fourth electrode 31 are electrically connected by a via hole (not illustrated) provided in the substrate 11 .
- the gate electrode 22 may be electrically connected to the fourth electrode 31 by a via hole (not illustrated) provided in the substrate 11 .
- a buffer layer (not illustrated) is formed on the substrate 11 made of n + -SiC.
- MOVPE Metal-Organic Vapor Phase Epitaxy
- an opening part 41 is formed in an area where the gate electrode 22 is formed as described below.
- the gate insulating film 15 is formed inside the opening part 41 and on the surface of the n-GaN layer 14 , and the gate electrode 22 is formed inside the opening part 41 via the gate insulating film 15 .
- the source electrode 21 is formed.
- an insulating film 132 to act as a back side insulating film is formed on the back side of the substrate 11 .
- the insulating film 132 made of SiN formed to have a thickness of 10 nm through 10 ⁇ m is formed on the back side of the substrate 11 by plasma CVD.
- a fourth electrode 133 is formed on the insulating film 132 in areas other than the part corresponding to the area where the gate electrode 22 is formed.
- photoresist is applied on the insulating film 132 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where the fourth electrode 133 is to be formed.
- a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the fourth electrode 133 is formed on the insulating film 132 in areas other than the part corresponding to the area where the gate electrode 22 is formed, and at a part corresponding to the area where the source electrode 21 is formed.
- an insulating film 142 is formed on the fourth electrode 133 and the insulating film 132 , and furthermore, the insulating film 132 and the insulating film 142 are removed at parts corresponding to the area where the gate electrode 22 is formed, to form an opening part 143 .
- the insulating film 142 made of SiN is formed on the fourth electrode 133 and the insulating film 132 by plasma CVD.
- photoresist is applied on the surface of the insulating film 142 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part 143 is to be formed.
- dry etching such as RIE is performed by using gas including fluorine, to remove the insulating film 132 and the insulating film 142 in the area where the resist pattern is not formed, so that part of the back side of the substrate 11 is exposed and the opening part 143 is formed.
- a metal laminated film including Au is formed on the insulating film 142 and the exposed back side of the substrate 11 , to form a drain electrode 144 .
- This drain electrode 144 is connected with the substrate 11 whose back side is exposed at the opening part 143 .
- the semiconductor device according to the present embodiment is manufactured.
- the semiconductor device according to the present embodiment has a structure in which the source electrode 21 and the fourth electrode 133 are electrically connected by a via hole (not illustrated) provided in the substrate 11 .
- the gate electrode 22 may be electrically connected to the fourth electrode 133 by a via hole (not illustrated) provided in the substrate 11 .
- a buffer layer (not illustrated) is formed on the substrate 11 made of n + -SiC.
- MOVPE Metal-Organic Vapor Phase Epitaxy
- an opening part 41 is formed in an area where the gate electrode 22 is formed as described below.
- the gate insulating film 15 is formed inside the opening part 41 and on the surface of the n-GaN layer 14 , and the gate electrode 22 is formed inside the opening part 41 via the gate insulating film 15 .
- the source electrode 21 is formed.
- part of the area excluding the part corresponding to the area where the gate electrode 22 is formed is removed by dry etching or ion milling, so that the n-GaN layer 12 is exposed and a back side removal area 230 is formed.
- photoresist is applied on the back side of the substrate 11 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the back side of the substrate 11 is to be removed.
- part of the substrate 11 and the n-GaN layer 12 in the area where the resist pattern is not formed is removed by dry etching, so that the n-GaN layer 12 is exposed and the back side removal area 230 is formed.
- the back side removal area 230 is formed on the back side of the substrate 11 at a part corresponding to an area where the source electrode 21 is formed.
- an insulating film 232 to act as a back side insulating film is formed on the back side of the substrate 11 and the back side removal area 230 where the n-GaN layer 12 is exposed.
- the insulating film 232 made of SiN formed to have a thickness of 10 nm through 10 ⁇ m is formed by plasma CVD.
- a fourth electrode 233 is formed on the insulating film 232 formed on the back side removal area 230 .
- photoresist is applied on the insulating film 232 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where the fourth electrode 233 is to be formed.
- a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off.
- the fourth electrode 233 is formed on the insulating film 232 formed on the back side removal area 230 .
- the fourth electrode 233 formed as described above is formed at a part corresponding to the area where the source electrode 21 is formed.
- an insulating film 242 is formed on the fourth electrode 233 and the insulating film 232 , and furthermore, the insulating film 232 and the insulating film 242 are removed at a part corresponding to the area where the gate electrode 22 is formed, to form an opening part 243 .
- the insulating film 242 made of SiN is formed on the fourth electrode 233 and the insulating film 232 by plasma CVD.
- photoresist is applied on the insulating film 242 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part 243 is to be formed.
- dry etching such as RIE is performed by using gas including fluorine, to remove the insulating film 232 and the insulating film 242 in the area where the resist pattern is not formed, so that part of the back side of the substrate 11 is exposed and the opening part 243 is formed.
- a drain electrode 244 to be connected to the opening part 243 where the back side of the substrate 11 is exposed is formed.
- photoresist is applied on the surface of the insulating film 242 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the drain electrode 244 is to be formed.
- a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the drain electrode 244 is formed, which is connected to the opening part 243 where the back side of the substrate 11 is exposed.
- the semiconductor device according to the present embodiment is manufactured.
- the semiconductor device according to the present embodiment has a structure in which the source electrode 21 and the fourth electrode 233 are electrically connected by a via hole (not illustrated) provided in the substrate 11 .
- the gate electrode 22 may be electrically connected to the fourth electrode 233 by a via hole (not illustrated) provided in the substrate 11 .
- a buffer layer (not illustrated) is formed on the substrate 11 made of n + -SiC.
- MOVPE Metal-Organic Vapor Phase Epitaxy
- an opening part 41 is formed in an area where the gate electrode 22 is formed as described below.
- the gate insulating film 15 is formed inside the opening part 41 and on the surface of the n-GaN layer 14 , and the gate electrode 22 is formed inside the opening part 41 via the gate insulating film 15 .
- the source electrode 21 is formed. Specifically, photoresist is applied on the surface of the gate insulating film 15 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the source electrode 21 is to be formed.
- the drain electrode 23 is formed at a part corresponding to the area where the gate electrode 22 is formed.
- the drain electrode 23 is not formed at a part corresponding to an area where the source electrode 21 is formed.
- the insulating film 32 is formed on the back side of the substrate 11 and on the drain electrode 23 .
- the insulating film 32 made of SiN is formed to have a thickness of 10 nm through 10 ⁇ m by plasma CVD.
- an opening part 343 is formed by removing part of the insulating film 32 in the area where the drain electrode 23 is formed. Specifically, photoresist is applied on the insulating film 32 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part 343 is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove the insulating film 32 in an area where the resist pattern is not formed, so that part of the surface of the drain electrode 23 is exposed.
- RIE reactive etching
- the semiconductor device according to the present embodiment is manufactured.
- the drain electrode 23 is formed on the back side of the substrate 11 at a part corresponding to the area where the gate electrode 22 is formed, and is not formed at a part corresponding to the area where the source electrode 21 is formed. Therefore, it is possible to decrease the leakage current flowing between the source and the drain without providing a fourth electrode.
- a buffer layer (not illustrated) is formed on the substrate 11 made of n + -SiC.
- MOVPE Metal-Organic Vapor Phase Epitaxy
- an opening part 41 is formed in an area where the gate electrode 22 is formed as described below.
- the gate insulating film 15 is formed inside the opening part 41 and on the surface of the n-GaN layer 14 , and the gate electrode 22 is formed inside the opening part 41 via the gate insulating film 15 .
- the source electrode 21 is formed.
- part of the area excluding the part corresponding to the area where the gate electrode 22 is formed is removed by dry etching or ion milling, so that the n-GaN layer 12 is exposed and a back side removal area 230 is formed.
- photoresist is applied on the back side of the substrate 11 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the back side of the substrate 11 is to be removed.
- part of the substrate 11 and the n-GaN layer 12 in the area where the resist pattern is not formed is removed by dry etching, so that the back side removal area 230 is formed.
- the back side removal area 230 is formed at a part corresponding to an area where the source electrode 21 is formed.
- an insulating film 232 is formed on the back side of the substrate 11 and the back side removal area 230 where the n-GaN layer 12 is exposed. Specifically, the insulating film 232 made of SiN formed to have a thickness of 10 nm through 10 ⁇ m is formed by plasma CVD.
- an opening part 443 is formed.
- photoresist is applied on the insulating film 232 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the opening part 443 is to be formed.
- dry etching such as RIE is performed by using gas including fluorine to remove the insulating film 232 in the area where the resist pattern is not formed, so that the back side of the substrate 11 is exposed and the opening part 443 is formed.
- a drain electrode 444 is formed, which is to be connected at the opening part 443 where the back side of the substrate 11 is exposed.
- photoresist is applied on the surface of the insulating film 232 , and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the drain electrode 444 is to be formed.
- a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, the drain electrode 444 is formed.
- the drain electrode 444 is connected to the back side of the substrate 11 , at the opening part 443 where the back side of the substrate 11 is exposed.
- the semiconductor device according to the present embodiment is manufactured.
- the drain electrode 444 is formed on the back side of the substrate 11 at a part corresponding to the area where the gate electrode 22 is formed, and is not formed at a part corresponding to the area where the source electrode 21 is formed. Therefore, it is possible to decrease the leakage current flowing between the source and the drain without providing a fourth electrode.
- a semiconductor device and a manufacturing method of a semiconductor device are provided, in which the insulation breakdown voltage is high, the chip size is small, and the amount of leakage current is small.
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Abstract
A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
Description
- This patent application is a Divisional Application of the U.S. patent application Ser. No. 13/869,271 filed on Apr. 24, 2013 and based upon and claims the benefit of priority under 35 USC 120 and 365(c) of PCT application PCT/JP2010/069733 filed in Japan on Nov. 5, 2010, the entire contents of which are incorporated herein by reference.
- The embodiments discussed herein are related to a semiconductor device.
- Nitride semiconductors such as GaN, AlN, and InN have a wide band gap and good material properties, and may therefore be used for high breakdown voltage electronic devices or short-wavelength light emitting devices. Particularly, as to field effect transistors (FET) to be used as high breakdown voltage electronic devices, studies are being made in regard to High Electron Mobility Transistors (HEMT), which may be used for high output/high efficiency amplifiers and high power switching devices.
- Incidentally, in a conventional HEMT having a horizontal structure (a structure in which the current flows substantially parallel to the substrate surface), when a sufficient amount of breakdown voltage is to be secured for use in high power/high breakdown voltage switching devices, a long inter-electrode length is to be formed. In this case, the chip size of the device to be formed is increased, and the number of chips that may be manufactured from one wafer is decreased, which leads to an increase in the manufacturing cost, resulting in high cost.
- Therefore, in high power/high breakdown voltage switching devices, a field effect transistor having a vertical structure (a structure in which the current flows substantially perpendicular to the substrate surface) is garnering attention, because the chip size may be decreased with such a structure.
- Patent document 1: Japanese Laid-Open Patent Publication No. 2002-359256
- Patent document 2: Japanese Laid-Open Patent Publication No. 2008-53448
- Non-patent document 1: Applied Physics Express 1 (2008) 011105
- Non-patent document 2: Applied Physics Express 1 (2008) 021104
- For example, a field effect transistor having a vertical structure has a source electrode formed on one side of a substrate and a drain electrode formed on the other side of the substrate. Specifically, a description is given of a field effect transistor having a vertical structure, with reference to
FIG. 1 . - In the field effect transistor having a vertical structure, on a
substrate 611 constituted by n+-SiC or n+-GaN, a n-GaN layer 612, a p-GaN layer 613, and a n-GaN layer 614 are formed. On part of the surface of the n-GaN layer 614, asource electrode 621 is formed. Furthermore, an opening part is formed by etching part of the n-GaN layer 614, the p-GaN layer 613, and theGaN layer 612 from the surface of the n-GaN layer 614. An insulatingfilm 615 is formed so as to cover the surface of the n-GaN layer 614 and the surface of the inside of the opening part. Furthermore, in the opening part, agate electrode 622 is formed via the insulatingfilm 615. On the back side of thesubstrate 611, i.e., on the side opposite to the side on which the semiconductor layer is formed, adrain electrode 623 is formed. - In a field effect transistor having the above structure, when a voltage is applied between the
source electrode 621 and thedrain electrode 623, regardless of the potential of thegate electrode 622, a leakage current passing the p-GaN layer 613 is generated. That is to say, in an area other than the area that is the current path indicated by a dashed-line arrow A, a leakage current flowing through the p-GaN layer 613 indicated by a dashed-line arrow B is generated. When such a leakage current is generated, properties of the field effect transistor are degraded. - Thus, there is demand for a semiconductor device and a manufacturing method of a semiconductor device having a high insulation breakdown voltage, a small chip size, and a small amount of leakage current.
- According to an aspect of the embodiments, a semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
- The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.
-
FIG. 1 is a structural diagram of a field effect transistor having a vertical structure; -
FIG. 2 is a structural diagram of a semiconductor device according to a first embodiment; -
FIGS. 3A through 3C are manufacturing procedure diagrams of a semiconductor device according to a first embodiment (1); -
FIGS. 4A through 4C are manufacturing procedure diagrams of a semiconductor device according to the first embodiment (2); -
FIGS. 5A and 5B are manufacturing procedure diagrams of a semiconductor device according to the first embodiment (3); -
FIGS. 6A through 6C are manufacturing procedure diagrams of a semiconductor device according to a second embodiment (1); -
FIGS. 7A through 7C are manufacturing procedure diagrams of a semiconductor device according to the second embodiment (2); -
FIGS. 8A and 8B are manufacturing procedure diagrams of a semiconductor device according to the second embodiment (3); -
FIGS. 9A through 9C are manufacturing procedure diagrams of a semiconductor device according to a third embodiment (1); -
FIGS. 10A through 10C are manufacturing procedure diagrams of a semiconductor device according to the third embodiment (2); -
FIGS. 11A through 11C are manufacturing procedure diagrams of a semiconductor device according to the third embodiment (3); -
FIGS. 12A through 12C are manufacturing procedure diagrams of a semiconductor device according to a fourth embodiment (1); -
FIGS. 13A through 13C are manufacturing procedure diagrams of a semiconductor device according to the fourth embodiment (2); -
FIG. 14 is a manufacturing procedure diagram of a semiconductor device according to the fourth embodiment (3); -
FIGS. 15A through 15C are manufacturing procedure diagrams of a semiconductor device according to a fifth embodiment (1); -
FIGS. 16A through 16C are manufacturing procedure diagrams of a semiconductor device according to the fifth embodiment (2); and -
FIGS. 17A and 17B are manufacturing procedure diagrams of a semiconductor device according to the fifth embodiment (3). - Embodiments of the present invention will be explained with reference to accompanying drawings. The same elements are denoted by the same reference numerals and overlapping descriptions are omitted.
- A description is given of a semiconductor device according to the present embodiment. As illustrated in
FIG. 2 , a semiconductor device according to the present embodiment is a field effect transistor having a vertical structure. Specifically, on asubstrate 11 constituted by n+-SiC or n+-GaN, a n-GaN layer 12, a p-GaN layer 13, and a n-GaN layer 14 are formed. On part of the surface of the n-GaN layer 14, asource electrode 21 is formed. Furthermore, an opening part is formed by etching part of the p-GaN layer 13 and the n-GaN layer 12 from the surface of the n-GaN layer 14. Agate insulating film 15 is formed so as to cover the surface of the n-GaN layer 14 and the surface of the inside of the opening part. In the opening part, agate electrode 22 is formed via thegate insulating film 15. - On the back side of the
substrate 11, i.e., on the side opposite to the side on which the semiconductor layer is formed, adrain electrode 23 is formed in a part corresponding to the area where thegate electrode 22 is formed and an area surrounding thegate electrode 22. Furthermore, in a part corresponding to an area other than where thedrain electrode 23, and the area where thesource electrode 21 is formed and areas surrounding thesource electrode 21, afourth electrode 31 is formed via an insulatingfilm 32 which acts as a back side insulating film. Between thedrain electrode 23 and thefourth electrode 31, insulation properties are maintained by the insulatingfilm 32. - In the semiconductor device according to the present embodiment, a potential, which is substantially the same as the potential applied to the
source electrode 21 or thegate electrode 22, is applied to thefourth electrode 31. Accordingly, when a potential that causes an on state is applied to thegate electrode 22, a current flows through the p-GaN layer 13 near thegate electrode 22 via thegate insulating film 15, as indicated by a dashed-line arrow C. However, a leakage current hardly flows in the p-GaN layer 13 in areas outside the above area. - When the same potential as that of the
source electrode 21 is applied to thefourth electrode 31, and a potential that causes an on state is applied to thegate electrode 22, a current flows from thesource electrode 21 to thedrain electrode 23 in the p-GaN layer 13 near thegate electrode 22 via thegate insulating film 15. However, thefourth electrode 31 and thesource electrode 21 have the same potential, and the insulatingfilm 32 is formed, and therefore a current does not flow from thesource electrode 21 to thefourth electrode 31. - Therefore, when a potential, which turns off the current flowing between the
source electrode 21 and thedrain electrode 23, is applied to thegate electrode 22, in this case also, a current hardly flows between thesource electrode 21 and thedrain electrode 23. That is to say, in the semiconductor device according to the present embodiment, in the on state, as indicated by a dashed-line arrow C, a current flows in an area of the p-GaN layer 13 via thegate insulating film 15 near thegate electrode 22, but a current does not flow in areas other than this area. Therefore, the leakage current is significantly decreased in the off state, and therefore device properties are improved. - Furthermore, the same applies to a case where the potential applied to the
fourth electrode 31 is substantially the same as the potential applied to thegate electrode 22. In this case also, as indicated by the dashed-line arrow C, it is possible to make a current flow only to the p-GaN layer 13 near thegate electrode 22. Accordingly, it is possible to decrease the leakage current. If the potential applied to thefourth electrode 31 is less than or equal to the potential applied to thedrain electrode 23 and greater than or equal to the potential applied to thesource electrode 21 or thegate electrode 22, the same effects are achieved. - Next, a description is given of a manufacturing method of a semiconductor device according to the present embodiment, with reference to
FIGS. 3A through 5B . - First, as illustrated in
FIG. 3A , on thesubstrate 11 made of n+-SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer 12, the p-GaN layer 13, and the n-GaN layer 14 are laminated. - The n-
GaN layer 12 is formed to have a thickness of 1 μm through 10 μm, and 1×1017 cm−3 through 1×1020 cm−3 of Si is doped as an impurity element. The p-GaN layer 13 is formed to have a thickness of 10 nm through 1 μm, and approximately 1×1019 cm−3 of Mg is doped as an impurity element. The n-GaN layer 14 is formed to have a thickness of 10 nm through 1 μm, and 1×1017 cm−3 through 1×1020 cm−3 of Si is doped as an impurity element. - Next, as illustrated in
FIG. 3B , anopening part 41 is formed in an area where thegate electrode 22 is formed as described below. Specifically, photoresist is applied on the n-GaN layer 14, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where theopening part 41 is to be formed. Subsequently, dry etching such as RIE (Reactive Ion Etching) is performed with the use of gas including chlorine, to remove part of the n-GaN layer 14, the p-GaN layer 13, and the n-GaN layer 12, and form theopening part 41. - Next, as illustrated in
FIG. 3C , thegate insulating film 15 is formed inside the openingpart 41 and on the surface of the n-GaN layer 14, and thegate electrode 22 is formed inside the openingpart 41 via thegate insulating film 15. Specifically, by plasma CVD (Chemical Vapor Deposition), thegate insulating film 15 made of SiN is formed to have a thickness of 1 nm through 1 μm, inside the openingpart 41 and on the surface of the n-GaN layer 14. Subsequently, photoresist is applied on the surface of thegate insulating film 15, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where thegate electrode 22 is to be formed. Furthermore, subsequently, a metal film made of Ni is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thegate electrode 22 is formed in theopening part 41 via thegate insulating film 15. - Next, as illustrated in
FIG. 4A , thesource electrode 21 is formed. Specifically, photoresist is applied on the surface of thegate insulating film 15, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where thesource electrode 21 is to be formed. Subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove thegate insulating film 15 so that the surface of the n-GaN layer 14 is exposed. Furthermore, subsequently, a metal film made of Ti/Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thesource electrode 21 is formed on the n-GaN layer 14, and subsequently, ohmic contact is realized by performing a heat treatment in a nitrogen atmosphere. - Next, as illustrated in
FIG. 4B , on the back side of thesubstrate 11, thedrain electrode 23 is formed at a part corresponding to the area where thegate electrode 22 is formed. Specifically, photoresist is applied on the back side of thesubstrate 11, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where thedrain electrode 23 is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, on the back side of thesubstrate 11, thedrain electrode 23 is formed at a part corresponding to the area where thegate electrode 22 is formed. At this time, thedrain electrode 23 is not formed at the part corresponding to the area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 4C , the insulatingfilm 32 is formed on the back side of thesubstrate 11 and on thedrain electrode 23. Specifically, on the back side of thesubstrate 11 and on thedrain electrode 23, the insulatingfilm 32 made of SiN is formed to have a thickness of 10 nm through 10 μm by plasma CVD. - Next, as illustrated in
FIG. 5A , thefourth electrode 31 is formed in an area on the insulatingfilm 32 where thedrain electrode 23 is not formed. Specifically, photoresist is applied on the surface of the insulatingfilm 32, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where thefourth electrode 31 is to be formed. Subsequently, a metal laminated film made of Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thefourth electrode 31 is formed on the insulatingfilm 32, at a part corresponding to the area where thedrain electrode 23 is not formed and the area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 5B , the insulatingfilm 42 is formed in an area including thefourth electrode 31, and then by removing part of the insulatingfilms drain electrode 23 is formed, anopening part 43 is formed. Specifically, in an area including thefourth electrode 31, the insulatingfilm 42 made of SiN is formed by plasma CVD. Subsequently, photoresist is applied on the insulatingfilm 42, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where theopening part 43 is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove part of the insulatingfilms drain electrode 23 is exposed. - As described above, the semiconductor device according to the present embodiment is manufactured. The semiconductor device according to the present embodiment has a structure in which the
source electrode 21 and thefourth electrode 31 are electrically connected by a via hole (not illustrated) provided in thesubstrate 11. However, as another structure of the semiconductor device according to the present embodiment, thegate electrode 22 may be electrically connected to thefourth electrode 31 by a via hole (not illustrated) provided in thesubstrate 11. - Next, a description is given of a manufacturing method of a semiconductor device according to a second embodiment, with reference to
FIGS. 6A through 8B . - First, as illustrated in
FIG. 6A , on thesubstrate 11 made of n+-SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer 12, the p-GaN layer 13, and the n-GaN layer 14 are laminated. - Next, as illustrated in
FIG. 6B , anopening part 41 is formed in an area where thegate electrode 22 is formed as described below. - Next, as illustrated in
FIG. 6C , thegate insulating film 15 is formed inside the openingpart 41 and on the surface of the n-GaN layer 14, and thegate electrode 22 is formed inside the openingpart 41 via thegate insulating film 15. - Next, as illustrated in
FIG. 7A , thesource electrode 21 is formed. - Next, as illustrated in
FIG. 7B , on the back side of thesubstrate 11, an insulatingfilm 132 to act as a back side insulating film is formed. Specifically, the insulatingfilm 132 made of SiN formed to have a thickness of 10 nm through 10 μm is formed on the back side of thesubstrate 11 by plasma CVD. - Next, as illustrated in
FIG. 7C , afourth electrode 133 is formed on the insulatingfilm 132 in areas other than the part corresponding to the area where thegate electrode 22 is formed. Specifically, photoresist is applied on the insulatingfilm 132, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where thefourth electrode 133 is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thefourth electrode 133 is formed on the insulatingfilm 132 in areas other than the part corresponding to the area where thegate electrode 22 is formed, and at a part corresponding to the area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 8A , an insulatingfilm 142 is formed on thefourth electrode 133 and the insulatingfilm 132, and furthermore, the insulatingfilm 132 and the insulatingfilm 142 are removed at parts corresponding to the area where thegate electrode 22 is formed, to form anopening part 143. Specifically, the insulatingfilm 142 made of SiN is formed on thefourth electrode 133 and the insulatingfilm 132 by plasma CVD. Subsequently, photoresist is applied on the surface of the insulatingfilm 142, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where theopening part 143 is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove the insulatingfilm 132 and the insulatingfilm 142 in the area where the resist pattern is not formed, so that part of the back side of thesubstrate 11 is exposed and theopening part 143 is formed. - Next, as illustrated in
FIG. 8B , a metal laminated film including Au is formed on the insulatingfilm 142 and the exposed back side of thesubstrate 11, to form adrain electrode 144. Thisdrain electrode 144 is connected with thesubstrate 11 whose back side is exposed at theopening part 143. - As described above, the semiconductor device according to the present embodiment is manufactured. The semiconductor device according to the present embodiment has a structure in which the
source electrode 21 and thefourth electrode 133 are electrically connected by a via hole (not illustrated) provided in thesubstrate 11. However, as another structure of the semiconductor device according to the present embodiment, thegate electrode 22 may be electrically connected to thefourth electrode 133 by a via hole (not illustrated) provided in thesubstrate 11. - Contents other than the above are the same as the first embodiment.
- Next, a description is given of a manufacturing method of a semiconductor device according to a third embodiment, with reference to
FIGS. 9A through 11C . - First, as illustrated in
FIG. 9A , on thesubstrate 11 made of n+-SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer 12, the p-GaN layer 13, and the n-GaN layer 14 are laminated. - Next, as illustrated in
FIG. 9B , anopening part 41 is formed in an area where thegate electrode 22 is formed as described below. - Next, as illustrated in
FIG. 9C , thegate insulating film 15 is formed inside the openingpart 41 and on the surface of the n-GaN layer 14, and thegate electrode 22 is formed inside the openingpart 41 via thegate insulating film 15. - Next, as illustrated in
FIG. 10A , thesource electrode 21 is formed. - Next, as illustrated in
FIG. 10B , on the back side of thesubstrate 11, part of the area excluding the part corresponding to the area where thegate electrode 22 is formed is removed by dry etching or ion milling, so that the n-GaN layer 12 is exposed and a backside removal area 230 is formed. Specifically, photoresist is applied on the back side of thesubstrate 11, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the back side of thesubstrate 11 is to be removed. Subsequently, part of thesubstrate 11 and the n-GaN layer 12 in the area where the resist pattern is not formed is removed by dry etching, so that the n-GaN layer 12 is exposed and the backside removal area 230 is formed. The backside removal area 230 is formed on the back side of thesubstrate 11 at a part corresponding to an area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 10C , on the back side of thesubstrate 11 and the backside removal area 230 where the n-GaN layer 12 is exposed, an insulatingfilm 232 to act as a back side insulating film is formed. Specifically, the insulatingfilm 232 made of SiN formed to have a thickness of 10 nm through 10 μm is formed by plasma CVD. - Next, as illustrated in
FIG. 11A , afourth electrode 233 is formed on the insulatingfilm 232 formed on the backside removal area 230. Specifically, photoresist is applied on the insulatingfilm 232, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening at the part where thefourth electrode 233 is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thefourth electrode 233 is formed on the insulatingfilm 232 formed on the backside removal area 230. Thefourth electrode 233 formed as described above is formed at a part corresponding to the area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 11B , an insulatingfilm 242 is formed on thefourth electrode 233 and the insulatingfilm 232, and furthermore, the insulatingfilm 232 and the insulatingfilm 242 are removed at a part corresponding to the area where thegate electrode 22 is formed, to form anopening part 243. Specifically, the insulatingfilm 242 made of SiN is formed on thefourth electrode 233 and the insulatingfilm 232 by plasma CVD. Subsequently, photoresist is applied on the insulatingfilm 242, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where theopening part 243 is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine, to remove the insulatingfilm 232 and the insulatingfilm 242 in the area where the resist pattern is not formed, so that part of the back side of thesubstrate 11 is exposed and theopening part 243 is formed. - Next, as illustrated in
FIG. 11C , adrain electrode 244 to be connected to theopening part 243 where the back side of thesubstrate 11 is exposed, is formed. Specifically, photoresist is applied on the surface of the insulatingfilm 242, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where thedrain electrode 244 is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thedrain electrode 244 is formed, which is connected to theopening part 243 where the back side of thesubstrate 11 is exposed. - As described above, the semiconductor device according to the present embodiment is manufactured. The semiconductor device according to the present embodiment has a structure in which the
source electrode 21 and thefourth electrode 233 are electrically connected by a via hole (not illustrated) provided in thesubstrate 11. However, as another structure of the semiconductor device according to the present embodiment, thegate electrode 22 may be electrically connected to thefourth electrode 233 by a via hole (not illustrated) provided in thesubstrate 11. - Contents other than the above are the same as the first embodiment.
- Next, a description is given of a manufacturing method of a semiconductor device according to a fourth embodiment, with reference to
FIGS. 12A through 14 . - First, as illustrated in
FIG. 12A , on thesubstrate 11 made of n+-SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer 12, the p-GaN layer 13, and the n-GaN layer 14 are laminated. - Next, as illustrated in
FIG. 12B , anopening part 41 is formed in an area where thegate electrode 22 is formed as described below. - Next, as illustrated in
FIG. 12C , thegate insulating film 15 is formed inside the openingpart 41 and on the surface of the n-GaN layer 14, and thegate electrode 22 is formed inside the openingpart 41 via thegate insulating film 15. - Next, as illustrated in
FIG. 13A , thesource electrode 21 is formed. Specifically, photoresist is applied on the surface of thegate insulating film 15, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where thesource electrode 21 is to be formed. - Next, as illustrated in
FIG. 13B , on the back side of thesubstrate 11, thedrain electrode 23 is formed at a part corresponding to the area where thegate electrode 22 is formed. Thedrain electrode 23 is not formed at a part corresponding to an area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 13C , the insulatingfilm 32 is formed on the back side of thesubstrate 11 and on thedrain electrode 23. Specifically, on the back side of thesubstrate 11 and on thedrain electrode 23, the insulatingfilm 32 made of SiN is formed to have a thickness of 10 nm through 10 μm by plasma CVD. - Next, as illustrated in
FIG. 14 , anopening part 343 is formed by removing part of the insulatingfilm 32 in the area where thedrain electrode 23 is formed. Specifically, photoresist is applied on the insulatingfilm 32, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where theopening part 343 is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove the insulatingfilm 32 in an area where the resist pattern is not formed, so that part of the surface of thedrain electrode 23 is exposed. - As described above, the semiconductor device according to the present embodiment is manufactured. In the semiconductor device according to the present embodiment, the
drain electrode 23 is formed on the back side of thesubstrate 11 at a part corresponding to the area where thegate electrode 22 is formed, and is not formed at a part corresponding to the area where thesource electrode 21 is formed. Therefore, it is possible to decrease the leakage current flowing between the source and the drain without providing a fourth electrode. - Contents other than the above are the same as the first embodiment.
- Next, a description is given of a manufacturing method of a semiconductor device according to a fifth embodiment, with reference to
FIGS. 15A through 17B . - First, as illustrated in
FIG. 15A , on thesubstrate 11 made of n+-SiC, by a MOVPE (Metal-Organic Vapor Phase Epitaxy) method, a buffer layer (not illustrated) is formed. On this buffer layer, the n-GaN layer 12, the p-GaN layer 13, and the n-GaN layer 14 are laminated. - Next, as illustrated in
FIG. 15B , anopening part 41 is formed in an area where thegate electrode 22 is formed as described below. - Next, as illustrated in
FIG. 15C , thegate insulating film 15 is formed inside the openingpart 41 and on the surface of the n-GaN layer 14, and thegate electrode 22 is formed inside the openingpart 41 via thegate insulating film 15. - Next, as illustrated in
FIG. 16A , thesource electrode 21 is formed. - Next, as illustrated in
FIG. 16B , on the back side of thesubstrate 11, part of the area excluding the part corresponding to the area where thegate electrode 22 is formed is removed by dry etching or ion milling, so that the n-GaN layer 12 is exposed and a backside removal area 230 is formed. Specifically, photoresist is applied on the back side of thesubstrate 11, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where the back side of thesubstrate 11 is to be removed. Subsequently, part of thesubstrate 11 and the n-GaN layer 12 in the area where the resist pattern is not formed is removed by dry etching, so that the backside removal area 230 is formed. The backside removal area 230 is formed at a part corresponding to an area where thesource electrode 21 is formed. - Next, as illustrated in
FIG. 16C , on the back side of thesubstrate 11 and the backside removal area 230 where the n-GaN layer 12 is exposed, an insulatingfilm 232 is formed. Specifically, the insulatingfilm 232 made of SiN formed to have a thickness of 10 nm through 10 μm is formed by plasma CVD. - Next, as illustrated in
FIG. 17A , by removing the insulatingfilm 232 at a part corresponding to the area where thegate electrode 22 is formed, anopening part 443 is formed. Specifically, photoresist is applied on the insulatingfilm 232, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where theopening part 443 is to be formed. Furthermore, subsequently, dry etching such as RIE is performed by using gas including fluorine to remove the insulatingfilm 232 in the area where the resist pattern is not formed, so that the back side of thesubstrate 11 is exposed and theopening part 443 is formed. - Next, as illustrated in
FIG. 17B , adrain electrode 444 is formed, which is to be connected at theopening part 443 where the back side of thesubstrate 11 is exposed. Specifically, photoresist is applied on the surface of the insulatingfilm 232, and exposing and developing is performed with an exposing device, to form a resist pattern having an opening in the area where thedrain electrode 444 is to be formed. Subsequently, a metal laminated film including Au is formed by vacuum vapor deposition, and by dipping this in an organic solvent, the metal laminated film formed on the resist pattern is removed together with the resist pattern by being lifted off. Accordingly, thedrain electrode 444 is formed. Thedrain electrode 444 is connected to the back side of thesubstrate 11, at theopening part 443 where the back side of thesubstrate 11 is exposed. - As described above, the semiconductor device according to the present embodiment is manufactured. In the semiconductor device according to the present embodiment, the
drain electrode 444 is formed on the back side of thesubstrate 11 at a part corresponding to the area where thegate electrode 22 is formed, and is not formed at a part corresponding to the area where thesource electrode 21 is formed. Therefore, it is possible to decrease the leakage current flowing between the source and the drain without providing a fourth electrode. - Contents other than the above are the same as the third embodiment.
- According to an aspect of the embodiments, a semiconductor device and a manufacturing method of a semiconductor device are provided, in which the insulation breakdown voltage is high, the chip size is small, and the amount of leakage current is small.
- The present invention is not limited to the specific embodiments described herein, and variations and modifications may be made without departing from the scope of the present invention.
- All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
Claims (12)
1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity;
a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer;
an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer;
a gate insulating film formed so as to cover an inner wall of the opening part;
a gate electrode formed inside the opening part via the gate insulating film;
a source electrode formed on a surface of the third semiconductor layer;
a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and
a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.
2. The semiconductor device according to claim 1 , wherein
the fourth electrode is formed on a back side insulating film which is formed on the another side of the semiconductor substrate.
3. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity;
a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer;
an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer;
a gate insulating film formed so as to cover an inner wall of the opening part;
a gate electrode formed inside the opening part via the gate insulating film;
a source electrode formed on a surface of the third semiconductor layer;
a back side removal area formed by removing, from another side of the semiconductor substrate, part of the semiconductor substrate and the first semiconductor layer at a part corresponding to the source electrode;
a fourth electrode formed in the back side removal area where the first semiconductor layer is exposed; and
a drain electrode connected to a part corresponding to the gate electrode on the another side of the semiconductor substrate.
4. The semiconductor device according to claim 3 , wherein
the fourth electrode is formed on a back side insulating film where the first semiconductor layer is exposed.
5. The semiconductor device according to claim 1 , wherein
a potential applied to the fourth electrode is between a potential applied to the drain electrode and a potential applied to the source electrode.
6. The semiconductor device according to claim 1 , wherein
a potential applied to the fourth electrode is a potential applied to the source electrode or a potential applied to the gate electrode.
7. The semiconductor device according to claim 1 , wherein
an insulating film is formed between the drain electrode and the fourth electrode.
8. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity;
a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer;
an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer;
a gate insulating film formed so as to cover an inner wall of the opening part;
a gate electrode formed inside the opening part via the gate insulating film;
a source electrode formed on a surface of the third semiconductor layer; and
a drain electrode connected to a part corresponding to the gate electrode, and not connected to a part corresponding to the source electrode, on another side of the semiconductor substrate.
9. The semiconductor device according to claim 8 , wherein
a back side insulating film is formed at a part corresponding to the source electrode on the another side of the semiconductor substrate.
10. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate having conductivity;
a second semiconductor layer of a second conductivity type formed on the first semiconductor layer;
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer;
an opening part formed by removing part of the third semiconductor layer, the second semiconductor layer, and the first semiconductor layer;
a gate insulating film formed so as to cover an inner wall of the opening part;
a gate electrode formed inside the opening part via the gate insulating film;
a source electrode formed on a surface of the third semiconductor layer;
a back side removal area formed by removing, from another side of the semiconductor substrate, part of the semiconductor substrate and the first semiconductor layer at a part corresponding to the source electrode; and
a drain electrode connected to a part corresponding to the gate electrode on the another side of the semiconductor substrate.
11. The semiconductor device according to claim 10 wherein
a back side insulating film is formed in the back side removal area where the first semiconductor layer is exposed.
12. The semiconductor device according to claim 1 wherein
the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are formed with a material including GaN.
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US15/386,004 US20170104098A1 (en) | 2010-11-05 | 2016-12-21 | Semiconductor device |
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PCT/JP2010/069733 WO2012060014A1 (en) | 2010-11-05 | 2010-11-05 | Semiconductor device and method for manufacturing semiconductor device |
US13/869,271 US9564527B2 (en) | 2010-11-05 | 2013-04-24 | Semiconductor device and manufacturing method of semiconductor device |
US15/386,004 US20170104098A1 (en) | 2010-11-05 | 2016-12-21 | Semiconductor device |
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US13/869,271 Division US9564527B2 (en) | 2010-11-05 | 2013-04-24 | Semiconductor device and manufacturing method of semiconductor device |
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US15/386,004 Abandoned US20170104098A1 (en) | 2010-11-05 | 2016-12-21 | Semiconductor device |
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JP2012175089A (en) * | 2011-02-24 | 2012-09-10 | Fujitsu Ltd | Semiconductor device and method of manufacturing semiconductor device |
JP6054621B2 (en) * | 2012-03-30 | 2016-12-27 | トランスフォーム・ジャパン株式会社 | Compound semiconductor device and manufacturing method thereof |
JP2015130374A (en) * | 2014-01-06 | 2015-07-16 | 日本電信電話株式会社 | Method for manufacturing nitride semiconductor device |
US10608102B2 (en) * | 2017-09-29 | 2020-03-31 | Electronics And Telecommunications Research Institute | Semiconductor device having a drain electrode contacting an epi material inside a through-hole and method of manufacturing the same |
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Also Published As
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US20130228795A1 (en) | 2013-09-05 |
JPWO2012060014A1 (en) | 2014-05-12 |
JP5668758B2 (en) | 2015-02-12 |
CN103201841A (en) | 2013-07-10 |
US9564527B2 (en) | 2017-02-07 |
WO2012060014A1 (en) | 2012-05-10 |
CN103201841B (en) | 2016-06-22 |
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