JP4908856B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a heterostructure field effect transistor and a manufacturing method thereof.

  Nitride semiconductors have a band gap from the far-infrared region to the ultraviolet region, and are expected to be applied as materials for light-receiving / light-emitting elements in such a band-gap region. In addition, since it has a strong atomic bonding force, a high dielectric breakdown electric field, and a high saturation electron velocity, it is considered to be promising as a material for electronic devices such as high temperature resistance, high output, and high frequency transistors.

  In particular, in the use of electronic devices, a high-output heterostructure field effect transistor (HFET: Heterostructure) having a high output of several hundred mW or more is aimed at application to an amplifier for a mobile phone base station as an electronic device for high frequency and high output. Field Effect Transistor (hereinafter sometimes abbreviated as HFET) is under development. In addition, as one of low frequency application examples, application to a switching element is also being considered, and application as a high output element is greatly expected.

  HFETs are usually fabricated by MOCVD (Metal-Organic Chemical Vapor Deposition), but in order to enable applications in the above-described fields, it is necessary to reduce the sheet resistance of the HFET channel. There is a strong demand. Because, by reducing the sheet resistance of the HFET channel, it is possible to increase the gain, increase the transistor current, and reduce the contact resistance of the source electrode and drain electrode, and as a result, high frequency characteristics, output characteristics, and power efficiency as an electronic device It is because it can improve greatly. In order to reduce the sheet resistance, it is necessary to increase the concentration of a two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) or increase the electron mobility.

  2DEG is induced not only by modulation doping to the AlGaN barrier layer of the AlGaN / GaN HFET structure but also by a polarization electric field generated at the interface between the AlGaN barrier layer and the GaN buffer layer. The concentration of 2DEG is AlGaN It also depends greatly on the AlN composition and film thickness of the barrier layer. That is, by increasing the AlN composition and the film thickness, the concentration of 2DEG increases, and the sheet resistance of the HFET structure can be reduced.

However, the structure of the AlGaN barrier layer greatly affects the transistor characteristics of the AlGaN / GaN HFET structure. When the thickness of the AlGaN barrier layer is increased, the mutual conductance (g _m ) is lowered, and it is difficult to improve the high frequency characteristics. Further, when the AlN composition of the AlGaN barrier layer is increased, the lattice mismatch with the GaN buffer layer is increased. Large lattice mismatch causes problems such as difficulty in growing a high-quality product or being liable to cause crystal deterioration during a process or device operation. In addition, since the increase in the Si modulation doping concentration leads to deterioration of the crystallinity of the AlGaN barrier layer (barrier layer), gate leakage, and the like, there is a limit to the increase in the Si modulation doping concentration.

Moreover, even if an AlGaN / GaN HFET structure with a low sheet resistance is fabricated, a phenomenon has been reported that the sheet resistance increases due to annealing in a nitrogen atmosphere (Non-Patent Documents 1 and 2). The cause of such an increase in sheet resistance is that the surface state changes due to the desorption and surface oxidation of surface nitrogen atoms during heat treatment, the channel potential state changes, and the activity of the carrier in the modulation doped layer It has been reported that the conversion rate decreases (Non-Patent Documents 3 and 4). Annealing is an essential process in forming ohmic contacts for source and drain electrodes in an HFET structure. Therefore, in the current process technology, an increase in sheet resistance during heat treatment is unavoidable.
K. Shiojima et al., “Thermal Stability of Electrical Properties in AlGaN / GaN Heterostructures”, Japanese J. of Appl. Phys., Vol. 43, no. 1 (2004), p. p. 100. K. Shiojima et al., “Systematic study of thermal stability of AlGaN / GaN two-dimensional electron gas structure with SiN surface passivation”, IEICE Electronics Express, Vol. 1, No. 1 7 (2004), p. p. 160 T. Hashizume et al., “Effects of nitrogen deficiency on electronic properties of AlGaN surface subjected to thermal and plasma processes”, App1. Surface Science, 234 (2004), p. p. 387 VMBermudez, “Study of oxygenchemisorption on the GaN (0001)-(1 × 1) surface”, J. App 1. Phys., 80 (2) 15 July (1996), p. p. 1190

  As described above, in the HFET structure manufactured by the conventional technique, reducing the sheet resistance by changing the structure has a limitation because it causes deterioration of device characteristics. In addition, the phenomenon that the sheet resistance of the HFET structure increases due to the heat treatment for forming the ohmic contact in the transistor manufacturing process. These hinder the improvement of the high frequency characteristics, output characteristics, and power efficiency of the HFET.

  This invention is made | formed in view of this subject, The objective is to provide the semiconductor device using the epitaxial wafer for field effect transistors which can suppress characteristic degradation during device manufacture, and its manufacturing method. .

In order to solve the above problems, in the present invention, an Al _y Ga _z In _1-yz N surface protective layer (0 ≦ y ≦ 1, 0 ≦ z ≦) is further formed on a conventional HFET epitaxial wafer. The semiconductor device is manufactured using the HFFT epitaxial wafer on which 1) is deposited.

  That is, the semiconductor device and the manufacturing method thereof according to the present invention are constituted by the following specific technical means.

The first technical means includes a substrate made of a predetermined material and a GaN layer formed on the substrate, and an Al _x Ga _1-x N layer (0 <x <1) is formed on the GaN layer. An Al _y Ga _z In _1-yz N layer ( 0 <y <1, 0 ≦ z <1 ) on the Al _x Ga _1-x N layer, and the Al _y Ga _{The z} In _1-yz N layer is a semiconductor device using an epitaxial wafer for HFET lattice-matched with the GaN layer.

According to a second technical means, in the semiconductor device according to the first technical means, the Al _x Ga _1-x N layer includes an n-type Al _x Ga _1-x N layer therein. Features.

A third technical means is the semiconductor device according to the first or second technical manual stage, the material of the substrate, a sapphire, and wherein the silicon carbide is any one of silicon.

According to a fourth technical means, in the semiconductor device according to any one of the first to third technical means, an AlN layer is provided between the GaN layer and the Al _x Ga _1-x N layer. Features.

The fifth technical means is that a GaN layer, an Al _x Ga _1-x N layer (0 <x <1), and an Al _y Ga _z In ₁₋ lattice matched with the GaN layer are formed on a substrate of a predetermined material. a step of sequentially epitaxially growing a _yz N layer ( 0 <y <1, 0 ≦ z <1 ), and a protective film on a predetermined protective region on the Al _y Ga _z In _1-yz N layer After the deposition, a step of forming a source electrode and a drain electrode in regions other than the protective region on the Al _y Ga _z In _1-yz N layer, and after removing the protective film, the Al _y Forming a gate electrode in a predetermined region in the protection region on the Ga _z In _1-yz N layer, and manufacturing the semiconductor device.

According to a sixth technical means, a GaN layer, an Al _x Ga _1-x N layer (0 <x <1), and an Al _y Ga _z In ₁₋ lattice matched with the GaN layer are formed on a substrate of a predetermined material. a step of sequentially epitaxially growing a _yz N layer ( 0 <y <1, 0 ≦ z <1 ), and a protective film on a predetermined protective region on the Al _y Ga _z In _1-yz N layer after deposition, the _Al y _Ga z _in the region other than the protected area of the _1-y-z N layer, the _{Al y Ga z in 1-y} -z N layer, further, the _{Al x Ga 1-x} Removing a desired thickness of the N layer by etching, forming a source electrode and a drain electrode on the Al _x Ga _1-x N layer in a region other than the protective region, and the protective film after removal of the _Al y Ga Characterized by the In _{1-y-z N} preparation of a semiconductor device having a step of forming a gate electrode to a predetermined area of the protected area on the layer.

According to the semiconductor device and the manufacturing method thereof of the present invention, an Al _y Ga _z In _1-yz N surface protective layer (0 ≦ y ≦ 1, 0 ≦ z ≦) is further formed on the conventional epitaxial wafer for HFET. Since the HFFT epitaxial wafer having 1) deposited thereon is used, it is possible to manufacture a low-resistance HFET epitaxial wafer and to suppress an increase in sheet resistance due to heat treatment. More specifically, the following effects can be achieved.

The present invention uses an HFET epitaxial wafer having an Al _y Ga _z In _1-yz N surface protective layer (0 ≦ y ≦ 1, 0 ≦ z ≦ 1). Since separation is suppressed, an increase in sheet resistance due to heat treatment can be suppressed accordingly.

  Furthermore, even when a high AlN composition is used, it is possible to suppress degradation of device characteristics caused by a large lattice mismatch accompanying therewith.

In particular, the a-axis lattice constant of the Al _y Ga _z In _1-yz N surface protective layer has compositions y and z that are larger than the a-axis lattice constant of the Al _x Ga _1-x N barrier layer. If so, a low-resistance HFET epitaxial wafer can be produced more effectively, and an increase in sheet resistance due to heat treatment can be suppressed.

  Therefore, by manufacturing a semiconductor device such as a field effect transistor by using an epitaxial wafer for HFET like this, the sheet resistance can be reduced without incurring other device characteristics such as rising of source / drain electrodes and gate leakage. Reduction, gain increase, transistor current increase, and source / drain electrode contact resistance can be reduced, and the high frequency characteristics, output characteristics, and power efficiency of the device can be greatly improved.

  Hereinafter, an example of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings, taking a high-frequency switch circuit as an example.

FIG. 1 is a schematic view showing an example of an epitaxial wafer for HFET having an Al _y Ga _z In _1-yz N surface protective layer (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) used in the semiconductor device of the present invention. FIG.

In the epitaxial wafer 100 for HFET shown in FIG. 1, 1 is a substrate made of a predetermined material, 2 is a GaN layer, that is, a GaN buffer layer, 3 is a first Al _x Ga _1-x N (0 <x <1) layer, undoped _Al x _{Ga 1-x} n barrier layer, the 4 second _Al x _{Ga 1-x} n layer or Si-doped n-type _Al x _{Ga 1-x} n barrier layer, 5 a third _{Al x Ga 1-x} N layer, that is, undoped Al _x Ga _1-x N barrier layer, 6 is an Al _y Ga _z In _1-yz N (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) layer, that is, Al _y Ga _z In _{1-y -Z} Indicates an N surface protective layer. In the case of FIG. 1, values of x = 0.25, y = 0.82, and z = 0 are used as an example of the AlN composition.

  In some cases, the interface between the substrate 1 and the GaN buffer layer 2 may have a nucleation layer. However, the presence or absence of the nucleation layer may be any, and the effect of the present invention was not affected at all. Moreover, although the sapphire substrate, the silicon carbide (SiC) substrate, and the silicon (Si) substrate were respectively used as the material of the substrate 1, the difference between these substrates had no influence on the effect of the present invention.

Further, as Al _x Ga _1-x N barrier layers 3, 4, 5 (AlN composition x = 0.25 in the case of FIG. 1), as in Si-doped n-type Al _x Ga _1-x N barrier layer 4 Even when the HFET structure does not include an n-type doped layer, the effect of the present invention is not affected.

Further, instead of the Al _y In _1-y N surface protective layer in the case of the composition z = 0 as shown in FIG. 1, an Al _y Ga _z In _1-yz N surface protective layer further containing Ga (0 ≦ y Even when ≦ 1, 0 <z ≦ 1), the effect of the present invention was not affected at all. The Al _y Ga _z In _1-yz N surface protective layer 6 is lattice-matched with the GaN buffer layer 2.

The total thickness of the Al _x Ga _1-x N barrier layers 3, 4, 5 (in the case of FIG. 1, AlN composition x = 0.25) is 15 nm, and the Al _x Ga _1-x N barrier layer 3 , 4 and 5 did not affect the effects of the present invention. On the other hand, the film thickness of the Al _y Ga _z In _1-yz N surface protective layer 6 (in the case of FIG. 1, AlN composition y = 0.82, z = 0, that is, Al _0.82 In _0.18 N layer). Is 1 nm.

In the case of the epitaxial wafer 100 for an HFET having such a structure, the electron mobility is 1400 cm ² / Vs, the two-dimensional electron (2DEG) concentration is 8 × 10 ¹² cm ⁻² , and the sheet resistance is about 560 Ω / sq. Met.

FIG. 2 shows the heat treatment temperature dependence of the sheet resistance change in the HFET epitaxial wafer 100 shown in FIG. 1 used as an example in the semiconductor device of the present invention. The horizontal axis of FIG. 2 indicates the heat treatment temperature (° C.), the vertical axis indicates the sheet resistance (Ω / sq.), And the graph having the mark of ▲ indicates the change in sheet resistance in the epitaxial wafer 100 for HFET of FIG. As shown. For comparison, the conventional HFET epitaxial wafer, that is, the Al _0.82 In _0.18 N surface protective layer 6 alone is not provided, and the other structures are the same as those in the case of FIG. The temperature dependence of the epitaxial wafer is shown as a graph having a mark of ●.

Here, also in the case of the conventional epitaxial wafer structure for HFET, as the characteristics measured before the heat treatment, the electron mobility is 1400 cm ² / Vs, the two-dimensional electron gas concentration is 8 × 10 ¹² cm ⁻² , and the sheet The resistance is approximately 560 Ω / sq. 1 and the structure of the epitaxial wafer 100 for HFET shown in FIG. 1 used as an example in the semiconductor device of the present invention.

  Next, heat treatment was performed for 10 minutes at 600 ° C., 700 ° C., and 800 ° C. heat treatment temperatures as durations.

  In the case of the heat treatment, as shown by the mark marked with ● in FIG. 2, in the conventional epitaxial wafer structure for HFET, the sheet resistance rapidly increased as the heat treatment temperature increased. At 800 ° C., the sheet resistance is 890 Ω / sq. That is 1.6 times higher than before heat treatment.

On the other hand, in the case of the structure of the epitaxial wafer 100 for HFET of FIG. 1 used as an example in the semiconductor device of the present invention, the structure having the Al _0.82 In _0.18 N surface protective layer 6 has a surface nitrogen by heat treatment. 2 is suppressed, the sheet resistance slightly increases with an increase in the heat treatment temperature, as shown by the mark in FIG. 2, but the change in the sheet resistance is suppressed to a small level. Even at 800 ° C., the sheet resistance is 580Ω / sq. That is only a slight increase compared to before the heat treatment.

As described above, by adopting the epitaxial wafer structure for HFET having the Al _0.82 In _0.18 N surface protective layer 6 as shown in FIG. 1 used as an example in the semiconductor device of the present invention, the surface of the surface by heat treatment can be obtained. Since nitrogen desorption is suppressed, an increase in sheet resistance due to heat treatment can be suppressed to a small range.

Next, the increase rate of the sheet resistance in the heat treatment of the epitaxial wafer 100 for HFET of FIG. 1 used as an example in the semiconductor device of the present invention with respect to the AlN composition x of the Al _x Ga _1-x N barrier layers 3, 4, 5. This will be explained from the viewpoint of dependency. FIG. 3 shows the dependence of the AlN composition of the Al _x Ga _1-x N barrier layer on the rate of increase in sheet resistance in the heat treatment of the epitaxial wafer 100 for HFET shown in FIG. 1 used as an example in the semiconductor device of the present invention.

3 represents the AlN composition x of the Al _x Ga _1-x N barrier layers 3, 4, and 5, and the vertical axis represents the sheet resistance (Ω / sq.). The epitaxial wafer 100 for HFET of FIG. The change in sheet resistance at is shown as a graph with a mark. For comparison, the conventional HFET epitaxial wafer, that is, the Al _0.82 In _0.18 N surface protective layer 6 alone is not provided, and the other structures are the same as those in the case of FIG. The temperature dependence of the epitaxial wafer is shown as a graph having a mark of ●.

Note that the total film thickness of the Al _x Ga _1-x N barrier layers 3, 4, and 5 used in FIG. 3 is 15 nm in all the AlN compositions x. On the other hand, the film thickness of the Al _0.82 In _0.18 N surface protective layer 6 is 1 nm.

In the conventional HFET epitaxial wafer structure, as shown by the mark in FIG. 3, when the AlN composition x is 0.0 to 0.3, the sheet resistance decreases as the AlN composition x increases. Go. This is because the induced 2DEG concentration increases as the polarization effect increases. However, when the AlN composition x exceeds 0.3, the sheet resistance increases rapidly as the AlN composition x increases. This _is due to the increase of the lattice mismatch between Al x _{Ga 1-x} N barrier layer 3, 4, 5 and the GaN buffer layer _2, Al x _{Ga 1-x} N barrier layer 3, 4 and 5 to relax the lattice This is because the crystallinity of the Al _x Ga _1-x N barrier layers 3, 4, 5 is deteriorated and the 2DEG concentration and the electron mobility are lowered.

On the other hand, in the structure of the epitaxial wafer 100 for HFET of FIG. 1 used as an example in the semiconductor device of the present invention, the AlN composition x is 0.0 to 0.3, as in the case of the conventional structure. As the sheet resistance increases, the sheet resistance decreases. However, even if the sheet resistance exceeds 0.3, unlike the conventional structure, the sheet resistance continues to decrease until the AlN composition x becomes 0.4. . That is, the AlN composition x at which the sheet resistance starts to increase is from 0.4, which is a higher composition than the conventional structure. This is probably because the Al _0.82 In _0.18 N surface protective layer 6 lattice-matched with the GaN buffer layer 2 is the uppermost layer, so that the critical composition for lattice relaxation is increased compared to the conventional structure.

As described above, by adopting the epitaxial wafer structure for HFET having the Al _0.82 In _0.18 N surface protective layer 6 as shown in FIG. 1 used as an example in the semiconductor device of the present invention, the AlN composition x It was found to have the effect that the characteristic degradation due to lattice relaxation of _Al x _{Ga 1-x} N barrier layer 3, 4 and 5 with the increase (0 <x <1) can be suppressed.

Next, the rate of increase in sheet resistance in the heat treatment of the epitaxial wafer 100 for HFET of FIG. 1 used as an example in the semiconductor device of the present invention is expressed as Al ₀ .5 of Al _y Ga _z In _1-yz N surface protective layer 6 _{. This} will be described from the viewpoint of dependence on lattice mismatch with the ₂₅ Ga _0.75 N barrier layers 3, 4, and 5. In this embodiment, the heat treatment is performed at a temperature of 800 ° C. for 10 minutes. Figure 4, Al ₀ the _{Al y Ga z In 1-y} -z N surface protective layer 6 about the rate of increase in the sheet resistance in the heat treatment of the HFET epitaxial wafer 100 illustrated in FIG. 1 used as an example in a semiconductor device of the present invention Dependence of lattice mismatch with _.25 Ga _0.75 N barrier layers 3, 4 and 5. The horizontal axis of FIG. 4 represents the Al _y Ga _z In _1-yz N surface protective layer 6 (however, as shown in FIG. 1, the composition z = 0 of the Al _y In _1-y N surface protective layer containing no Ga). The ratio of the lattice mismatch (%) with the Al _0.25 Ga _0.75 N barrier layers 3, 4, and 5, and the vertical axis indicates the increase in sheet resistance (Ω / sq.). Shows the rate.

The Al _y Ga _z In _1-yz N surface protective layer 6 and the Al _0.25 Ga _0.75 N barrier layers 3, 4, 5 are lattice-mismatched, and the Al _y Ga _z In _1-y N When the a-axis lattice constant of the surface protective layer is larger than that of the Al _0.25 Ga _0.75 N barrier layer, that is, the atomic bonding force of the Al _y Ga _z In _1-y N surface protective layer is Al When larger than that of the _0.25 Ga _0.75 N barrier layer, desorption of nitrogen on the surface of the Al _y Ga _z In _1-yz N surface protective layer is suppressed, and the sheet resistance increase rate is approximately There was only a slight increase to 1.04.

On the other hand, when the a-axis lattice constant of the Al _y Ga _z In _1-y N surface protective layer is smaller than that of the Al _0.25 Ga _0.75 N barrier layer, the lattice mismatch increases, It was found that the rate of increase in resistance to sea bream increased considerably. However, the rate of increase was about 1.35 even at a lattice mismatch of 0.6%, which was suppressed compared to the rate of increase of 1.53 for conventional portable structures that do not have a surface protective layer.

  Similar results are obtained for AlGaN barrier layers having other AlN compositions.

As described above, in the epitaxial wafer 100 for HFET having the Al _y Ga _z In _1-yz N surface protective layer 6 (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) in the present invention, the surface protective layer It was found that when the a-axis lattice constant is larger than the a-axis lattice constant of the Al _x Ga _1-x N barrier layers 3, 4, 5, the increase in sheet resistance due to heat treatment can be further suppressed.

That is, as shown in FIG. 4, in a certain region of Al _y Ga _z In _1-yz N (0 ≦ y ≦ 1, 0 ≦ z ≦ 1), the lattice constant of the a axis is large, and the atoms The bonding force is stronger than that of Al _x Ga _1-x N and GaN, and the lattice mismatch can be made smaller than that of the Al _x Ga _1-x N layer used for the barrier layer of the HFET structure. Therefore, the desorption of nitrogen due to the heat treatment on the outermost surface is suppressed as compared with the surface of the Al _x Ga _1-x N layer or the GaN layer as in the conventional HFET structure, and the GaN buffer layer having the HFET structure and the AlGaN It was found that the degradation of device characteristics caused by lattice mismatch with the barrier layer can be suppressed.

Next, an example different from FIG. 1 of the HFET epitaxial wafer structure used in the semiconductor device of the present invention will be described with reference to FIG. FIG. 5 shows an HFET epitaxial wafer structure having an AlN layer, that is, an AlN intermediate layer between a GaN buffer layer and an AlGaN barrier layer as an example different from FIG. 1 of the HFET epitaxial wafer structure used in the semiconductor device of the present invention. is there. As shown in FIG. 5, in the HFET epitaxial wafer structure of this example, an AlN intermediate layer 7 is formed between the GaN buffer layer 2 and the undoped Al _0.25 Ga _0.75 N barrier layer 3. .

In the case of the HFET epitaxial wafer 200 structured as shown in FIG. 5, the electron mobility is 1800 cm ² / Vs, the two-dimensional electron (2DEG) concentration is 8 × 10 ¹² cm ⁻² , and the sheet resistance is approximately 434 Ω / sq. Met.

Also in the case of the HFET epitaxial wafer 200 having the AlN intermediate layer 7, the heat resistance dependency of the sheet resistance change, the AlN composition dependency of the AlGaN barrier layer, the Al _y Ga _z In _1-yz N surface protective layer The lattice mismatch dependence with the Al _x Ga _1-x N barrier layer showed the same tendency as in the case without the AlN intermediate layer 7 described with reference to FIG.

Next, a method for manufacturing a semiconductor device of the present invention will be described by taking as an example the case of manufacturing a heterostructure field effect transistor HFET. First, an HFET epitaxial wafer 100 having an Al _y Ga _z In _1-yz N surface protective layer as shown in FIG. 1 is fabricated, and further, a heterostructure field effect transistor HFET using the HFET epitaxial wafer 100 is fabricated. A first embodiment relating to the manufacturing method to be manufactured will be described with reference to the process diagrams of FIGS. 6, 7, and 8.

6, FIG. 7, and FIG. 8 respectively show the first fabrication process and the second fabrication of the HFET using the epitaxial wafer for HFET having the Al _y Ga _z In _1-yz N surface protective layer according to the present invention. FIG. 8 shows a schematic diagram as an example of the HFET structure manufactured in the process and the third manufacturing process, respectively. Through the manufacturing process from FIG. 6 to the manufacturing process in FIG. The procedure for completing the fabrication is shown. Hereinafter, an example of the HFET manufacturing process of the present invention will be described in order from FIG. 6 to FIG.

In the first manufacturing process shown in FIG. 6, a GaN buffer layer 2, an undoped Al _x Ga _1-x N barrier layer 3 (0 <x <1), a Si-doped n-type Al _x Ga _1-x are formed on the substrate 1. An N barrier layer 4, an undoped Al _x Ga _1-x N barrier layer 5, and an Al _y Ga _z In _1-yz N surface protective layer 6 (0 ≦ y ≦ 1, 0 ≦ z ≦ 1) are epitaxially grown in sequence. After forming the epitaxial wafer 100 for HFET, a protective film 8 is deposited on a predetermined protective region on the Al _y Ga _z In _1-yz N surface protective layer 6 to obtain an intermediate HFET 101 which is an intermediate product of HFET. Is made.

Next, in the second manufacturing step shown in FIG. 7, Al _y Ga _z In in the remaining region other than the protective region that is not protected by the protective film 8 in the intermediate HFET 101 manufactured in the first manufacturing step in FIG. 6. A source electrode 9 and a drain electrode 10 that are in ohmic contact are deposited on the _1-yz N surface protective layer 6 to fabricate an intermediate HFET 102.

In the final third manufacturing step shown in FIG. 8, after the protective film 8 is removed from the intermediate HFET 102 manufactured in the second manufacturing step of FIG. 7, the Al _y Ga _z In _1-yz N surface protective layer 6 is removed. A Schottky gate electrode 11 is deposited in a region where the upper protective film 8 has been removed, that is, a predetermined gate electrode region in the protective region, and a final heterostructure field effect transistor HFET 103 is manufactured.

The heterostructure field effect transistor 103 using the HFET epitaxial wafer 100 having the Al _y Ga _z In _1-yz N surface protective layer 6 shown in FIG. 1 is manufactured by the manufacturing method of the first embodiment as described above. can do.

Next, a heterostructure field effect transistor HFET having a heterostructure different from the heterostructure field effect transistor HFET103 shown in FIG. 8 using an epitaxial wafer for HFET having an Al _y Ga _z In _1-yz N surface protective layer is obtained. A second embodiment relating to the manufacturing method to be manufactured will be described with reference to the process diagrams of FIGS. 6, 9, 10 and 11.

FIG. 6 shows a manufacturing process similar to the first manufacturing process described above. 9, FIG. 10 and FIG. 11 show manufacturing steps sequentially following the first manufacturing step of FIG. 6, each of which is an HFET having an Al _y Ga _z In _1-yz N surface protective layer according to the present invention. FIG. 9 and FIG. 10 are schematic views showing an example of the HFET structure produced in the 2A fabrication process, the 3A fabrication process, and the 4A fabrication process of the HFET using the epitaxial wafer, respectively. 11 shows a procedure for finally completing the fabrication of the HFET having a heterostructure different from that in FIG. 8 in FIG. 11 through the fabrication steps up to FIG. Hereinafter, the second embodiment of the HFET manufacturing process of the present invention will be described in order from FIG. 6 to FIG. 9, FIG. 10, and FIG.

In the first manufacturing process shown in FIG. 6, as described above, the GaN buffer layer 2, the undoped Al _x Ga _1-x N barrier layer 3 (0 <x <1), the Si-doped n-type Al layer are formed on the substrate 1. _x Ga _1-x N barrier layer 4, an undoped _Al x _{Ga 1-x} N barrier layer _{5, Al y Ga z In 1} -y-z N surface protective layer 6 (0 ≦ y ≦ 1,0 ≦ z ≦ 1) After epitaxially growing the epitaxial wafer 100 for HFET, a protective film 8 is deposited on a predetermined protective region on the Al _y Ga _z In _1-yz N surface protective layer 6 to produce an intermediate HFET. An intermediate HFET 101 is manufactured.

Next, in the manufacturing process of 2A shown in FIG. 9, the Al _y Ga _z In _1-yz N surface of the remaining region other than the protective region that is not protected by the protective film 8 in the intermediate HFET 101 of FIG. 6. The protective layer 6 and further the Al _x Ga _1-x N barrier layers 3, 4, and 5 are removed by etching to an arbitrary thickness to produce the intermediate HFET 102 A. In the present embodiment, an example is shown in which the undoped Al _x Ga _1-x N barrier layer 5 is completely removed to expose the Si-doped n-type Al _x Ga _1-x N barrier layer 4.

Next, in the manufacturing process 3A shown in FIG. 10, in the intermediate HFET 102A manufactured in the manufacturing process 2A of FIG. 9, the Al _y Ga _z In _1-yz N surface protective layer 6 and the undoped Al _x Ga _{1- On} the Si-doped n-type Al _x Ga _1-x N barrier layer 4 in the region where the _xN barrier layer 5 has been removed by etching, that is, in the remaining region other than the protection region, an ohmic contact source electrode 9 and drain electrode 10 are respectively provided. Deposit the intermediate HFET 103A.

In the last manufacturing process of 4A shown in FIG. 11, after removing protective film 8 from intermediate HFET 103A manufactured in the manufacturing process of 3A of FIG. 10, Al _y Ga _z In ₁₋ in the region where protective film 8 is removed. _A schottky gate electrode 11 is deposited in a region where the protective film 8 on the _yz N surface protective layer 6 is removed, that is, a predetermined gate electrode region in the protective region, and a final heterostructure field effect transistor HFET 104A is formed. Make it.

A heterostructure different from that shown in FIG. 8 by using the HFET epitaxial wafer 100 having the Al _y Ga _z In _1-yz N surface protective layer 6 shown in FIG. 1 by the manufacturing method of the second embodiment as described above. A heterostructure field effect transistor 104A can be manufactured.

It is a schematic view showing an example of a HFET epitaxial wafer having an _{Al y Ga z In 1-y} -z N surface protective layer used in the semiconductor device of the present invention. It is a graph which shows the heat processing temperature dependence of the change of the sheet resistance in the epitaxial wafer for HFET shown in FIG. 1 used as an example for the semiconductor device of this invention. The semiconductor device of the present invention is a graph showing the dependence of the AlN composition of Al x _Ga 1-x _N barrier layer about the rate of increase in the sheet resistance in the heat treatment of the epitaxial wafer for the HFET shown in Figure 1 used as an example. The Al _0.25 Ga _0.75 of the Al _y Ga _z In _1-yz N surface protective layer related to the rate of increase in sheet resistance in the heat treatment of the epitaxial wafer for HFET shown in FIG. 1 used as an example in the semiconductor device of the present invention. It is a graph which shows the dependence of the lattice mismatch with an N barrier layer. As an example different from FIG. 1 of the HFET epitaxial wafer structure used in the semiconductor device of the present invention, there is an HFET epitaxial wafer structure having an AlN intermediate layer between a GaN buffer layer and an AlGaN barrier layer. It is a schematic diagram showing an example of _{Al y Ga z In 1-y} -z N HFET structure manufactured by the first manufacturing process of the HFET using epitaxial wafer for HFET having a surface protective layer according to the present invention. It is a schematic diagram showing an example of _{Al y Ga z In 1-y} -z N HFET structure made with a second fabrication step of the HFET using epitaxial wafer for HFET having a surface protective layer according to the present invention. It is a schematic diagram showing an example of _{Al y Ga z In 1-y} -z N a 3 HFET structure fabricated by the manufacturing process of the HFET using epitaxial wafer for HFET having a surface protective layer according to the present invention. It is a schematic diagram showing an example of the HFET structure manufactured in the 2A manufacturing process of the HFET using the epitaxial wafer for HFET having the Al _y Ga _z In _1-yz N surface protective layer according to the present invention. It is a schematic diagram showing an example of _{Al y Ga z In 1-y} -z N surface HFET structure fabricated by the manufacturing process of the 3A of the HFET using epitaxial wafer for HFET having a protective layer according to the present invention. It is a schematic diagram showing an example of _{Al y Ga z In 1-y} -z N surface HFET structure fabricated by the manufacturing process of the 4A of the HFET using epitaxial wafer for HFET having a protective layer according to the present invention.

Explanation of symbols

1 ... substrate, 2 ... GaN buffer layer, 3 ... undoped _Al x _{Ga 1-x} N barrier layer (undoped _Al 0.25 _{Ga 0.75} N barrier layer), 4 ... Si-doped n-type _Al x _{Ga 1-x} N Barrier layer (Si-doped n-type Al _0.25 Ga _0.75 N barrier layer), 5... Undoped Al _x Ga _1-x N barrier layer (undoped Al _0.25 Ga _0.75 N barrier layer), 6. _{y Ga z in 1-y-} z N surface protective layer _{(Al 0.82 in 0.18} N surface protective layer), 7 ... AlN in question layer, 8 ... protective film, 9 ... source electrode, 10 ... drain electrode, DESCRIPTION OF SYMBOLS 11 ... Gate electrode, 100 ... Epitaxial wafer for HFET, 101, 102, 102A, 103A ... Intermediate HFET, 103, 104A ... Heterostructure field effect transistor HFET, 200 ... HFET epitaxial Wafer.

Claims (6)

A substrate of a predetermined material; and a GaN layer formed on the substrate; an Al _x Ga _1-x N layer (0 <x <1) on the GaN layer; and the Al the _x Ga _1-x N _layer, Al _y Ga _{z in} a _1-y-z N layer (0 <y <1,0 ≦ z <1), the _{Al y Ga z in 1-y} -z A semiconductor device characterized in that an NFET epitaxial wafer for lattice matching with the GaN layer is used for the N layer. The semiconductor device according to claim 1, wherein the Al _x Ga _1-x N layer includes an n-type Al _x Ga _1-x N layer inside. Material of the substrate, a sapphire, a semiconductor device according to claim 1 or 2, wherein the silicon carbide is any one of silicon. Wherein between the GaN layer and the _Al x _{Ga 1-x} N layer, a semiconductor device according to any one of 3 claims 1 and having an AlN layer. On a substrate of a predetermined material, a GaN layer, an Al _x Ga _1-x N layer (0 <x <1), and an Al _y Ga _z In _1-yz N layer ( 0 <Y <1, 0 ≦ z <1 ) are sequentially epitaxially grown, and after depositing a protective film in a predetermined protective region on the Al _y Ga _z In _1-yz N layer, the Al _y A step of forming a source electrode and a drain electrode in a region other than the protective region on the Ga _z In _1-yz N layer, and after removing the protective film, the Al _y Ga _z In _1-y- preparation of a semiconductor device characterized by having a step of forming a gate electrode to a predetermined area of the protected area on the _{z N} layer. On a substrate of a predetermined material, a GaN layer, an Al _x Ga _1-x N layer (0 <x <1), and an Al _y Ga _z In _1-yz N layer ( 0 <Y <1, 0 ≦ z <1 ) are sequentially epitaxially grown, and after depositing a protective film on a predetermined protective region on the Al _y Ga _z In _1-yz N layer, the Al _y for _{Ga z in 1-y-z} N region other than the protected area on layer, the _{Al y Ga z in 1-y} -z N layer, further, to any thickness of the _Al x _{Ga 1-x} N layer Are removed by etching, a step of forming a source electrode and a drain electrode on the Al _x Ga _1-x N layer in a region other than the protective region, and after removing the protective film, the Al _{y Ga z In 1-y-} z Preparation of a semiconductor device and a step of forming a gate electrode to a predetermined area of the protected area on the layer, the.

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