JP5642935B2 - インピーダンス調整回路及びこれを備える半導体装置 - Google Patents

インピーダンス調整回路及びこれを備える半導体装置 Download PDF

Info

Publication number
JP5642935B2
JP5642935B2 JP2009036771A JP2009036771A JP5642935B2 JP 5642935 B2 JP5642935 B2 JP 5642935B2 JP 2009036771 A JP2009036771 A JP 2009036771A JP 2009036771 A JP2009036771 A JP 2009036771A JP 5642935 B2 JP5642935 B2 JP 5642935B2
Authority
JP
Japan
Prior art keywords
impedance
circuit
determination
replica
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2009036771A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010193291A (ja
JP2010193291A5 (enExample
Inventor
俊二 桑原
俊二 桑原
藤澤　宏樹
宏樹 藤澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PS4 Luxco SARL
Original Assignee
PS4 Luxco SARL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PS4 Luxco SARL filed Critical PS4 Luxco SARL
Priority to JP2009036771A priority Critical patent/JP5642935B2/ja
Priority to US12/707,354 priority patent/US8278973B2/en
Publication of JP2010193291A publication Critical patent/JP2010193291A/ja
Publication of JP2010193291A5 publication Critical patent/JP2010193291A5/ja
Application granted granted Critical
Publication of JP5642935B2 publication Critical patent/JP5642935B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017581—Coupling arrangements; Interface arrangements programmable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Networks Using Active Elements (AREA)
  • Dram (AREA)
JP2009036771A 2009-02-19 2009-02-19 インピーダンス調整回路及びこれを備える半導体装置 Expired - Fee Related JP5642935B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009036771A JP5642935B2 (ja) 2009-02-19 2009-02-19 インピーダンス調整回路及びこれを備える半導体装置
US12/707,354 US8278973B2 (en) 2009-02-19 2010-02-17 Impedance control circuit and semiconductor device including the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009036771A JP5642935B2 (ja) 2009-02-19 2009-02-19 インピーダンス調整回路及びこれを備える半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014220946A Division JP2015043620A (ja) 2014-10-30 2014-10-30 半導体装置においてオンダイターミネーションを提供するための方法

Publications (3)

Publication Number Publication Date
JP2010193291A JP2010193291A (ja) 2010-09-02
JP2010193291A5 JP2010193291A5 (enExample) 2012-01-26
JP5642935B2 true JP5642935B2 (ja) 2014-12-17

Family

ID=42559345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009036771A Expired - Fee Related JP5642935B2 (ja) 2009-02-19 2009-02-19 インピーダンス調整回路及びこれを備える半導体装置

Country Status (2)

Country Link
US (1) US8278973B2 (enExample)
JP (1) JP5642935B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100921832B1 (ko) * 2008-03-03 2009-10-16 주식회사 하이닉스반도체 반도체 메모리장치의 온 다이 터미네이션 제어회로
KR101166643B1 (ko) * 2010-09-07 2012-07-23 에스케이하이닉스 주식회사 데이터 출력 회로
KR101086884B1 (ko) 2010-09-30 2011-11-25 주식회사 하이닉스반도체 임피던스 제어신호 발생 회로 및 반도체 회로의 임피던스 제어 방법
JP2013081079A (ja) * 2011-10-04 2013-05-02 Elpida Memory Inc 半導体装置
KR101950319B1 (ko) * 2012-06-27 2019-02-20 에스케이하이닉스 주식회사 온 다이 터미네이션 회로
KR20140120101A (ko) * 2013-04-02 2014-10-13 에스케이하이닉스 주식회사 데이터송신회로
KR102083005B1 (ko) 2013-10-31 2020-02-28 삼성전자주식회사 종단 저항을 보정하는 반도체 메모리 장치 및 그것의 종단 저항 보정 방법
JP2015154316A (ja) 2014-02-17 2015-08-24 マイクロン テクノロジー， インク． 半導体装置
US10554450B2 (en) * 2018-03-14 2020-02-04 Samsung Display Co., Ltd. High resolution voltage-mode driver
KR20240016238A (ko) 2022-07-27 2024-02-06 창신 메모리 테크놀로지즈 아이엔씨 임피던스 교정 회로
US12431872B2 (en) * 2023-06-16 2025-09-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor circuit and method for operating the same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5606275A (en) * 1995-09-05 1997-02-25 Motorola, Inc. Buffer circuit having variable output impedance
JP2001217705A (ja) * 2000-01-31 2001-08-10 Fujitsu Ltd Ｌｓｉデバイス
US6356105B1 (en) * 2000-06-28 2002-03-12 Intel Corporation Impedance control system for a center tapped termination bus
KR100391148B1 (ko) * 2000-11-02 2003-07-16 삼성전자주식회사 프로그래머블 임피던스 제어회로 및 방법
US6509778B2 (en) * 2001-03-15 2003-01-21 International Business Machines Corporation BIST circuit for variable impedance system
US6690211B1 (en) * 2002-11-28 2004-02-10 Jmicron Technology Corp. Impedance matching circuit
JP4428504B2 (ja) * 2003-04-23 2010-03-10 株式会社ルネサステクノロジ 半導体集積回路装置
JP3885773B2 (ja) * 2003-06-30 2007-02-28 日本電気株式会社 インピーダンス調整回路及び調整方法、インピーダンス調整回路を備える半導体装置
KR100610007B1 (ko) * 2004-06-14 2006-08-08 삼성전자주식회사 임피던스 랜지 시프팅 기능을 갖는 반도체 장치의프로그래머블 임피던스 콘트롤 회로 및 그에 따른임피던스 랜지 시프팅 방법
KR100558559B1 (ko) * 2004-07-07 2006-03-10 삼성전자주식회사 프로그래머블 임피던스 컨트롤 장치 및 그의 동작 방법
US7221193B1 (en) * 2005-01-20 2007-05-22 Altera Corporation On-chip termination with calibrated driver strength
JP2006270331A (ja) * 2005-03-23 2006-10-05 Nec Corp インピーダンス調整回路及び集積回路装置
KR100655083B1 (ko) * 2005-05-11 2006-12-08 삼성전자주식회사 반도체 장치에서의 임피던스 콘트롤 회로 및 임피던스콘트롤 방법
KR100588601B1 (ko) * 2005-06-09 2006-06-14 삼성전자주식회사 임피던스 제어 회로
JP4916699B2 (ja) * 2005-10-25 2012-04-18 エルピーダメモリ株式会社 Ｚｑキャリブレーション回路及びこれを備えた半導体装置
JP4205741B2 (ja) 2006-08-21 2009-01-07 エルピーダメモリ株式会社 キャリブレーション回路を有する半導体装置及びキャリブレーション方法
JP4920512B2 (ja) * 2007-07-04 2012-04-18 エルピーダメモリ株式会社 キャリブレーション回路及びこれを備える半導体装置、並びに、データ処理システム
US7973553B1 (en) * 2010-03-11 2011-07-05 Altera Corporation Techniques for on-chip termination

Also Published As

Publication number Publication date
US20100207680A1 (en) 2010-08-19
US8278973B2 (en) 2012-10-02
JP2010193291A (ja) 2010-09-02

Similar Documents

Publication Publication Date Title
JP5642935B2 (ja) インピーダンス調整回路及びこれを備える半導体装置
KR100744039B1 (ko) 데이터 출력드라이버의 임피던스를 조정할 수 있는 반도체메모리 장치
KR100879747B1 (ko) 데이터 입출력드라이버의 임피던스를 조정할 수 있는반도체 장치
US8878565B2 (en) Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same
JP4159553B2 (ja) 半導体装置の出力回路及びこれを備える半導体装置、並びに、出力回路の特性調整方法
JP4916699B2 (ja) Ｚｑキャリブレーション回路及びこれを備えた半導体装置
US9077332B2 (en) Impedance control circuit and semiconductor device including the same
US7869973B2 (en) Calibration circuit
US9294072B2 (en) Semiconductor device and method for adjusting impedance of output circuit
US20100177588A1 (en) Calibration circuit and calibration method
JP6084764B2 (ja) 半導体装置
JP2013081079A (ja) 半導体装置
JP4117977B2 (ja) 半導体装置
US7994835B2 (en) Duty control circuit and semiconductor device having the same
CN113646841A (zh) 具有非目标odt功能的输出缓冲电路
KR100772533B1 (ko) 온 다이 터미네이션 회로 및 그의 구동 방법
JP4282713B2 (ja) キャリブレーション回路を有する半導体装置及びキャリブレーション方法
JP7251624B2 (ja) 半導体集積回路
JP2013074564A (ja) 半導体装置及びその制御方法
JP2015043620A (ja) 半導体装置においてオンダイターミネーションを提供するための方法
JP2011135436A (ja) 半導体装置
JP4618602B2 (ja) 半導体装置
JP2014127894A (ja) 半導体装置
CN114189231A (zh) 不稳定性降低的延迟电路
JP2013074561A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111207

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111207

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20130730

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130822

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131206

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140121

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140401

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140404

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140708

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141007

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141030

R150 Certificate of patent or registration of utility model

Ref document number: 5642935

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees