JP5637212B2 - 基板処理方法、パターン形成方法、半導体素子の製造方法、および半導体素子 - Google Patents
基板処理方法、パターン形成方法、半導体素子の製造方法、および半導体素子 Download PDFInfo
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Description
Claims (6)
- 被処理基板の処理を行う基板処理方法であって、
被処理基板上に、ハードマスク層を形成するハードマスク層形成工程と、
前記ハードマスク層形成工程の後に、形成したハードマスク層の上に、所定の形状にパターニングされたフロロカーボン(CFx:xは任意の数)層を形成するフロロカーボン層形成工程と、
前記フロロカーボン層形成工程の後に、形成された前記フロロカーボン層および前記フロロカーボン層の間に露出する前記ハードマスク層を覆うように、シリコンを含有する膜を形成するシリコン含有膜形成工程と、
前記シリコン含有膜形成工程の後に、前記フロロカーボン層の側壁側に位置するシリコン含有膜を残し、前記フロロカーボン層の上側および前記ハードマスク層の上側に位置するシリコン含有膜を除去するようにエッチングを行うシリコン含有膜エッチング工程と、
前記シリコン含有膜エッチング工程の後に、前記側壁間に位置する前記フロロカーボン層を除去するようにエッチングを行うフロロカーボン層エッチング工程と、
前記フロロカーボン層エッチング工程の後に、残った前記シリコン含有膜をマスクとしてハードマスク層のエッチングを行うハードマスク層エッチング工程と、
前記ハードマスク層エッチング工程の後に、残ったハードマスク層をマスクとして、前記被処理基板のエッチングを行う被処理基板エッチング工程とを含む、基板処理方法。 - 前記シリコン含有膜は、SiO2膜を含む、請求項1に記載の基板処理方法。
- 前記ハードマスク層は、SiN膜を含む、請求項1に記載の基板処理方法。
- 被処理基板のエッチングを行う際のパターンを形成するパターン形成方法であって、
被処理基板上に、ハードマスク層を形成するハードマスク層形成工程と、
前記ハードマスク層形成工程の後に、形成したハードマスク層の上に、所定の形状にパターニングされたフロロカーボン(CFx:xは任意の数)層を形成するフロロカーボン層形成工程と、
前記フロロカーボン層形成工程の後に、形成された前記フロロカーボン層および前記フロロカーボン層の間に露出する前記ハードマスク層を覆うように、シリコンを含有する膜を形成するシリコン含有膜形成工程と、
前記シリコン含有膜形成工程の後に、前記フロロカーボン層の側壁側に位置するシリコン含有膜を残し、前記フロロカーボン層の上側および前記ハードマスク層の上側に位置するシリコン含有膜を除去するようにエッチングを行うシリコン含有膜エッチング工程と、
前記シリコン含有膜エッチング工程の後に、前記側壁間に位置する前記フロロカーボン層を除去するようにエッチングを行い、被処理基板のエッチングを行う際のフロロカーボン層のパターンを形成するパターン形成工程とを含む、パターン形成方法。 - 被処理基板にエッチングを行って製造される半導体素子の製造方法であって、
被処理基板上に、ハードマスク層を形成するハードマスク層形成工程と、
前記ハードマスク層形成工程の後に、形成したハードマスク層の上に、所定の形状にパターニングされたフロロカーボン(CFx:xは任意の数)層を形成するフロロカーボン層形成工程と、
前記フロロカーボン層形成工程の後に、形成された前記フロロカーボン層および前記フロロカーボン層の間に露出する前記ハードマスク層を覆うように、シリコンを含有する膜を形成するシリコン含有膜形成工程と、
前記シリコン含有膜形成工程の後に、前記フロロカーボン層の側壁側に位置するシリコン含有膜を残し、前記フロロカーボン層の上側および前記ハードマスク層の上側に位置するシリコン含有膜を除去するようにエッチングを行うシリコン含有膜エッチング工程と、
前記シリコン含有膜エッチング工程の後に、前記側壁間に位置する前記フロロカーボン層を除去するようにエッチングを行うフロロカーボン層エッチング工程と、
前記フロロカーボン層エッチング工程の後に、残った前記シリコン含有膜をマスクとしてハードマスク層のエッチングを行うハードマスク層エッチング工程と、
前記ハードマスク層エッチング工程の後に、残ったハードマスク層をマスクとして、前記被処理基板のエッチングを行う被処理基板エッチング工程とを含む、半導体素子の製造方法。 - 被処理基板上に、ハードマスク層を形成し、形成したハードマスク層の上に、所定の形状にパターニングされたフロロカーボン(CFx:xは任意の数)層を形成し、形成された前記フロロカーボン層および前記フロロカーボン層の間に露出する前記ハードマスク層を覆うように、シリコンを含有する膜を形成し、前記フロロカーボン層の側壁側に位置するシリコン含有膜を残し、前記フロロカーボン層の上側および前記ハードマスク層の上側に位置するシリコン含有膜を除去するようにエッチングを行い、前記側壁間に位置する前記フロロカーボン層を除去するようにエッチングを行い、残った前記シリコン含有膜をマスクとしてハードマスク層のエッチングを行い、残ったハードマスク層をマスクとして、前記被処理基板のエッチングを行って製造される、半導体素子。
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Also Published As
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US9117764B2 (en) | 2015-08-25 |
US20130157468A1 (en) | 2013-06-20 |
CN103081074A (zh) | 2013-05-01 |
KR20130064104A (ko) | 2013-06-17 |
US20150325448A1 (en) | 2015-11-12 |
CN103081074B (zh) | 2015-08-26 |
KR101425760B1 (ko) | 2014-08-01 |
WO2012026286A1 (ja) | 2012-03-01 |
JPWO2012026286A1 (ja) | 2013-10-28 |
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