JP5591356B2 - Capacitance adjustment to increase stack voltage tolerance - Google Patents

Description

  The present disclosure relates to electronic integrated circuits (ICs), and more specifically to circuits having stacked transistor devices that switch high frequency signals.

Most radios, cell phones, television receivers, and related devices today require “RF switches” to control connections between various transmitter and receiver circuits (“RF”). Is used generically herein to mean any moderately high frequency AC signal.) FIG. 1 is a simplified diagram of a typical simple double throw switch used, for example, to switch a single antenna 102 between a transmit signal source 104 and a receive circuit 106. Switches S ₁ 108, S ₂ 110, S ₃ 112 and S ₄ 114 are represented by the symbols of mechanical single pole single throw switches. In general, the switch, as S ₂ is open or high impedance when S ₁ is turned in the closing to or low impedance, are controlled. Since the switch is not perfect, the node of the transmit / receive switch farthest away from the antenna (eg, S ₁ 108 or S ₂ 110) will usually be subject to signal leakage effects through the switch when the switch is open. Shorted to circuit common to reduce. In this way, S ₂ 110 is represented in an open state, and the corresponding shorting switch S ₄ 114 is closed to terminate the received S _RF signal at node 106 to ground 116. Conversely, short circuit switch S ₃ 112 is open because its corresponding signal switch S ₁ 108 is closed to conduct the transmit S _RF signal at node 104 to antenna 102. In order to couple the antenna 102 to the receiving circuit, the state of all four switches can generally be reversed from the state shown in FIG.

  In modern circuits, the RF switch as represented in FIG. 1 is most often implemented using semiconductor devices, usually some form of field effect transistor (FET). Semiconductor RF switches are generally manufactured using insulated gate FETs, often referred to as MOSFETs, despite the fact that many do not use the original metal oxide semiconductor (MOS) structure. Non-insulated gate FETs (eg, junction FETs (JFETs)) are also commonly used, particularly with certain semiconductor materials (eg, GaAs). Each switch may be implemented using a single FET or multiple FETs stacked in series as described herein.

The impedance of an on (conducting) switch is generally low enough to ignore the voltage appearing across the switch in this state. However, switches that are off (non-conducting or high impedance) typically must support the full voltage of the RF signal they control. Thus, the RF power that can be controlled by a semiconductor RF switch depends on its voltage capability, i.e. on the drain-source breakdown voltage (BVds) of its constituent transistors. In FIG. 1, both S ₂ 110 and S ₃ 112 must withstand the transmitted signal voltage S _RF to ground.

  Integrated circuit manufacturing requires many compromises. Specifically, many IC transistors have a small BVds and are very effective at switching RF signals, but may not be suitable for large amplitude control signals. One solution is to use an alternative transistor design that yields a higher BVds. However, the trade-offs necessary to manufacture transistors with higher BVds in integrated circuits can be cumbersome. For example, such a design may not be compatible with other circuits desired for integrated circuits. Alternatively, it can be uneconomical.

Thus, many semiconductor RF switches today stack a large number of low BVds transistors in series to improve overall switch breakdown performance. FIG. 2 shows an example of such a stacked transistor semiconductor switch. The switch is disposed between the first node N ₁ 202 and the second node N ₂ 204 and is controlled by the voltage V _Control 206. Many (j) FETs are stacked in series connection from the drain to the adjacent source to form the entire switch. In this way, the first transistor M 1 has a source coupled to N ₁ 202 and a drain coupled in series to the source of the second FET M ₂ 210. The further FET represented by the dotted line is connected in the same way to the second FET M ₂ 210, and the drain of the last of these FETs represented by the dotted line is the top of the stack, ie j Coupled to the source of the second FET M _j 201. Each FET in the stack is controlled by a V _Control coupled to the gate of the FET via a corresponding gate impedance (eg, represented base resistances RB ₁ 214, RB ₂ 216,..., RB _j 218). Is done.

The FET channel terminal closer to N ₁ is called the “source” and the opposite terminal is called the “drain”, but this is not a requirement. The FETs may be implemented in a wide variety of designs and polarities (eg, N-channel FETs and P-channel FETs, enhancement and depletion modes, and various threshold voltages, etc.). Furthermore, a circuit in which a transistor is used may be expressed using various specifications described later. Transistor polarity and drain-source positioning can often be replaced without significantly changing the principle of operation of the circuit. Rather than representing numerous possible permutations of drafting specifications, transistor polarity, and transistor design, those skilled in the art will naturally appreciate that the exemplary descriptions and figures presented here are descriptions of all such alternative circuits and The equivalent device design is represented similarly.

For most RF switches purposes (FIG. 2 represented in a resistance RBx214,216,218) base impedance, the transfer function is minimum (expected signal present between _{N 1} and _{N 2} It should be combined with the effective corresponding gate capacitance of the FET to form a low pass filter that has at least a single pole roll-off at a frequency less than 1/6 of the design frequency. In practice, the at least one pole frequency is desirably one-tenth or lower of such a lowest design signal frequency. Such low frequency base control allows each FET's gate voltage to follow the voltage at the FET's channel, thus ensuring an accurate on or off gate / source voltage (Vgs), and Limit both Vgs and drain / gate voltage (Vds) to prevent gate insulation breakdown.

  Ideally, a device switch as shown in FIG. 2 has a net voltage capability equal to the BVds of the individual FETs multiplied by the number (j) of FETs included in the stack. In this way, a stack of 10 transistors, each having a BVds of 1.8 volts, can ideally switch a signal having a peak amplitude of 18 volts. In practice, unfortunately, such stacks may not be able to support such ideal voltages. The voltage withstand capability can be increased by increasing the number of devices included in the stack, but this can cause a significant increase in the corresponding required integrated circuit area.

For example, suppose BVds for a given manufacturing process is 2 volts (ie, each single transistor can handle 2V), but the 16V signal must be controlled. Ideally, a stack of 8 transistors can control a signal with a peak voltage of 16V. If eight transistors are actually insufficient for this task, more transistors must be added to support the required voltage. Unfortunately, the stack series resistance is the sum of the individual device resistances. As a result, as the number of stacked devices increases by a factor S, the on-resistance of the switch increases as well. Therefore, the impedance of each device must be reduced by a factor S to maintain the required overall on-resistance (or insertion loss). This requires that the area of each such device is increased by a factor S. When each think the S additional FET having an area increased by S times, the total area of the FET in the stack is clear that may increase as S ^2. At some point, the switch area is tremendous. Furthermore, the parasitic capacitance of these transistors generally increases with area and can cause a number of additional problems.

  Therefore, it is necessary to identify and eliminate problems that prevent several stacked FETs from controlling the ideal voltage, ie, the individual FET's BVds multiplied by the number of FETs. . In the present specification, such problems are mitigated or eliminated, allowing the stacked transistors to withstand a voltage that reaches or equals the theoretical maximum of a given BVds of the constituent transistors. Embodiments relating to devices and methods for manufacturing such devices are described.

  Investigation of faults observed for multiple stacked transistor RF switches at a voltage lower than the expected applied switch voltage (Vsw) has shown that the small parasitic capacitance (Cpd) previously considered negligible is It was concluded that a significant imbalance could be unexpectedly caused in the distribution of Vsw across individual transistors. To reduce this distribution imbalance, the capacitance to the internal stack node is added, in contrast to previous practice that simply makes the drain-source capacitance (Cds) non-uniform for the transistors connected in series (stacked). Or it is changed intentionally.

  One embodiment is a stacked transistor having a transistor stack having a plurality of configuration transistors (FETs) coupled in series with drains to sources so as to form a series string with internal nodes between adjacent transistors. RF switch device. This embodiment has an effective drain-source capacitance Cds for one transistor that is significantly different from that of the other transistors in the stack. Their relative Cds values are at least 2%, 5%, or 10%, or at least 0.5% for each of the majority of the constituent transistor pairs, and / or effectively adjust the capacitance of the stack. May be different. The adjustment is effective when the mismatch in the magnitude of Vds-off distributed over all the constituent transistors becomes large when the Cds values are made substantially equal. Embodiments may include discrete capacitive elements coupled to internal nodes of the series string and / or may include transistors having different Cds values due to design differences, and There may be different Cds between the majority of the pairs of transistors in the stack.

  Another embodiment also includes a stack having a transistor stack having a plurality of configuration transistors (FETs) coupled in series with drains to sources so that an internal node forms a series string between adjacent transistors. Type transistor RF switch device. This embodiment has a separate physical capacitor element Ccomp that effectively adjusts the capacitance of the transistor stack by being coupled to an internal node of the series string. The adjustment is effective when the discrepancy in the magnitude of Vds-off distributed over all the constituent transistors becomes large when all the Ccomp capacitors are removed. Ccomp capacitors may be manufactured as metal-insulator-metal (MIM) capacitors, or other discrete elements having an impedance that is primarily capacitive at the frequency (primary frequency) of the signal normally switched by the RF switch. The physical properties of

  A further embodiment is a method of manufacturing an RF switch having a plurality of configuration transistors connected in series with a series string with an internal node between each pair of adjacent transistors, and comprising the effectiveness of different transistors included in the stack Establishing significantly different values for integrated drain-source capacitance Cds. Significantly different values may be values that vary by at least 2%, 5%, or 10%, or by at least 0.5% for each of the majority of the constituent transistor pairs, and / or the capacitance of the stack. May be adjusted effectively. Adjustment is effective when the effective drain-source capacitance is made substantially more equal when the Vds-off magnitude distribution distributed across all components due to the voltage Vsw applied to the RF switch increases. It is. The method may include the additional step of determining a parasitic drain capacitance other than a drain-source capacitance coupled to an internal node included in the series string, and further at an end node of the RF switch. There may be a further step of determining the voltage of the node to which the parasitic drain capacitance is coupled relative to the voltage of. The method establishes a value of capacitance coupled to a particular internal node of the series string of stacked transistors, and such capacitance value is applied across the capacitance in operation to voltage weight the capacitance. There may be a further capacitance balancing step that is multiplied by a number that reflects the proportion of Vsw that appears. Thus, the sum of the capacitances thus voltage weighted is approximately zero for the particular node. The method further comprises the step of maintaining node balance between each of the majority of adjacent transistor pairs, or thus maintaining node balance between each adjacent transistor pair of the stack. You may have.

  Yet another embodiment is a method of manufacturing an RF switch having a plurality of serially connected configuration transistors in a series string with an internal node between each pair of adjacent transistors, the stack comprising one or more of the stacks Combining the individual capacity characteristics, or alternatively at least two individual capacity characteristics, to the internal nodes of the system. The individual capacitance characteristic is an individual element having an impedance that is mainly capacitive at the frequency of the signal normally switched by the RF switch, and Vds− distributed across all the constituent transistors by the voltage Vsw applied to the RF switch. An off magnitude mismatch is needed to effectively adjust the capacitance of the stack so that all of the individual capacitance characteristics can be removed. The method may include the additional step of determining a parasitic drain capacitance Cpd coupled to an internal node included in the series string, and the parasitic compared to the voltage at the end node of the RF switch. There may be the step of determining the voltage at the node to which the drain capacitance is coupled. Determining the parasitic drain capacitance may include analyzing semiconductor device layout geometry parameters including parameters describing the interconnect traces. The method includes a capacitance balance that weights each value of capacitance coupled to a particular internal node of the series string of stacked transistors according to a number that reflects the ratio of Vsw represented across the capacitance in operation. There may be steps. Thus, the sum of the capacitance values thus weighted is approximately zero for the particular internal node. The method may further comprise performing a transition to previous period for each of a majority of the internal nodes of the series string or for all of the internal nodes of the serial string.

FIG. 2 is a simplified diagram of a simple transmit / receive RF switch. 1 represents a basic FET stack designed to function as an RF switch device. This represents the partial pressure in the j stacked FETs included in the RF switch that is “off”. 3 represents the effective parasitic drain capacitance Cpd for the FETs in the stack represented in FIG. It is an equivalent circuit showing the influence of parasitic drain capacitance Cpd. 6 is an equivalent circuit representing the addition of capacitance adjustment between stack nodes to compensate for Cpd in the circuit depicted in FIG. FIG. 6 is a graph representing the relative Vds of each of the transistors in a 16 transistor stack as a function of the ratio of Cpd to Cds value. FIG. 6 is a graph representing the effective number of transistors in a transistor stack having 2 to 16 transistors as a function of the ratio of Cpd to Cds value. Fig. 5 schematically represents further capacitance details of the circuit represented in Fig. 4;

  Embodiments of the present invention will be more readily understood with reference to the accompanying drawings. In the drawings, like reference numerals and symbols indicate like elements.

As represented in FIG. 2, the above background describes a typical stacked RF switch. FIG. 3 shows that a switch as represented in FIG. 2 shows the applied RF voltage (eg, V _S 302 to V _Ref 304) so that an equal voltage is applied to each of the j FETs in the stack. Describes how to divide. Each FET is in a high impedance state, but the switch conducts somewhat due to the effective drain-source capacitance Cdsx corresponding to each FETx. Since the “off” conduction is almost entirely due to their capacitance, the FET structure itself is not shown, and j corresponding effective drain-source capacitances Cds ₁ 306, Cds ₂ 308, Cds ₃ 310,. , Cds _(j−1) 312 and Cds _j 314 are represented. This capacitive divider applies applied voltage Vs across each corresponding drain node to generate Vd ₁ 316, Vd ₂ 318, Vd ₃ 320,..., Vd _(j−2) 322 and Vd _(j−1) 324. Split.

When each Cds _x has the same value, Vs is Vd ₁ (all voltages with respect to V _Ref ) Vs / j, Vd ₂ is 2 × Vs / j, and thereafter Vd _{(j−1 )} = (J-1) It should be distributed uniformly across the FETs to continue as well with the relationship Vs / j. Because of this expected result, stacked FET devices are pre-fabricated to establish Cds for each FET with approximately the same value. Other parasitic capacitances in such FET stacks are generally very small with respect to Cds, and furthermore usually do not directly divide the applied voltage. Thus, the effects of such other parasitic capacitances have been largely ignored with respect to the voltage distribution across the FET in a stacked FET RF switch.

For example, as shown in FIG. 2, the series combination of transistors to form a stacked switch forms a path for conduction when the switch is “on”. In its “on” state, the conduction path connects the end nodes (the lower N ₁ 202 and the upper N ₂ 204) through all channels of the configuration FETs M ₁ 208 to M _j 212. Only nodes along such a conduction path are referred to herein as "series nodes" or "series string nodes" of transistor stacks or stacked switches. Typically, most of the series string nodes are either the drain or source of a configuration FET where all such nodes are coupled so close that they can be referred to as “drain nodes”. However, other elements may be arranged in a series string of transistor stacks, in which case they may have nodes that are on the conduction path and are also “series nodes” or “nodes of series strings” .

[Unbalanced voltage distribution due to parasitic drain capacitance]
After investigating the problem of breakdown at unexpectedly low voltages for stacked FET RF switches, Applicants have determined that the voltage distribution across the FETs included in such a stack is not uniform. Thus, in general, one FET was applied with a higher percentage of the applied switch voltage than the other FETs in the stack. That most stressed FET failed first, causing other FETs to fail in a domino fashion. Under further investigation, the Applicant has determined that voltage distribution imbalances are often caused by parasitic capacitances that are small compared to the drain-source capacitances and thus have been missed previously.

As described above, the value of the drain parasitic capacitance (Cpd) is generally at most a few percent of the corresponding drain-source capacitance Cds. As such, Cpd has often been ignored in calculating the expected voltage distribution. However, even small values of Cpd can have a large effect on the voltage distribution, depending on the node to which such Cpd is coupled. The Cpd that couples the drain to the node Np that receives a certain combination of signals at the RF switch end node pulls these signals into the drain and changes the voltage distribution across the FETs in the stack from ideal balance to unfavorable. Let That is, the node Np is A × V ₁ + B × V ₂ (A and B are sometimes complex or time dependent multipliers, V ₁ is the voltage at one end of the open RF switch, and V ₂ Is the voltage at the other end of the open RF switch.), The signal can be drawn into the corresponding drain to distort the distribution of V ₂ -V ₁ across the FET. Any Cpd that couples to such Np (node having a significant component of A × V ₁ + B × V ₂ ) can be related to the net voltage distribution. When such a signal at Np is significantly different from the ideal drain voltage, the imbalance in signal injection and the resulting voltage distribution is very large due to its large voltage, even when Cpd is small. sell. Such an effect will be described in more detail below with reference to FIG.

  All integrated circuit technologies are equal and have not succeeded in increasing the RF switch breakdown voltage by stacking devices in series. In some techniques, the Cpd may be fairly clearly significant compared to the corresponding Cds, and so is not missed in that case. However, in some cases, the problem is not recognized or solved by these techniques because the performance is so poor that the problem is not pursued. In fact, the very large parasitic components can in some cases be an important reason why stacked switch designs are not pursued by certain integrated circuit technologies.

Special case: The parasitic drain capacitance Cpd is mainly arranged between the corresponding drain and ground. In a special case, each significant Cpd _n (1 <= n <= (j−1)) is a common voltage V _COM (eg, ground) to which one end of the corresponding RF switch is connected. Combined. In other words, Np _n each is, one end portion and essentially the same signal of the RF switch, normally, V _COM or receiving ground. This special case is treated first for two reasons. First, it is close to many practical switches, and second, it is conceptually simple.

An RF switch is often placed between an RF signal node and ground or a circuit common node. This is, for example, the situation for the RF switch S ₃ transmit / receive antenna switch circuit represented in Figure 1. As shown in FIG. 1, the transmit RF signal TransmitS _RF 104 is applied to one side of S ₃ 112 and the other side of switch S ₃ is connected to ground 116. Also, it is not exceptional that the parasitic drain capacitance Cpd is mainly coupled to the ground level. For example, Cpd consists primarily of parasitic capacitance to the substrate, which may be held at ground potential (at least for RF purposes). A special case appears where at least one of these conditions exists, each associated Cpd is coupled to a signal at one end of the RF switch. In such a special case, the Cpd of each FET may have an effect on the RF switch voltage distribution that is approximately proportional (off) to the value of Cpd multiplied by the number n of FETs. Note that n = 1 for FETs having a source coupled to V _COM or ground. Thus, n indicates how many FETs are connected in series between the drain of FETn and V _COM or ground.

FIG. 4 represents three FETs 402, 404, and 406 in a stack of j FETs disposed between the first node N ₁ 202 and the second node N ₂ 204. To understand the special case, assume that N ₁ 202 is ground and Np _n 410 and Np _(n−1) 414 are coupled to ground for at least the RF signal. Also, assume that the ideal voltage at Dn (the drain of the central FET M _n 402) is (n / j) V _N2 . Such an ideal voltage distribution is obtained, for example, in the RF switch reflected by FIG. 4 when all values Cds are equal and all values of Cpd are truly negligible. Also, temporarily, it is assumed that all values of Cds are certainly equal, and that all values of Cpd _x (x is not equal to n) are truly negligible.

The effect of Cpd _n 408 on the signal present at the drain D _n 502 of FET _n can then be analyzed with reference to FIG. FIG. 5 is the equivalent circuit of FIG. 4 reflecting the conditions and assumptions described above. The equivalent Cpd capacitance for (j−n) FETs on FET M _n corresponds to capacitor 504 having a value of Cds / (j−n). Similarly, Cds for the bottom n FETs corresponds to a capacitor having the value Cds / n. As mentioned above, Cpd values have usually been ignored because they are generally at most about 2% of the value of Cds. However, the examination of FIG. 5 reveals that the effect of Cpd _n is much greater than suggested by its size in proportion to Cds, at least when n reaches j for a large stack. For example, j = 16, n = 15, and Cpd = 2% of Cds. Even if Cpd _n is only 2% as large as Cds, it has 30% as large as an equivalent capacitor (capacitor 506) that is parallel to Cpd _n . As such, Cpd _n is clearly not negligible. _Indeed, the voltage resulting in D n 502 is, (15/16) _{N 2} or (0.9375) of _{N 2} (Cpd _n does not exist), rather than the ideal value, (0.9202 ) N ₂ . Thus, a single Cpd _{15 that} has only 2% value of Cds will cause the drain-source voltage across M ₁₆ to be (1.276 / 16) N ₂ rather than (1/16) N _2. To do. This is a 27.6% increase in Vds ₁₆ . Further, as shown in FIG. 7, the impact is greatly increased when each D _n has a corresponding Cpd _n with respect to ground.

FIG. 7 is a graph showing the relative distribution of the drain-source voltage Vds _n (n = 1 to 16) for each of the FETs included in the stacked RF switch as a function of the size of Cpd with respect to Cds. The relative Vds is the Vds for each FET _n that is compared to the voltage of N ₂ / j. Since j is 16 in this example, the relative Vds is the Vds of the particular FET compared to 1/16 of the RF switch voltage. A curve is given for each of the 16 FETs included in the stack, and is labeled on the right side of the graph when space allows.

As expected from a review of FIG. 5, FIG. 7 shows that the imbalance between the ideal expected voltage across each FET _n appears most at the end of the stack, ie, n = 1 and n = 16, And it shows that the magnitude of Vds _n increases as the value of n increases. In practice, the FET 16 receives a relative voltage (relative Vds = 2) that is 200% greater than the ideal value when each Cpd is exactly 1.6% of the Cds. The assumption in this figure is that each Cds has the same value, Cpd has the same proportional value of Cds, and each Cpd is an RF signal equal to the voltage (eg, ground) at the source connection of FET M _1. Is to be coupled to.

  FIG. 8 also reflects the effect of uncompensated Cpd capacitance as a function of the ratio of Cpd to Cds. The effective stack height is the actual withstand voltage of the RF switch in units of BVds. This is the same for each stack transistor. The effective stack height for a stack of j FETs is shown for the actual stack height j = 1 (no stack at all) to 16 transistors. When the drain parasitic capacitance Cpd is very small (0.0001% or 0.01%) compared to the drain-source capacitance Cds, the stack has a withstand voltage obtained by multiplying each FET's BVds by j. Works almost ideally. In this way, when Cpd / Cds = 0.0001, the 13 FET stack (j = 13) basically behaves like an ideal stack of 13 devices, so it is Begins with an effective stack height of 13. Since each other trace similarly starts with an effective stack height value equal to the actual stack height of the switch, the trace does not require signing. As the ratio of Cpd / Cds increases, the effective stack height decreases as the uncompensated Cpd value causes a non-uniform distribution of voltage across the FETs in the stack and decreases fastest for the largest stack (j = 16) To do. As the ratio of Cpd to Cds increases, the transistors no longer share the source voltage equally, and usually the top transistor Mj in the stack receives a significantly higher voltage than the other transistors. When Mj breaks, the remaining transistors follow with the domino effect. The effectiveness is therefore limited by the voltage across Mj. For 16 stacks, the ideal breakdown voltage of the stack is 16 × BVds, but at a Cpd / Cds ratio of only 1.6% (0.016), it will not work at 8 × BVds, so 8 Effective stack height.

  For the special case, it is clear that the stack may fail at a much lower voltage than expected, at least when the Cpd value is considered. It is likely that the FET located furthest from the RF switch ground connection will initially fail at a total RF switch voltage that is part of the ideal or expected peak voltage. Several solutions to this problem are described below for special cases. The occurrence of problems and corresponding general solutions follow.

[Solutions for special cases]
FIG. 6 is an equivalent circuit similar to the equivalent circuit of FIG. 5 and represents a different set of solutions according to the value of k. Node D _{(n + k)} 602 is selected based on factors such as ease of layout and effectiveness of node 602 to compensate or adjust node D _n 502. The top k nodes may be more effective, as described below. As an example, when j = 16 and n = 10, k is set to any value from 1 to 6 (ie, j−n). Selection of node 602 results in a capacitor 604 consisting of a series combination of Cds above D _{(n + k)} 602. Therefore, capacitor 604 has a value of Cds / (j−n−k) (k <(j−n)). Of course, if k = (j−n), then D (n + k) 602 is directly coupled to N ₂ 204 so that capacitor 604 is not present. Similar to FIG. 5, capacitor 506 represents the series combination of Cds of all FETs up to FETM _n and thus has a value of Cds / n. Capacitor 506, along with Cpd _n 408, is coupled to ground. Adjustment is accomplished by adding a compensation capacitor Ccomp _n 608 to compensate for the disruptive effects of Cpd _n 408.

In one conceptually simple solution, k = (j−n) so that D _{(n + k)} 602 is directly coupled to N ₂ 204. Then a perfect adjustment of D _n 502 is easily achieved by making Ccomp _n 608 equal to Cpd _n × (n / k). This can be a solution for any value of k. Such adjustment is an iterative process because node D _{(n + k)} 602 needs to be subsequently compensated by the effect of Ccomp _n 608. In this special case (all Cpd components effectively connected to the source of M ₁ ), the solution according to the form represented in FIG. 6 first compensates for the node D ₁ (Cdp ₁ ) and then each It is most easily implemented by compensating for a series of drain nodes.

It may be useful in some embodiments to have k = 1 so that Ccomp _n is simply placed in parallel in M _{(n + 1)} channels. One advantage resides in the relative simplicity of placing Ccomp _n between two adjacent nodes. Another advantage may occur when the design of M (n + 1) is modified so that the intrinsic capacitance Cds _{(n + 1)} is significantly larger. Changes to the layout and design of the transistors M ₁ to M _j serves to reduce the size of Ccomp capacitance required, it is possible to eliminate the need for several individual Comp capacitance.

On the other hand, when k> 1 (ie, when Ccomp is coupled to the drain of the upper transistor in the stack), the actual capacitance required for this Ccomp is generally higher for k. It becomes smaller in proportion to It should be noted that the breakdown voltage of this Ccomp must be increased correspondingly. To implement the special case, the solution requires a separate Ccomp capacitor to bridge multiple FETs when k> 1. In the special case (ie, when the various effective Cpds are coupled primarily to the node corresponding to the end of the RF switch coupled to the bottom transistor M ₁ ), the k> = 1 solution is This may be implemented by placing a Ccomp capacitor between the drain node D _n and the drain D _{(m> n)} . The drain D _{(m> n)} may be a node corresponding to the end of the RF switch to which M _j is coupled, for example.

  The preference of such coupling to the drains of the FETs that are more distant in the stack depends on the manufacturing parameters and layout of the subject RF switch. Factors that tend to favor such remote node coupling include: a) a layout that accommodates such connections, especially if the Ccomp layout does not produce a less desirable parasitic capacitance; b) a voltage greater than BVds The availability of capacitors suitable for; and c) lack of space applicable to such capacitors. In practice, if the breakdown voltage BVc of the compensation capacitor is sufficiently high, it is useful to couple the compensation capacitor to the end node of the RF switch that is opposite the node to which the compensated Cpd is coupled closest. It is possible. The capacitance required for the compensation capacitor is proportional to 1 / m. Note that m is the number of series FETs in which such compensation capacitors are coupled in parallel. This effect allows a compensation capacitor arranged in parallel with a plurality of FETs to occupy less die area. This is almost always beneficial.

  Thus, the best embodiment for tuning is, among other things, the proximity of the various drain nodes, the suitability of the capacitors to suit manufacturing parameters, the space available for such capacitors, and the die area Depending on whether it can be manufactured on top of other structures without adding. If the adjustment causes difficulties in the layout, it is desirable not to compensate perfectly since j can increase slightly.

A further solution for tuning applies in the special case (each Cpd is coupled to ground or N ₁ ), and in a basic way, the compensation capacitance only for a single transistor (ie k = 1). use. Conceptually, this further solution first compensates for Cpd ₁ by increasing the effective Cds ₂ by an amount equal to Cpd ₁ . Then it increases the effective Cds ₃ by an amount equal to Cpd ₂ , but because Cpd ₂ is coupled across the _two transistors M ₁ and M _2, by increasing by a factor of 2 (ie ₂ Cds ₂ ). Cpd ₂ is compensated. Furthermore, Cds ₃ must increase above Cds _2, which has already increased by the value of Cpd ₁ . Given that all Cpds are equal and all original Cds are equal, for n> 1, each effective Cds must increase by an amount Ccomp _n determined according to the following geometric sequence.

Ｃｐｄ_１の補償から始まるように概念上記載されているが、式はどんな順序で値を求められてもよい点に留意すべきである。全ての補償は当然に製造時に存在しなければならず、従って、補償の順序は実際にはない。

It should be noted that although conceptually described as starting from compensation of Cpd ₁ , the formula may be determined in any order. All compensation must of course be present at the time of manufacture, so there is no actual order of compensation.

Compensation or adjustment can rarely be absolutely accurate, and more accurate values will certainly reach zero for uncompensated Cpd values that are 0.01% or less of Cds. The smaller the stack, the greater the inaccuracy allowed. In the case represented in FIG. 5, a single Cpd ₁₅ assumed to exist resulted in an increased Vds ₁₆ over the ideal value by a factor of 1.28. Furthermore, FIG. 7 suggests that as a result of the same transistor M ₁₆ , Vds ₁₆ has a value about 2.2 times greater than the ideal value when each drain has a corresponding Cpd. Thus, a single parasitic capacitance is not negligible, but by itself it is unlikely to cause a serious voltage distribution imbalance. Thus, the error in adjusting any one particular node is not important if most nodes are reasonably well adjusted.

  Furthermore, even the inaccurate adjustment can substantially increase the voltage capability of the stacked transistor RF switch. For example, if the Cpd capacitance of the stacked transistor RF switch design is primarily coupled to the first end node of the RF switch, the improvement in switch voltage tolerance is the net effective Cds for transistors that are progressively farther from the first end node. Can be realized by gradually increasing. Such a general incremental increase can be achieved, for example, by changing the transistor design and / or by adding individual compensation capacitance. Such a general inaccurate solution is described with respect to FIG. 6 with k = 1.

[Circuits and solutions for general cases]
In fact, there can be any number of places where parasitic capacitance from internal nodes can be coupled. In standard CMOSICs they may be bonded to the substrate. In SOI or GaAs devices, they may be bonded to the metal or package on the back of the part. For all types of devices, the parasitic capacitance can also be coupled to nearby metal lines. A configuration Cpd capacitance coupled to any node having a signal with X × VN ₁ −Y × VN ₂ may limit the RF-capacitance of a large stack to less than j × BVds.

  Not only the effective Cpd of the drain node but also the effective Cds and / or the effective Ccomp may be composed of a plurality of individual component capacitances. The effective Cpd capacitance components may be appropriately coupled to a wide variety of circuit nodes, as will the Ccomp components. Cds is coupled between specific nodes, but may also have multiple constituent capacitances. As a result, the general case is much more complex than the special case described above.

FIG. 9 is developed from part of FIG. 4 to represent such additional complexity. FIG. 9 shows a Cpd _(n−1) 412 coupled to a source node _Sn and a corresponding termination node NP _(n−1) 414 and two end nodes N ₁ 202 and N ₂ 204 of the RF switch, This represents M _n 402 in FIG. FIG. 9 represents an expansion of the effective Cpd _n 408 of FIG. 4 and / or an expansion of the effective compensation capacitance Ccomp. In the first case, Cn _A 902, Cn _B 904 and Cn _C 906 terminated at nodes 908, 910 and 912, respectively, represent the constituent capacitance of Cpd _n 408. Node 908 is RF equivalent of the second end N ₂ 204 of the RF switch, while node 912 is RF equivalent of the first end N ₁ 202 of the RF switch. Finally, node 910 is RF equivalent of different drains _Dq . Since Cpd _n 408 represents such a parallel combination of component capacitances, the total capacitance of Cpd _n 408 is the sum of the three values of Cn _A , Cn _B and Cn _C , assuming no other significant Cpd component is present. It is.

In this general case, the equivalent node Np n ₄₁₀ of FIG. 4 is not the actual node. In any case, however, it is a mathematically equivalent node with an equivalent signal content based on the signal voltage of N ₂ , N ₁ and the relative magnitude of Cn _A 902, Cn _B 904 and Cn _C 906. is there. Be valid signal in the equivalent node Np n ₄₁₀ determines whether close to one of the signals in the signal or N ₁ in N ₂ can be useful. (Net effective) associated signal component of Cpd _n, in most cases, somewhere signals between the ideal voltage and N ₁ of the voltage between, or D _n between the ideal voltage and N ₂ of the voltage of the D _n Lower. In the former case, D _n is said to be suitably closer to N ₂ than N ₁ , while in the latter case, D _n is said to be suitably closer to N ₁ . When M ₁ is coupled to N ₁ (as shown in FIG. 4), the compensation for effective Cpd _n that is coupled closer to N ₁ is _equal to one or more nodes that are coupled closer to N ₂ and D _n Requires an increase in capacitance. The converse is also true, and compensation for effective Cpd _n closer to N ₂ requires an increase in capacitance between one or more nodes closer to N ₁ and D _n . For each drain node n, the effects of each component of Cpd may be calculated as described with reference to FIG. 6, and the effects of all such components are combined to determine the effective Cpd _n. Is done.

In the alternative idea of FIG. 9, capacitances Cn _A 902, Cn _B 904, and Cn _C 906 represent both Cpd and Ccomp components instead of explicitly representing the Cpd component. According to one example of this idea, node 912 is N ₁ and capacitor Cn _C 906 has substantially all of Cpd _n . Node 910 (D _q ) is the second drain from the top, D _{(n + 1)} (ie, q = n + 1), and as a result, Cn _B 904 represents an increase in effective drain-source capacitance Cds _{(n + 1)} . Cn _B 904 may be, for example, an individual capacitor, or it may reflect an increase in Cds resulting from a design change of M _{(n + 1)} . Furthermore, it may reflect a combination of both meanings. Since node 908 is RF equal to N ₂ , Cn _A 902 may be a small discrete capacitor coupled between D _n and N ₂ . Capacitances 902 and 904 are components of Ccomp _n . The values of capacitances 902, 904, and 906 should be established to satisfy Equation 1, as described below, with any unbalance between Cds _n and Cds _{(N + 1)} not included in Cn _B 904. It is. Of course, Ccomp may have any number of component capacitances, and the effects of each Ccomp component may be determined individually and combined as effective Ccomp _n, as described above for determining effective Cpd.

  The general rules for adjusting or compensating the node m, which is the drain of the stacked transistor, are listed below. Each capacitance Cim is arranged between the node m and a different node i. Node m (with an RF switch in operation or in an off state) has a voltage Vm, and under the same conditions, each other node i has a voltage Vi. P is the total number of individual capacitors coupled to node m. Then, based on the calculation of charge injection into node m, equilibrium (and uniform voltage distribution) can be achieved by establishing the following relationship:

ノードの直ぐ上のトランジスタのＣｄｓ及びノードｍの直ぐ下のトランジスタのＣｄｓが等しい限りでは、それらのＣｄｓは、電圧がそれら２つのトランジスタで一様である場合、すなわち、［Ｖ（ｍ＋１）−Ｖ（ｍ−１）］／２＝Ｖｍである場合に、無視されてよい。しかし、ノードｍの上及び下のＶｄｓが、大きさが等しく（且つ符号が逆と）なるよう確立され得ない場合は、各Ｃｄｓは計算に含まれなければならない。たとえＶｄｓが等しいとしても、Ｃｄｓ値は、少なくともそれらが有意に同じでない限りでは、総和に含まれるべきである。

As long as the Cds of the transistors immediately above the node and the Cds of the transistors immediately below the node m are equal, those Cds are equal if the voltage is uniform across the two transistors, ie [V (m + 1) −V If (m−1)] / 2 = Vm, it may be ignored. However, if the Vds above and below the node m cannot be established to be equal in magnitude (and opposite in sign), each Cds must be included in the calculation. Even if Vds is equal, Cds values should be included in the sum, at least as long as they are not significantly the same.

While accuracy is somewhat beneficial, as described above, accuracy is not always necessary to substantially improve the voltage distribution imbalance across the transistors included in the stacked RF switch. For some embodiments, we observe that Cpd on average is more closely coupled to N ₁ than to N ₂ , but significantly increases for most of the FETs, not approximately equal or randomly changing It is sufficient to establish a value for Cds that does (eg, increases by more than 0.03%). Many embodiments of the devices and methods described herein are stack-type by adding a compensation capacitance coupled between the nodes of the transistors in the stack, in particular between the drain node (or equivalent source node). Compensation for undesirable parasitic capacitance in the FET RF switch. Such compensation capacitance can cause adjacent FETs in the stack to have significantly different net values of Cds or establish a compensation network of capacitance that is parallel to the series Cds string of the FET stack.

[Add compensation capacitance]
Cds is described as an effective drain-source capacitance, and here means the net and effect of total effective drain-source capacitance, intentional and unintentional capacitance, unless a different meaning is clarified. The net effective Cds may be altered, for example, simply by coupling primarily capacitive characteristics between the drain and source nodes of the transistors included in the RF switch stack. The predominantly capacitive characteristic is a passive element having an impedance at the frequency of the switching signal that is more capacitive than induction or resistance. As the circuit designer understands, many structures may be manufactured to function as capacitors, or any such capacitor or primarily capacitive characteristic or element may constitute a compensation capacitor or capacitance. Good.

  The compensation capacitance may have a difference between the intrinsic Cds of different constituent transistors of the stack, at least as long as such a difference is an intentional result of a particular design change between the transistors. Certain configuration FETs in the stack may have a different layout than other configuration FETs, or may be designed or manufactured differently to achieve the desired difference in Cds values between the FETs. The manner in which Cds is achieved is not critical to the devices and methods described herein. Instead, any technique may be used to establish a satisfactory effective Cds value. In this way, any significant or intentional difference between the effective Cds of different transistors in the stack may be considered reasonably equivalent to the compensation capacitance.

  If it is feasible to change individual transistor designs to change their effective Cds, such changes can at least partially adjust the capacitance of the transistor stack. Such changes are very sophisticated. However, the required design differences are cumbersome to implement and are relatively difficult to reconstruct if the circuit is to be changed for unrelated reasons. Nonetheless, such a change may provide some or all of the configuration capacitance required to satisfactorily adjust the capacitance of the stacked transistor RF switch.

The simplest design change to change the effective Cds is a simple change in device size. Larger devices inherently have larger Cds values, so physically larger transistors may be used when larger Cds are required. In practice, the intrinsic Cds may suitably be roughly proportional to the device size. In the special case where the Cpd capacitance is primarily coupled to one end node (lower side) of the RF switch, the transistors on the stack require more compensation capacitance. In that case, instead of or in addition to adding individual capacitance between the nodes of the stack's series string, the upper transistor may be progressively increased. The general concept of resizing transistors to at least partially replace the need for individual compensation capacitances applies to the general case of adjusting stacked transistor switches. However, in particular, the following analysis involves the assumptions made for FIGS. 5 and 6 where each Cpd is coupled to a node corresponding to the lowest end node of the RF switch (N ₁ to which M ₁ is coupled): It applies to the special case stack described above with reference to FIG. The width W _n of each transistor M _n (n> 1) is determined as follows for a special case, with W ₁ selected to establish the overall switch resistance to meet performance requirements. Good.

Ｃｄｓは概してトランジスタ幅とともに線形関数であり、一方、Ｃｐｄは通常非線形であるから、式２は容易には更に簡単化されず、また正確にされ得ない。理想的に、式２に従って調整されるスタックは、また、上述される式１の要件を満たす。

Since Cds is generally a linear function with transistor width, while Cpd is usually non-linear, Equation 2 cannot easily be further simplified or accurate. Ideally, a stack tuned according to Equation 2 also meets the requirement of Equation 1 above.

  Capacitances produced by gate isolation may be used for tuning even if they have a relatively low breakdown voltage or are non-linear, for example. Moreover, since parasitic capacitance is often proportional to layout area, adding such a compensation capacitor on the side of the transistor can cause additional parasitic capacitance. This can adjust the iterative process as the solution to the problem changes with each addition of compensation.

  A metal-insulator-metal (MIM) capacitance placed on the switch transistor itself is the best solution in some cases. MIM capacitors placed in this way do not require extra die area and usually do not add at least extra parasitic capacitance to ground. Furthermore, establishing the desired capacitance with MIM capacitors is relatively simple and as a result, it may be easier to review subsequent design iterations compared to solutions based on changing transistor designs. . The MIM capacitor may also have a higher breakdown voltage and is therefore suitable to be coupled between nodes m and i separated by multiple (ie, k> 1 with respect to FIG. 6) transistors. .

[Confirmation and quantification of effective adjustments]
The voltage Vsw applied to the RF switch consisting of j constituent stacked transistors is distributed across the constituent transistors of the stack. Deviation from distribution uniformity may be quantized as a variable V in the portion of Vsw that appears in each transistor. Here, Vds _i for each transistor M _i obtained from Vsw is V _i and the following equation holds.

スタック型トランジスタＲＦスイッチの有用な調整は、スタックの構成トランジスタにわたる分布電圧について変数Ｖをより小さなものとする。ランダムなプロセス変動は、不可避的に、スタック内の異なるトランジスタのＣｄｓの間に小さな差を生じさせる。しかし、変更を伴わない設計は可能な限り完璧であるから、このようなランダムな変更は、概して、分布トランジスタ電圧の不一致を増大させる働きをすべきである。然るに、一方でのＣｄｓの制御による意図的な調整と、他方でのＣｄｓの値のランダムで意図的でない変更とは、（構成トランジスタのＣｄｓをより均一にするよう）デバイス又は方法においてＣｄｓの変化を減らすことが、スタックにわたる電圧分布の不一致を減少又は増大させるかどうかの提示によって、区別されてよい。不一致は、スタック型スイッチを有効に調整する働きをするＣｄｓの偏差を減らす結果として増大する。

Useful tuning of a stacked transistor RF switch makes the variable V smaller for the distributed voltage across the stack's constituent transistors. Random process variations inevitably cause small differences between the Cds of different transistors in the stack. However, such a random change should generally serve to increase the distributed transistor voltage mismatch because the design without change is as perfect as possible. However, intentional adjustment by control of Cds on one side and random and unintentional changes in the value of Cds on the other side are Cds changes in the device or method (to make the Cds of the constituent transistors more uniform). May be distinguished by the presentation of whether to reduce or increase the voltage distribution mismatch across the stack. The discrepancy increases as a result of reducing the Cds deviation which serves to effectively adjust the stack type switch.

  The voltage distribution mismatch across the constituent transistors can also distinguish the distributed tuning capacitance coupled to the internal node of the series string of stacked transistor switches. In eliminating the predominantly capacitive elements coupled to the internal nodes of the switch in the RF switch embodiments described herein, voltage distribution mismatches can be increased if they are distributed tuning capacitances. As a result, removing such capacitance can reduce voltage distribution mismatch when the capacitance is coupled to internal string nodes for other processes other than tuning to increase the voltage withstand capability.

  A random process change in the Cds value can be distinguished from a change that is intentionally implemented to increase voltage immunity that is adjusted by the magnitude of the maximum Cds change. In this way, for the constituent transistors of a stack in a particular device, the maximum Cds is very close to the minimum Cds if the deviation is simply due to random process changes. In order to adjust the stack of j transistors, the size comparison (Cds (max) / Cds (min) -1) is required to be at least j / 200, or at least j / 100, or at least j / 50. It's okay. Regardless of j, the tuned transistor stack may be required to have a Cds (max) that exceeds Cds (min) by at least 2%, at least 5%, or at least 10%, or at least 20%. Any of these limitations may be explicitly added to any method, process or apparatus claim to distinguish secondary designs not intended to be encompassed by the claims.

  The difference in net effective Cds value between adjacent pairs of transistors included in the series stack may be required to be at least 5% for most of such adjacent pairs. Alternatively, the difference in such net effective Cds values between adjacent pairs of transistors is compared to the total Cpd (excluding the Cds component) for the internal node of the string between the pair of transistors. Good. The Cds difference may then be required to exceed the total Cpd for the nodes between adjacent pairs, for at least half of the adjacent pairs, or for the majority of the adjacent pairs. Calculations may be made by averaging so that the sum of the Cds differences between all adjacent transistor pairs is required to exceed the sum of the total Cpd for the nodes between that pair.

[Determination of Cpd value]
Integrated circuit designers often face the need to evaluate circuit parasitics, and any such technique, along with parasitic drain-source capacitance Cds, provides parasitic drain capacitance Cpd to other nodes other than the corresponding source. May be used to establish. A complete circuit simulation based on the detailed parameters of the selected manufacturing process and layout, if the simulation program is accurate and sufficient processing power is effective to complete the task in a reasonable amount of time, Ideal. It is also possible to assemble the circuit, examine (measure) the distribution of the RF switch voltage across the individual transistors of the stack, and estimate an effective Cpd value from such measurements. However, as noted above, substantial improvements in RF switch voltage capability can be achieved without complete compensation. However, less burdensome techniques may be used to estimate the Cpd value.

  An example of such a technique for estimating parasitic capacitance from a node to a substrate is as follows.

なお、ｗ及びＬはノードの幅及び長さであり、ｔはノードの厚さであり、ｈは接地面の上のノードの高さであり、ε＝ε_０×８．８５４ｅ−１２Ｆ／ｍ、及びε_０は基板材料の比誘電率である。

Here, w and L are the width and length of the node, t is the thickness of the node, h is the height of the node above the ground plane, and ε = ε ₀ × 8.854e−12F / m , And ε ₀ are the relative permittivity of the substrate material.

  A number of computer programs exist to help designers estimate parasitic circuit elements. For example, Medici, ADS / Momentum, FastCap, HFSS, and other programs are capable of two-dimensional (2D) and three-dimensional (3D) parasitic capacitance estimation. These tools allow a more accurate estimate of the capacitance for all other nodes near the analyzed node.

[Conclusion]
The above is an example implementation and novel of a related method of adjusting or compensating the switch capacitance to resolve the low breakdown voltage of the stacked transistor RF switch resulting from an imbalance in the overall RF switch voltage distribution across the stack transistors. Represents special features. It is also an implementation and novel feature of an integrated circuit stack transistor RF switch device that uses capacitive tuning or compensation characteristics, which improves the net breakdown voltage compared to the absence of such feature. Is described. It will be apparent to those skilled in the art that various deletions, substitutions, and modifications of the form and details of the methods and apparatus represented can be made without departing from the scope of the invention. Since it is impractical to explicitly list all embodiments, it is understood that each of the practical combinations of features described above as suitable for an apparatus or method embodiment is An alternative embodiment is configured. In addition, each practical combination of equivalents of such device or method alternatives also constitutes a separate alternative embodiment of the subject device or method. Accordingly, the scope of the present invention should be determined only with reference to the claims, when such claims are amended during the pendency of this application, and such limitations are claimed. Should not be limited by the features expressed above, unless specifically mentioned or intentionally involved.

  The transistors in the stacked transistor RF switch described herein are preferably of an insulated gate type or biased so as not to pass a DC gate current. Even more desirably, the transistor may be a FET specifically referred to as a MOSFET, regardless of the fact that it does not use a metal oxide semiconductor (MOS) structure. Although FETs are described as if they are N-polar (NMOS), they may be PMOS as well. Embodiments may use undesired transistors even if they require circuit adjustment to handle the control node DC current.

  The circuits shown and described herein are merely examples, and are alternatives known to those skilled in the art that are easily and unexpectedly applied with current knowledge common to those skilled in the art or in the future. In view of this, it should be understood that alternatives that are readily apparent to those skilled in the art are also described.

  All variations that come within the meaning and range of equivalency of the various claim elements are included within the scope of the corresponding claims. Each claim recited in the claims is intended to encompass any system or method that differs in no way from the literal language of such claims. However, only if such a system or method is not a prior art embodiment. For this purpose, each element recited in each claim should be construed as broadly as possible, and includes all equivalents to such element as much as possible without including the prior art. Should be understood.

Claims (20)

  A method for providing capacitance to regulate a stacked switch, wherein the stacked switch has a plurality of transistors coupled in series, and an internal node is an internal node between each pair of adjacent transistors The capacitance value of each capacitive element based on a sum of products between the capacitance value of each capacitive element coupled to a particular internal node and the corresponding voltage across each of the capacitive elements. Balancing the charge injection to the particular internal node by adjusting the capacitance coupled to the particular internal node such that the sum of products between and the corresponding voltage is substantially zero. Equilibrating charge injection to the specific internal node comprises:
Determining a capacitance value for each capacitive element coupled to the particular internal node;
Determining the voltage across each of the capacitive elements;
Determining a sum of products between each of the determined capacitance values and the determined corresponding voltage;
Have
The adjustment of a capacitance coupled to the particular internal node is based on a sum of the determined products between each of the determined capacitance values and the determined corresponding voltage. The method described in 1.   3. The method of claim 1, further comprising the step of repeatedly adjusting the capacitance so that a sum of products between a capacitance value of each capacitive element coupled to the specific internal node and a corresponding voltage is substantially zero. the method of.   The method of any one of claims 1 to 3, wherein the plurality of transistors comprises at least five transistors.   The method of any one of claims 1 to 4, further comprising balancing charge injection to most internal nodes of the stacked switch.   The method according to claim 1, further comprising balancing charge injection for each internal node of the stacked switch.   The method according to any one of the preceding claims, wherein adjusting the capacitance comprises adjusting a capacitance value of one or more capacitive elements coupled to the particular internal node. Adjustment of the capacitance, the effective drain of at least one transistor - to vary the source capacitance, comprising the step of changing the size of at least one transistor of the plurality of transistors of said stacked in the switch, The method according to claim 1.   The method according to any one of the preceding claims, wherein adjusting the capacitance comprises coupling at least one physical capacitive mechanism to one or more internal nodes of the stacked switch. The adjustment of the capacitance is
The effective drain of at least one transistor - to vary the source capacitance, the step of changing the size of at least one transistor of the plurality of transistors of said stacked in the switch,
Coupling at least one physical capacitive mechanism to one or more internal nodes of the stacked switch;
The method according to claim 1, comprising:   11. A method according to claim 9 or 10, wherein the coupling step comprises coupling at least one physical capacitive mechanism between two internal nodes of the stacked switch.   The capacitance adjustment comprises coupling at least one physical capacitive mechanism between an end node of the stacked switch and an internal node of the stacked switch. The method according to item. A stack type switch device,
(A) A transistor stack having a plurality of transistors in which all drains and sources are coupled in series to form a series string, the internal node being an internal node between adjacent transistor pairs , the series string at one end A transistor stack coupled to a first stacked switch end node and coupled to a second stacked switch end node at the other end;
(B) Total effective drain-source capacitance Cds of each transistor,
(C) drain parasitic capacitance Cpd of each internal node, the drain parasitic capacitance Cpd being not included in the total effective drain-source capacitance Cds of any transistor in the transistor stack,
Have
In the high-impedance operation, the drain parasitic capacitance Cpd is coupled at the other end to said first and combined and the internal node at one end to a node having a second signal based on a stacked switching end node signal set at the for at least half of the adjacent transistor pair, wherein the total effective drain of the adjacent transistor pairs - the value of the source capacitance, only the value is greater than the amount of the entire drain parasitic capacitance Cpd of internal nodes between said adjacent pair of transistors different from each other, Stack type switch device.   In high impedance operation, the first stack type switch end node has a voltage V1, the second stack type switch end node has a voltage V2, and each drain parasitic capacitance Cpd has an internal voltage at one end and the other end. The stacked switch device of claim 13, wherein the stacked switch device is coupled at a node to a node having an AC voltage of A * V 1 + B * V 2.   15. The stacked switch device according to claim 13 or 14, wherein the Cds values of the two transistors in the transistor stack are different from each other by at least 2%, by at least 5%, or by at least 10%.   The stack type switching device according to any one of claims 13 to 15, wherein the Cds value between different transistors in the transistor stack is different at least partially due to a difference between transistors.   17. The stack type switch device according to claim 16, wherein the Cds value between different transistors in the transistor stack is different at least partially due to a design difference between transistors.   The Cds values between different transistors in the transistor stack are different because of the physical capacitive mechanism arranged between the internal node of the stacked switch device and the other node of the stacked switch device. The stacked switch device according to claim 13, wherein the node is another internal node or a stacked switch end node. A stack type switch device,
(A) A transistor stack having a plurality of transistors in which all drains and sources are coupled in series to form a series string, and an internal node is an internal node between adjacent transistors, and the series string is first at one end. A transistor stack, coupled to a stack switch end node of the first and a second stack switch end node at the other end,
(B) at least one physical capacitor element Ccomp coupled between an internal node of the series string of the transistor stack and a parasitic drain capacitance Cpd;
Have
One physical capacitor element Ccomp of the at least one physical capacitor element Ccomp is coupled between an internal node of a specific transistor and the other node, and the other node is adjacent to the specific transistor. A stack type switch device, which is a stack type switch end node connected to an internal node of a non-performing transistor or a transistor not adjacent to the specific transistor.   The stacked switch device according to any one of claims 13 to 19, wherein the plurality of transistors include at least five transistors.

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