JP3215292B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a semiconductor element used for various information communication devices, and more particularly to a measure for reducing signal distortion of a transmission / reception switching GaAs FET switch.

[0002]

2. Description of the Related Art In recent years, as the importance of information communication has increased, the demand for information communication means, especially for mobile communication systems, has rapidly increased. In such a portable telephone or a cordless telephone, a transmission / reception change-over switch for sharing a receiving circuit and a transmitting circuit with one antenna is used to reduce the size. Hereinafter, the configuration of a conventional transmission / reception switching GaAs FET switch will be described.

FIG. 4 shows a conventional transmission / reception switching GaAs FET.
FIG. 2 is an electric circuit diagram showing a configuration of a switch.
b indicates a shunt FET on the transmission side and a reception side, respectively.
Reference numerals 2a and 2b denote through FEs on the transmission side and the reception side, respectively.
Reference symbol 4 denotes a first control terminal to which the voltage Vc1 is applied, reference numeral 5 denotes a second control terminal to which the voltage Vc2 is applied, reference numeral 6 denotes a transmission signal input terminal, and reference numeral 7 denotes reception. Reference numeral 8 denotes an antenna terminal. Each of the FETs 1a, 1b, 2a, 2b is composed of a GaAs FET. The FETs 2a and 1b are connected to a common first control terminal 4 via resistors 3a2 and 3b1, respectively.
T1a and T1b are connected to a common second control terminal 5 via resistors 3a1 and 3b2, respectively.

Transmission / reception switching GaAs configured as described above
The operation of the sFET switch will be described below.

First, the voltage Vc of the second control terminal 5
2 is a negative voltage that causes the FETs 1a and 2b to pinch off, and the voltage Vc1 of the first control terminal 4 is 0V. As a result, the shunt FET 1a on the transmission side becomes OF
F, the through FET 2a is turned on, the shunt FET 1b on the receiving side is turned on, the through FET 2b is turned off,
Only between the transmission signal input terminal 6 and the antenna terminal 8 is in a state where signals can be circulated. Further, the voltage Vc1 of the first control terminal 4 is set to a negative voltage that causes the FETs 2a and 1b to pinch off, and the voltage Vc1 of the second control terminal 5 is
c2 is set to 0V. As a result, the shunt FET on the receiving side
1a is OFF, the through FET 2a is ON, the shunt FET 1b on the transmission side is ON, and the through FET 2b is O
It becomes an FF, and only the portion between the receiving system terminal 7 and the antenna terminal 8 is in a state where signals can be circulated.

[0006]

However, the configuration of the conventional transmission / reception switching GaAs switch has the following problems.

That is, when the fluctuation in the potential of the drain of the shunt FET 1a on the transmission side during the transmission operation increases with an increase in the signal power, the potential difference between the gate and the drain of the FET 1a decreases, and the shunt FET 1a does not pinch off and the signal is distorted. May occur. Further, in order to prevent the occurrence of distortion during the operation of a large signal, it is necessary to apply an excessively large negative voltage to the shunt FET 1a.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a switch circuit in which a shunt FET and a through FET are arranged, and a means for suppressing a change in drain potential of the shunt FET. The object of the present invention is to effectively prevent signal distortion.

[0009]

Means taken by the present invention to achieve the above object is to reduce the impedance of the input signal to the switch circuit so that the signal applied to the drain of the shunt FET has a low impedance. This is provided with an impedance reducing means for reducing.

Specifically, the measures taken by the invention of claim 1 are as follows:
A semiconductor device comprising: a switching element for switching on / off the flow of a signal in a signal transmission line; and a switch circuit having a shunt FET made of a GaAs FET interposed in a branch line branching from a shunt junction of the signal transmission line. , An impedance reducing means interposed at a stage prior to the shunt junction of the signal transmission line to reduce an impedance of an input signal to the shunt junction, and a stage subsequent to the shunt junction of the signal transmission line. And impedance increasing means for increasing the impedance of a signal flowing through the signal transmission line.

Means taken by the invention of claim 2 is claim 1
Wherein the shunt junction is provided on the signal transmission line upstream of the switching element , and the impedance reduction means is a power amplification element provided upstream of the shunt junction on the signal transmission line; Is an impedance conversion circuit provided downstream of the switching element of the signal transmission line.

Means taken by the invention of claim 3 is claim 1.
Wherein the shunt junction is provided on the signal transmission line upstream of the switching element , and the impedance reducing means is a power amplification element provided downstream of the shunt junction. To the shunt junction of the signal transmission line-
This is an impedance conversion circuit provided between switching elements .

According to a fourth aspect of the present invention, there is provided a switching element for switching on / off the flow of a signal in a signal transmission line, and a branch branched from a shunt junction of the signal transmission line and connected to the ground. GaAsF interposed in the wire
A plurality of switch circuits having a shunt FET made of ET, and a signal in one of the switch circuits is turned on / off of each shunt FET and the switching element.
In the semiconductor device configured to be alternately circulated by turning off, the signal transmission line of each of the switch circuits may include:
The configuration is provided with impedance reducing means for reducing the impedance of the input signal to the switch circuit, and impedance increasing means for increasing the output signal from the switch circuit.

Means taken by the invention of claim 5 is claim 4
Wherein the output side of the signal transmission line in one of the two switch circuits and the input side of the signal transmission line in the other output circuit of the two switch circuits are connected to each other. The common wiring is provided with an impedance conversion circuit functioning as the impedance increasing means in the one switch circuit and the impedance reducing means in the other switch circuit.

The means implemented by the invention of claim 6 is a switching element for switching on / off the flow of a signal in the signal transmission line, and a branch branched from a shunt junction of the signal transmission line and connected to the ground. GaAsF interposed in the wire
A plurality of switch circuits having a shunt FET made of ET, wherein a signal in one of the switch circuits of the switch circuits is alternately passed by turning on / off the shunt FET and the switching element. In the semiconductor device described above, in the first switch circuit among the switch circuits, the first signal transmission line is provided with the switching element at a stage subsequent to the shunt junction, and the first signal transmission line is connected to the first signal transmission line. A power amplifying element interposed before the shunt junction, and the shunt junction- switching of the first signal transmission line;
And an impedance conversion circuit interposed between the elements to increase the impedance of the output signal from the shunt junction.

According to a seventh aspect of the present invention, in the second, third or sixth aspect, the power amplifying element is formed of GaAs.
It is constituted by an FET.

[0017]

According to the first aspect of the present invention, the impedance of the signal input to the switch circuit is reduced by the impedance reducing means, and the voltage amplitude of the signal input to the shunt FET is reduced. Therefore, it is possible to avoid a situation in which the shunt FET does not pinch off and generates signal distortion. In addition, even during a large signal operation, it is possible to suppress an increase in the absolute value of the voltage applied to the gate of the shunt FET. On the other hand, since the impedance increasing means is provided at a stage subsequent to the shunt junction, at least the impedance of the output signal from the switch circuit is returned to the original impedance value, thereby avoiding the problem of signal processing in other circuits. Is done.

According to the second aspect of the present invention, by utilizing the fact that the power amplifying element has a function of reducing the impedance of the signal and providing an impedance conversion circuit on the output side of the switching element, the output signal of the switch circuit is output. It is possible to suppress distortion during processing of a large signal while achieving impedance matching.

According to the third aspect of the present invention, the signal is connected to the signal transmission line including the switching element downstream of the shunt FET while suppressing the occurrence of large signal distortion in the shunt FET downstream of the power amplification element. In other circuit portions, signal processing can be performed without providing an impedance conversion circuit, and an increase in loss can be prevented.

According to the fourth aspect of the present invention, in a circuit in which a plurality of switch circuits are combined, it is possible to achieve impedance matching outside the switch circuit while suppressing the occurrence of signal distortion with a small impedance in the switch circuit. .

According to the fifth aspect of the present invention, when a plurality of switch circuits are combined, one impedance conversion circuit can serve as both the impedance reducing means and the impedance increasing means, so that the configuration is simplified. .

According to the sixth aspect of the present invention, in the first switch circuit, while suppressing the occurrence of signal distortion in the shunt FET due to the large signal amplified by the power amplifying element, the switching element and the second In a two-switch circuit or the like, there is no need to provide impedance conversion means, and it is possible to prevent an increase in loss.

According to the seventh aspect of the present invention, the power amplifying element composed of a GaAs FET has a large gate width, so that the effect of reducing the impedance is particularly remarkable.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is an electric circuit diagram showing a configuration of a transmission / reception switching GaAs FET switch according to a first embodiment, in which a transmission system switch circuit and a reception system switch circuit are combined. In FIG.
Reference numerals a and 1b denote shunt FETs on the transmission side and reception side, respectively. Reference numerals 2a and 2b denote through FETs on the transmission side and reception side, respectively. Reference numeral 4 denotes a first FET to which the voltage Vc1 is applied.
Reference numeral 5 denotes a control terminal to which the voltage Vc2 is applied, reference numeral 6 denotes a transmission signal input terminal, reference numeral 7 denotes a reception terminal, and reference numeral 8 denotes an antenna terminal. Each of the FETs 1a, 1b, 2a, 2
b is made of GaAsFET. The transmission system switch circuit includes a branch line 21 branched from the signal transmission line 20a at the shunt junction A and connected to the ground.
a is provided, a through FET 2a functioning as a switching element is provided on the downstream side of the shunt junction A of the signal transmission line 20a, and a shunt FET 1a is provided on the branch line 21a. The receiving switch circuit is provided with a branch line 21b branched from the signal transmission line 20b at the shunt junction B and connected to the ground, and a through FET 2b is connected to the signal transmission line 20b upstream of the shunt junction B. And a shunt FET is connected to the branch line 21b.
1b is interposed. Note that the output side of the signal transmission line 20a of the transmission system switch circuit and the input side of the signal transmission line 20b of the reception system switch circuit are shared by the wiring 20c connecting the junction C and the antenna terminal 8. The FETs 2a and 1b are connected to a common first control terminal 4 via resistors 3a2 and 3b1, respectively.
1a and 2b are connected to a common second control terminal 5 via resistors 3a1 and 3b2, respectively. This configuration is the same as the configuration of the conventional transmission / reception switching GaAs FET switch shown in FIG.

Here, as a feature of the present embodiment, between the transmission signal input terminal 6 of the signal transmission line 20a and the shunt junction A,
Shunt junction B of signal transmission line 20b-Reception system terminal 7
Between the antenna terminal 8 of the signal transmission line 20c and the junction C
In between, L. each consisting of an inductance and a capacitor. P. F. The first, second, and third impedance conversion circuits 9a, 9b, and 9c are provided. And the first
The impedance conversion circuit 9a converts a signal from the reception signal terminal 6 from high impedance to low impedance, and the second impedance conversion circuit 9b converts a signal to the reception system terminal 7 from low impedance to high impedance. The third impedance conversion circuit 9c converts a signal output from the antenna terminal 8 from low impedance to high impedance, while converting a signal input from the antenna terminal 8 from high impedance to low impedance. In other words, each of the impedance conversion circuits 9a, 9b, 9c converts a signal input into the transmission / reception switching GaAs FET switch into a low impedance, and converts a signal output outside the transmission / reception switching GaAs FET switch to the same high impedance as the impedance before input. It is converted into impedance.

Transmission / reception switching GaAs configured as described above
The operation of the sFET switch will be described below.

First, the voltage Vc of the second control terminal 5
2 is a negative voltage that causes the FETs 1a and 2b to pinch off, and the voltage Vc1 of the first control terminal 4 is 0V. As a result, the shunt FET 1a on the transmission side becomes OF
F, the through FET 2a is turned on, the shunt FET 1b on the receiving side is turned on, the through FET 2b is turned off,
Only between the transmission signal input terminal 6 and the antenna terminal 8 is in a state where signals can be circulated. At this time, the input signal is converted into a low impedance by the first impedance conversion circuit 9a arranged on the input side of the shunt FET 1a on the transmission side. Also, the signal transmission line 20c to the antenna terminal 8
The output signal is converted again into the impedance of the original input signal by the third impedance conversion circuit 9c provided therein.

The voltage Vc of the first control terminal 4
1 is set to a negative voltage that causes the FETs 2a and 1b to pinch off, and the voltage Vc2 of the second control terminal 5 is set to 0V. As a result, the shunt FET 1a on the receiving side becomes OF
F and the through FET 2a are turned on, the shunt FET 1b on the transmitting side is turned on, and the through FET 2b is turned off, so that only the signal between the receiving system terminal 7 and the antenna terminal 8 can be in a state where signals can be circulated. At this time, the signal input from the antenna terminal 8 is converted to a low impedance by the third impedance conversion circuit 9c, and is again converted to the original input signal impedance by the second impedance conversion circuit 9b by the signal transmission line 20b. A signal is output from the receiving system terminal 7.

As described above, in this embodiment, the voltage amplitude of the input signal from the transmission signal input terminal 6 is reduced by arranging the three impedance conversion circuits 9a, 9b and 9c in each signal transmission path. Shunt FET
1a. Specifically, in the present embodiment, the impedance of the input signal is reduced from 50Ω to 10Ω by the first impedance converter 9a. As a result, the drain amplitude of the shunt FET 1a due to the input signal is reduced to 1 / √5, whereby the power that can be transmitted without distortion can be increased by a factor of 10. Further, the absolute value of the gate applied voltage for transmitting the same power can be reduced to 1 / √5.

The impedance of the output signal from the antenna terminal 8 is converted to an impedance of 50Ω by the third impedance conversion circuit 9c, and is input from the antenna terminal 8 to 1 by the third impedance conversion circuit 9c.
The signal converted to 0Ω is supplied to the second impedance conversion circuit 9.
is converted into an impedance of 50Ω by b,
Problems such as the occurrence of impedance mismatch with other circuits do not occur. In addition, since the drain amplitude of the shunt FET 1b of the receiving switch circuit is also reduced, there is an effect that distortion of the received signal can be suppressed.

In this embodiment, the impedance conversion circuit is a L.I. P. F. Although an impedance conversion circuit of the type was used, the present invention is not limited to such an embodiment. P. F. Needless to say, a similar configuration can be obtained with an impedance conversion circuit of a type or a microstrip line or an impedance conversion circuit using a strip line.

(Second Embodiment) Next, a second embodiment will be described.

FIG. 2 shows a transmission / reception switching Ga according to the second embodiment.
FIG. 2 is an electric circuit diagram showing a configuration of an AsFET switch, and reference numerals 1a and 1b denote shunt FEs on a transmission side and a reception side, respectively.
T, 2a and 2b indicate through-FETs on the transmitting and receiving sides, respectively, 4 indicates a first control terminal to which a voltage Vc1 is applied, and 5 indicates a second control terminal to which a voltage Vc2 is applied. Reference numeral 6 indicates a transmission signal input terminal, reference numeral 7 indicates a reception system terminal, and reference numeral 8
Indicates an antenna terminal. Each of the FETs 1a, 1b, 2
Both a and 2b are composed of GaAs FETs.
A branch line 21 branched from the signal transmission line 20a of the transmission system switch circuit at the shunt junction A and connected to the ground.
a is provided, a through FET 2a functioning as a switching element is provided on the downstream side of the shunt junction A of the signal transmission line 20a, and a shunt FET 1a is provided on the branch line 21a. In the receiving switch circuit, the signal transmission line 20b of the receiving switch circuit is provided.
A branch line 21b that branches off from the shunt junction B and is connected to the ground is provided. A through FET 2b is provided in the signal transmission line 20b upstream of the shunt junction B, and a shunt FET 1b is provided in the branch line 21b. Has been established. The output side of the signal transmission line 20a of the transmission system switch circuit and the input side of the signal transmission line 20b of the reception system switch circuit are
It is shared by the wiring 20c connecting the junction point C and the antenna terminal 8. The FETs 2a and 1b are connected to a common first control terminal 4 via resistors 3a2 and 3b1, respectively. The FETs 1a and 2b are connected to a common second control terminal 5 via resistors 3a1 and 3b2, respectively.
It is connected to the. This configuration is the same as the configuration of the conventional transmission / reception switching GaAs FET switch shown in FIG.

Here, as a feature of this embodiment, the transmission signal input terminal 6 of the signal transmission line 20a and the shunt junction A
In between, instead of the impedance conversion circuit,
While the AsFET 10 is interposed, the signal transmission line 20b
Between the receiving system terminal 7 and the FET 2b and the signal transmission line 20c
Between the antenna terminal 8 and the junction point C, each of which has an inductance and a capacitor. P. F. The second and third impedance conversion circuits 9b and 9c are provided. The second and third impedance conversion circuits 9b and 9c
Are the same as the functions described in the first embodiment. On the other hand, the power amplifying GaAs FET 10 is configured to have a large gate width so as to exhibit the function as a power amplifying element, so that its impedance is extremely small. Specifically, in this embodiment, the impedance becomes about 10Ω. In other words, Ga for power amplification
AsFET 10 and each impedance conversion circuit 9b, 9
c converts the signal input into the transmission / reception switching GaAsFET switch into a low impedance, and converts the signal output from the transmission / reception switching GaAsFET switch into the same high impedance as the impedance before input.

The operation of the transmission / reception switching GaAs FET switch of the present embodiment configured as described above will be described below.

In a portable telephone system, a power amplifying element is arranged on the input side of a transmission signal of a transmission / reception changeover switch. Usually, a GaAs FET having a large gate width is used for the power amplifying element because high efficiency and low distortion are required. Since the GaAs FET has a large gate width for power amplification, it has an impedance of about 10Ω. Therefore, in this embodiment, a GaAs FET for power amplification is used.
Is located on the input side of the transmission system switch circuit,
A third impedance conversion circuit 9c for converting an output signal to the antenna terminal 8 into a 50Ω system used in a normal system is arranged, and the impedance is converted from 10Ω to 50Ω on the output side of the reception system switch circuit. Second
The impedance conversion circuit 9b is provided.
Therefore, distortion can be suppressed by the same effect as in the first embodiment.

Further, in the present embodiment, a transmission / reception switching GaAs FET switch is used instead of the first impedance conversion circuit 9a for converting a high impedance required for the first embodiment to a low impedance, which is required in the first embodiment. GaAs FET 10 for power amplification used on the transmission side
, The impedance conversion circuit arranged in the transmission system can be completed only by the third impedance conversion circuit 9c. Therefore, it is possible to simplify the configuration and reduce the loss due to the impedance conversion circuit.

(Third Embodiment) Next, a third embodiment will be described.

FIG. 3 shows a transmission / reception switching Ga according to the third embodiment.
FIG. 2 is an electric circuit diagram showing a configuration of an AsFET switch, and reference numerals 1a and 1b denote shunt FEs on a transmission side and a reception side, respectively.
T, 2a and 2b indicate through-FETs on the transmitting and receiving sides, respectively, 4 indicates a first control terminal to which a voltage Vc1 is applied, and 5 indicates a second control terminal to which a voltage Vc2 is applied. Reference numeral 6 indicates a transmission signal input terminal, reference numeral 7 indicates a reception system terminal, and reference numeral 8
Indicates an antenna terminal. Each of the FETs 1a, 1b, 2
Both a and 2b are composed of GaAs FETs.
A branch line 21 branched from the signal transmission line 20a of the transmission system switch circuit at the shunt junction A and connected to the ground.
a is provided, a through FET 2a functioning as a switching element is provided on the downstream side of the shunt junction A of the signal transmission line 20a, and a shunt FET 1a is provided on the branch line 21a. In the receiving switch circuit, the signal transmission line 20b of the receiving switch circuit is provided.
A branch line 21b that branches off from the shunt junction B and is connected to the ground is provided. A through FET 2b is provided in the signal transmission line 20b upstream of the shunt junction B, and a shunt FET 1b is provided in the branch line 21b. Has been established. The output side of the signal transmission line 20a of the transmission system switch circuit and the input side of the signal transmission line 20b of the reception system switch circuit are
It is shared by the wiring 20c that connects the junction point C and the antenna terminal 8. The FETs 2a and 1b are connected to a common first control terminal 4 via resistors 3a2 and 3b1, respectively. The FETs 1a and 2b are connected to a common second control terminal 5 via resistors 3a1 and 3b2, respectively.
It is connected to the. This configuration is the same as the configuration of the conventional transmission / reception switching GaAsFET switch shown in FIG.

Here, as a feature of this embodiment, a power amplifying GaAs FET is provided between the transmission signal input terminal 6 and the shunt junction A of the signal transmission line 20a of the transmission system switch circuit.
10 is provided between the shunt junction A of the signal transmission line 20a and the through FET 2a. P. F. A type impedance conversion circuit 9d is provided. The function of the impedance conversion circuit 9d is the same as the function described in the first embodiment. On the other hand, the power amplification GaAs FET 10
Is configured to have a large gate width so as to exhibit a function as a power amplifying element, and therefore has an extremely small impedance. Specifically, in this embodiment, 1
The impedance becomes about 0Ω. The impedance conversion circuit 9d sets the impedance of the signal flowing from the power amplification GaAs FET 10 to the through FET 2a to 1
Convert from 0Ω to the original 50Ω.

Transmission / reception switching GaAs configured as described above
The operation of the sFET switch will be described below.

In this embodiment, the GaAsF for power amplification is used.
By disposing the shunt FET 1a causing distortion between the ET 10 and the impedance conversion circuit 9d, which is an output impedance matching circuit, a signal is input to the shunt FET 1a with a small voltage amplitude.

In this embodiment, as compared with the second embodiment, the impedance conversion circuit 9b of the receiving switch circuit required in the second embodiment is not required, so that the circuit configuration can be further simplified. In addition, since an additional impedance conversion circuit is not required in the receiving switch circuit, an increase in loss in the receiving switch circuit can be prevented.

In each of the above embodiments, an example is shown in which each of the transmission system and the reception system is one system. However, the present invention is not limited to each embodiment, and both the transmission system and the reception system are used. It goes without saying that the present invention can be applied to a case where there are a plurality.

Further, in each of the above embodiments, an example has been described in which the power amplifying element is constituted by a GaAs FET. However, the present invention is not limited to such an embodiment, and a voltage controlled element such as a MOSFET is used. Needless to say, it can be applied similarly.

[0047]

As described above, according to the first aspect of the present invention, there is provided a switch circuit in which a switching element is provided on a signal transmission line and a shunt FET is disposed on a branch line of the signal transmission line. In a semiconductor device, an impedance reducing unit is provided on the front side of the shunt junction, while an impedance increasing unit is provided on the rear side of the shunt junction. By reducing the voltage amplitude of the input signal to the shunt FET, It is possible to prevent the occurrence of signal distortion and increase the power that can be transmitted without distortion.

According to the second aspect of the present invention, since the power amplifying element is used as the impedance increasing means in the first aspect, the signal distortion during the processing of a large signal is prevented while the function of reducing the impedance of the power amplifying element is prevented. Can be suppressed.

According to the third aspect of the present invention, an impedance conversion circuit is provided between the shunt junction and the switching element while using the power amplifying element as the impedance reducing means of the first aspect.
It is possible to eliminate the need for an impedance conversion circuit in another circuit portion connected to a signal transmission line including a switching element at a stage subsequent to the ET, thereby preventing an increase in loss.

According to the fourth aspect of the present invention, in a circuit in which a plurality of switch circuits are combined, the impedance reducing means is provided on the input side of each switch circuit, and the impedance increasing means is provided on the output side of each switch circuit. In addition, the occurrence of signal distortion of a signal in each switch circuit can be effectively suppressed.

According to the fifth aspect of the present invention, in a circuit in which a plurality of switch circuits are combined, when each signal transmission line partially overlaps, one impedance conversion circuit serves as both the impedance reducing means and the impedance increasing means. As a result, the configuration can be simplified.

According to the invention of claim 6, in a circuit in which a plurality of switch circuits are combined, a power amplifying element is provided in front of the shunt junction of one switch circuit, and the shunt junction-switching of another switch circuit is performed. Since the impedance conversion circuit for reducing the impedance is provided between the elements, it is possible to prevent an increase in loss while suppressing the occurrence of large signal distortion.

According to the seventh aspect of the present invention, the power element is Ga
Since the GaAs FET is constituted by an AsFET, it is possible to effectively prevent the generation of large signal distortion in the switch circuit by utilizing the characteristics of the GaAs FET having a large gate width and a large impedance reducing effect.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram of a transmission / reception switching GaAs FET switch according to a first embodiment.

FIG. 2 is an electric circuit diagram of a transmission / reception switching GaAsFET switch according to a second embodiment.

FIG. 3 is an electric circuit diagram of a transmission / reception switching GaAsFET switch according to a third embodiment.

FIG. 4 is an electric circuit diagram of a conventional transmission / reception switching GaAs FET switch.

[Explanation of symbols]

Reference Signs List 1 shunt FET 2 through FET 3 resistor 4 first control terminal 5 second control terminal 2 6 transmission signal input terminal 7 reception system terminal 8 antenna terminal 9 impedance conversion circuit (impedance reduction means, impedance increase means) 10 GaAs FET for power amplification ( Impedance reduction means)

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kazuo Miyatsuji 1-1, Sachimachi, Takatsuki City, Osaka Prefecture Inside Matsushita Electronics Corporation (56) References JP-A-4-105417 (JP, A) JP JP-A-3-237807 (JP, A) JP-A-6-29811 (JP, A) JP-A-7-303001 (JP, A) JP-A-8-70245 (JP, A) JP-A-5-136674 (JP JP-A-63-245013 (JP, A) JP-A-7-235802 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) H03K 17/00-17/70 H01P 1/15

Claims (7)

(57) [Claims] 1. A signal transmission in a signal transmission line is turned on.
A switching element for switching off and a Ga interposed on a branch line branching from a shunt junction of the signal transmission line.
In a semiconductor device provided with a switch circuit having a shunt FET composed of an AsFET, an impedance reduction interposed between the signal transmission line and the shunt junction before the shunt junction to reduce an impedance of an input signal to the shunt junction. And a means for increasing the impedance of a signal flowing through the signal transmission line, the impedance increasing means being provided downstream of the shunt junction of the signal transmission line. 2. The semiconductor device according to claim 1, wherein said shunt junction is located at said signal transmission line .
The impedance reducing means is provided before the switching element , the impedance reducing means is a power amplifying element provided before the shunt junction, and the impedance increasing means is provided on the signal transmission line.
A semiconductor device, which is an impedance conversion circuit provided downstream of a switching element. 3. The semiconductor device according to claim 1, wherein the shunt junction is located at the signal transmission line .
The impedance reducing means is provided before the switching element , the impedance reducing means is a power amplifying element provided after the shunt junction, and the impedance increasing means is the shunt junction of the signal transmission line. A semiconductor device comprising an impedance conversion circuit interposed between a point and a switching element . 4. A signal transmission line is turned on.
A plurality of switch circuits each having a switching element for switching off and a shunt FET made of a GaAs FET interposed on a branch line branched from a shunt junction of the signal transmission line and connected to the ground; And a signal transmission line of each of the switch circuits is connected to a signal transmission line of each of the switch circuits. A semiconductor device comprising: an impedance reducing unit that reduces an impedance of a signal; and an impedance increasing unit that increases an output signal from the switch circuit. 5. The semiconductor device according to claim 4, wherein an output side of a signal transmission line in one of the two switch circuits of the switch circuits and the other of the two switch circuits. And the input side of the signal transmission line in the output circuit is configured by a common wiring, and the common wiring includes the impedance increasing means in the one switch circuit and the impedance reducing means in the other switch circuit. A semiconductor device provided with a functioning impedance conversion circuit. 6. A signal transmission in a signal transmission line is turned on.
A plurality of switch circuits each having a switching element for switching off and a shunt FET made of a GaAs FET interposed on a branch line branched from a shunt junction of the signal transmission line and connected to the ground; In a semiconductor device configured to alternately pass a signal in one of the switch circuits according to ON / OFF of the shunt FETs and the switching elements, the first switch circuit of the switch circuits includes: In the first signal transmission line, the switching element is provided at a stage subsequent to the shunt junction, and a power amplification element provided at a stage prior to the shunt junction of the first signal transmission line. And the shunt junction- switch of the first signal transmission line
And an impedance conversion circuit interposed between the switching elements to increase the impedance of the output signal from the shunt junction. 7. The semiconductor device according to claim 2, wherein the power amplifying element is a GaAs FET.