JP3986780B2 - Complementary push-pull amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a complementary push comprising a complementary element using an active element for amplifying a half-wave of a pair of high-frequency input signals by a semiconductor and an anti-active element for amplifying the remaining half-wave of the high-frequency input signal. The present invention relates to a pull amplifier.
[0002]
[Prior art]
In general, an amplifier configured using a semiconductor amplifying element uses a push-pull configuration in order to realize a wide frequency band, high efficiency, and high linearity. In such complementary push-pull amplifiers, the operating point is generally placed at a class B operating point with good power efficiency. Class B complementary push-pull amplifiers use, for example, balanced / unbalanced converters to input two active elements and signals with the same potential and phase difference of 180 °, and each amplifies only the positive potential (or negative potential) portion. Then, for example, an amplifier that amplifies power efficiently by reducing distortion by combining again using a balanced / unbalanced converter.
[0003]
However, when the balance-unbalance converter is used as described above, there is a problem that the circuit scale becomes large. Therefore, by using an anti-active element as one of the two active elements, the circuit size can be reduced, and a complementary push-pull configuration that achieves high efficiency and high linearity is sometimes used. Here, the active element and the anti-active element refer to semiconductor amplification elements having duality such as an N-type FET and a P-type FET.
[0004]
FIG. 11 is an equivalent circuit diagram showing a conventional complementary push-pull amplifier described in, for example, JP-A-11-205049. In the figure, 1 is an input terminal, 2 and 3 are DC blocking capacitors, 4 and 5 are resistors for applying an input bias, 6 and 7 are power supply terminals, 8 is an N-type FET as an active element, and 9 is an anti-active element. P-type FETs 10 and 11 are output bias applying inductors, 12 and 13 are power supply terminals, 14 and 15 are ground terminals, 16 is a DC blocking capacitor, and 17 is an output terminal.
[0005]
Next, the operation will be described.
In the complementary push-pull amplifier shown in FIG. 11, the signal received at the input terminal 1 is input to the N-type FET 8 and the P-type FET 9. The N-type FET 8 amplifies the signal corresponding to the phase from 0 ° to 180 ° of the signal input from the operating point determined by the bias supplied via the input bias applying resistor 4 and the output bias applying inductor 10. Output. In the P-type FET 9, a signal corresponding to a phase from 180 ° to 360 ° of a signal input from an operating point determined by a bias supplied via the input bias applying resistor 5 and the output bias applying inductor 11 is output. Amplify and output. Signals output from the N-type FET 8 and the P-type FET 9 are synthesized by the output terminal 17.
[0006]
In this way, by forming a complementary push-pull amplifier using a pair of complementary elements composed of an N-type FET 8 and a P-type FET 9, a potential is applied to these two transistors using, for example, a balanced / unbalanced converter. Therefore, it is not necessary to input signals having the same phase difference of 180 °, so that the circuit can be reduced in size. Furthermore, high efficiency can be realized by operating a pair of complementary elements together in class B. Further, since the N-type FET 8 and the P-type FET 9 have duality, the output signal synthesized by the output terminal 17 amplifies the entire wave of the input signal, and a low distortion can be realized.
[0007]
[Problems to be solved by the invention]
Since the conventional complementary push-pull amplifier is configured as described above, when such a conventional complementary push-pull amplifier is used, it is necessary to use the output bias applying inductors 10 and 11 having a large element scale. In order to further reduce distortion, waveforms amplified by an active element such as an N-type FET 8 and an anti-active element such as a P-type FET 9 must have the same potential and a phase difference of 180 °. However, since the characteristics of the active element and the anti-active element are usually different, it is difficult to realize this, and the characteristics of the anti-active element are generally inferior to those of the active element. When combining these characteristics, there was a problem that the characteristics of the active element could not be sufficiently extracted.
[0008]
The present invention has been made to solve the above-described problems, realizes downsizing of a circuit, and realizes a continuous sine wave by combining the characteristics of an active element and an anti-active element, An object of the present invention is to obtain a complementary push-pull amplifier having high gain, high efficiency, and low distortion characteristics.
[0009]
[Means for Solving the Problems]
  The complementary push-pull amplifier according to the present invention uses an N-type FET whose source is grounded as an active element, and a P-type FET whose source is connected to a power source as an anti-active element.Loaded with a characteristic adjustment element that adjusts the gain and phase of the N-type FET between the N-type FET and the ground terminal to align the characteristics of the N-type FET and P-type FETThen, the source of the P-type FET is connected to the power source, the connection point of both gates is connected to the input terminal via a capacitor, the connection point of the drain is the output terminal, and the gates of the N-type FET and the P-type FET Are applied with different bias voltages, and the bias point of the N-type FET and P-type FET is set to class A or class AB.
[0012]
The complementary push-pull amplifier according to the present invention uses a characteristic adjusting inductor as a characteristic adjusting element.
[0013]
The complementary push-pull amplifier according to the present invention uses a characteristic adjusting resistor as a characteristic adjusting element.
[0014]
In the complementary push-pull amplifier according to the present invention, in order to align the characteristics of the N-type FET and the P-type FET, the characteristic adjusting element for adjusting the phase of the N-type FET or the gain and the phase is provided as Loaded between the input terminals.
[0015]
The complementary push-pull amplifier according to the present invention uses a characteristic adjusting resistor as a characteristic adjusting element.
[0016]
The complementary push-pull amplifier according to the present invention uses a characteristic adjusting delay element as a characteristic adjusting element.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is an equivalent circuit diagram showing a complementary push-pull amplifier according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes an input terminal for receiving a signal input to the complementary push-pull amplifier, and reference numerals 2 and 3 denote DC blocking capacitors for removing a DC component of the signal received at the input terminal 1. Reference numerals 4 and 5 are connected to the DC blocking capacitor 2 or 3, and are input bias applying resistors for applying an input bias for determining the operating point of the complementary push-pull amplifier, and 6 and 7 are applied with the input bias. This is a power supply terminal for supplying power for input bias to the resistor 4 or 5 for use.
[0023]
Reference numerals 18 and 19 denote a pair of complementary elements constituting the complementary push-pull amplifier according to the first embodiment. Reference numeral 18 denotes a P-type FET as an anti-active element. Reference numeral 19 denotes a drain connected to the drain of the P-type FET 18. N-type FET as an active element. A power supply terminal 20 is connected to the source of the P-type FET 18 and supplies an output bias for determining the operating point of the complementary push-pull amplifier. 21 is a ground terminal for grounding the source of the N-type FET 19. It is. Reference numeral 16 denotes a DC blocking capacitor for removing a DC component connected to the drains of the P type FET 18 and the N type FET 19. Reference numeral 17 denotes a P type FET 18 and an N type FET 19 from which the DC component is removed by the DC blocking capacitor 16. This is an output terminal for synthesizing signals from and outputting them to the outside.
[0024]
The input terminal 1, DC blocking capacitors 2, 3 and 16, input bias applying resistors 4, 5, power supply terminals 6, 7, and output terminal 17 are the same as those shown in FIG. The equivalent part.
[0025]
Next, the operation will be described.
In the complementary push-pull amplifier according to the first embodiment shown in FIG. 1, the signal received at the input terminal 1 is input to the gates of the P-type FET 18 and the N-type FET 19 via the DC blocking capacitor 2 or 3. In the P-type FET 18 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 via the input bias applying resistor 4 and the output bias supplied from the power supply terminal 20. Further, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FET 19 as an active element, the operating point is the input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and the output bias supplied from the power supply terminal 20 through the P-type FET 18. And the signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0026]
The signals amplified by the P-type FET 18 and the N-type FET 19 are respectively output from the drains of the P-type FET 18 and the N-type FET 19 and sent to the output terminal 17 through the DC blocking capacitor 16 to be synthesized. Output to the outside. The source of the N-type FET 19 is grounded by the ground terminal 21, and the drain-source potential of the P-type FET 18 and the N-type FET 19 is supplied from the power supply terminal 20. The supply of the output bias to the drains of the P-type FET 18 and the N-type FET 19 is commonly performed at a single power supply terminal 20.
[0027]
As described above, according to the first embodiment, since different voltages can be applied as the gate voltages of the P-type FET 18 and the N-type FET 19, the effect of adjusting the operation (bias) point of each FET can be realized. can get.
[0028]
Further, since the power supply terminal 20 for supplying a bias to the drains of the P-type FET 18 and the N-type FET 19 can be made common and a single power source, the price can be reduced. Further, the drain of the N-type FET 19 is directly connected to the power supply. Since the bias is supplied via the P-type FET 18, it is possible to achieve multistage connection and to obtain a high gain.
[0029]
The input bias configuration is not limited to the configuration shown in FIG. 1, and an input / output matching circuit may be used.
[0030]
Embodiment 2. FIG.
Since the complementary push-pull amplifier according to the second embodiment has the same configuration as the complementary push-pull amplifier described in the first embodiment, the same reference numerals are used for the same parts, and detailed description thereof is omitted. Different settings and operations will be described.
In the complementary push-pull amplifier according to the second embodiment, the bias points of the N-type FET as the active element and the P-type FET as the anti-active element are set to class A or class AB as compared with those described in the first embodiment. The set points are different.
[0031]
Next, the operation will be described.
Similar to the first embodiment, the complementary push-pull amplifier according to the second embodiment shown in FIG. 1 receives the signal received at the input terminal 1 via the DC blocking capacitor 2 or 3 and the P-type FET 18 and the N-type FET 19. Input to the gate.
In the P-type FET 18 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 via the input bias applying resistor 4 and the output bias supplied from the power supply terminal 20. Further, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FET 19 as an active element, the operating point is the input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and the output bias supplied from the power supply terminal 20 through the P-type FET 18. And the signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point. The operating points of the P-type FET 18 and the N-type FET 19 are set to bias points that operate in class A or class AB.
[0032]
The signals amplified by the P-type FET 18 and the N-type FET 19 are respectively output from the drains of the P-type FET 18 and the N-type FET 19 and sent to the output terminal 17 through the DC blocking capacitor 16 to be synthesized. Output to the outside. Further, the output sides of the P-type FET 18 and the N-type FET 19 are both in a high impedance state. The source of the N-type FET 19 is grounded by the ground terminal 21, and the drain-source potential of the P-type FET 18 and the N-type FET 19 is supplied from the power supply terminal 20. The supply of the output bias to the drains of the P-type FET 18 and the N-type FET 19 is commonly performed at a single power supply terminal 20.
[0033]
As described above, according to the second embodiment, during the complementary push-pull amplification operation, the output side of the P-type FET 18 and the N-type FET 19 are both high impedance, so that an output bias applying inductor is not required. The effect that the circuit can be reduced in size is obtained.
[0034]
In the second embodiment, as in the first embodiment, the input bias configuration is not limited to the configuration shown in FIG. 1, and input / output matching may be used.
[0035]
Embodiment 3 FIG.
FIG. 2 is an equivalent circuit diagram showing a complementary push-pull amplifier according to Embodiment 2 of the present invention. In the figure, 1 is an input terminal, 2, 3 and 16 are DC blocking capacitors, 4 and 5 are input bias applying resistors, 6 and 7 are power supply terminals, 17 is an output terminal, and 18 is a complementary type according to the first embodiment. P-type FET as an anti-active element of a push-pull amplifier, 19 is also an N-type FET as an active element, 20 is a power supply terminal, 21 is a ground terminal, and these are shown in FIG. Since it is a part equivalent to those of Form 1, the detailed description is omitted.
[0036]
Reference numeral 22 is loaded between the source of the N-type FET 19 and the ground terminal 21, and the gain and phase of the N-type FET 19 are adjusted to adjust the N-type FET 19 as the active element and the P-type FET 18 as the anti-active element. This is a characteristic adjusting inductor as a characteristic adjusting element for aligning characteristics.
[0037]
Next, the operation will be described.
In the complementary push-pull amplifier according to the second embodiment shown in FIG. 2, the signal received at the input terminal 1 is input to the gates of the P-type FET 18 and the N-type FET 19 via the DC blocking capacitor 2 or 3. In the P-type FET 18 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 through the input bias applying resistor 4 and the output bias supplied from the power supply terminal 20, and the operating point is determined. Further, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FET 19 as an active element, the operating point is set by the input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and the output bias supplied from the power supply terminal 20 through the P-type FET 18. The signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0038]
The signals amplified by the P-type FET 18 and the N-type FET 19 are respectively output from the drains of the P-type FET 18 and the N-type FET 19, sent to the output terminal 17 through the DC blocking capacitor 16, and both are synthesized. Output to the outside. Here, the source of the N-type FET 19 is connected to the ground terminal 21 via the characteristic adjusting inductor 22 and is grounded by the ground terminal 21. Thus, by loading the characteristic adjusting inductor 22 between the N-type FET 19 and the ground terminal 21, the gain of the N-type FET 19 can be reduced and the phase can be further delayed. Therefore, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform by adjusting the inductor value of the characteristic adjusting inductor 22. Note that the drain-source potentials of the P-type FET 18 and the N-type FET 19 are supplied from the power supply terminal 20.
[0039]
As described above, according to the third embodiment, as in the case of the first and second embodiments, downsizing of the circuit, reduction in cost associated with a single power source, and multistage connection are realized. Furthermore, since the characteristic adjusting inductor 22 is loaded between the N-type FET 19 and the ground terminal 21, the gain of the N-type FET 19 is reduced by adjusting the characteristic adjusting inductor 22. By delaying the phase, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform, so that it is possible to achieve a complementary push-pull amplifier having good low distortion characteristics.
[0040]
In this case, as in the first embodiment, the input bias configuration is not limited to the configuration shown in FIG. 2, and an input / output matching circuit may be used.
[0041]
Embodiment 4 FIG.
FIG. 3 is an equivalent circuit diagram showing a complementary push-pull amplifier according to Embodiment 4 of the present invention. The same reference numerals are assigned to the corresponding parts, and the description thereof is omitted. In the figure, reference numeral 23 is loaded between the source of the N-type FET 19 and the ground terminal 21, and the N-type FET 19 as an active element and the P-type FET 18 as an anti-active element are adjusted by adjusting the gain and phase of the N-type FET 19. This is a characteristic adjusting resistor as a characteristic adjusting element that aligns the above characteristics.
[0042]
Next, the operation will be described.
In the complementary push-pull amplifier according to the fourth embodiment shown in FIG. 3, the signal received at the input terminal 1 is input to the gates of the P-type FET 18 and the N-type FET 19 via the DC blocking capacitor 2 or 3. In the P-type FET 18 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 through the input bias applying resistor 4 and the output bias supplied from the power supply terminal 20, and the operating point is determined. Further, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FET 19 as an active element, the operating point is set by the input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and the output bias supplied from the power supply terminal 20 through the P-type FET 18. The signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0043]
The signals amplified by the P-type FET 18 and the N-type FET 19 are respectively output from the drains of the P-type FET 18 and the N-type FET 19 and sent to the output terminal 17 through the DC blocking capacitor 16 to be synthesized. Output to the outside. Here, the source of the N-type FET 19 is connected to the ground terminal 21 via the characteristic adjusting resistor 23, and is grounded by the ground terminal 21. Thus, by loading the characteristic adjusting resistor 23 between the N-type FET 19 and the ground terminal 21, the gain of the N-type FET 19 can be reduced and the phase can be further delayed. Therefore, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform by adjusting the resistance value of the characteristic adjusting resistor 23. Note that the drain-source potentials of the P-type FET 18 and the N-type FET 19 are supplied from the power supply terminal 20.
[0044]
As described above, according to the third embodiment, as in the case of the first and second embodiments, downsizing of the circuit, reduction in cost associated with a single power source, and multistage connection are realized. Furthermore, since the characteristic adjusting resistor 23 is loaded between the N-type FET 19 and the ground terminal 21, the gain of the N-type FET 19 can be reduced by adjusting the characteristic adjusting resistor 23. By delaying the phase, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform, and it is possible to achieve a complementary push-pull amplifier having a low distortion characteristic.
[0045]
In this case as well, as in the case of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 3, and an input / output matching circuit may be used.
[0046]
Embodiment 5 FIG.
FIG. 4 is an equivalent circuit diagram showing a complementary push-pull amplifier according to Embodiment 5 of the present invention. The same reference numerals are assigned to the corresponding parts, and description thereof is omitted. In the figure, reference numeral 24 is loaded between the gate of the N-type FET 19 and the input terminal 1 (connection point of the input bias applying resistor 5), and the gain and phase of the N-type FET 19 are adjusted so that N as the active element This is a characteristic adjusting resistor as a characteristic adjusting element that matches the characteristics of the type FET 19 and the P-type FET 18 as an anti-active element.
[0047]
Next, the operation will be described.
In the complementary push-pull amplifier according to the fifth embodiment shown in FIG. 4, the signal received at the input terminal 1 is fed to the gate of the P-type FET 18 via the DC blocking capacitor 2 on the one hand and to the DC blocking capacitor 3 and characteristics on the other hand. The voltage is input to the gate of the N-type FET 19 through the adjustment resistor 24. In the P-type FET 18 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 through the input bias applying resistor 4 and the output bias supplied from the power supply terminal 20, and the operating point is determined. Further, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FET 19 as an active element, the operating point is set by the input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and the output bias supplied from the power supply terminal 20 through the P-type FET 18. The signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0048]
The signals amplified by the P-type FET 18 and the N-type FET 19 are respectively output from the drains of the P-type FET 18 and the N-type FET 19, sent to the output terminal 17 through the DC blocking capacitor 16, and both are synthesized. Output to the outside. Thus, by loading the characteristic adjusting resistor 24 between the gate of the N-type FET 19 and the input terminal 1, the gain of the N-type FET 19 can be reduced and the phase can be further delayed. . Therefore, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform by adjusting the resistance value of the characteristic adjusting resistor 24. Here, the source of the N-type FET 19 is grounded by the ground terminal 21, and the drain-source potentials of the P-type FET 18 and the N-type FET 19 are supplied from the power supply terminal 20.
[0049]
As described above, according to the fifth embodiment, as in the case of the first and second embodiments, the circuit can be reduced in size, the cost can be reduced and the multi-stage connection can be realized with a single power supply. Furthermore, since the characteristic adjusting resistor 24 is loaded between the gate of the N-type FET 19 and the input terminal 1, the N-type FET 19 can be adjusted by adjusting the resistance value of the characteristic adjusting resistor 24. To achieve a complementary push-pull amplifier having a low distortion characteristic by outputting a continuous sine wave, which can adjust the characteristics of the N-type FET 19 and the P-type FET 18 by delaying the gain and delaying the phase. The effect that it becomes possible is acquired.
[0050]
In this case as well, as in the case of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 4, and an input / output matching circuit may be used.
[0051]
Embodiment 6 FIG.
FIG. 5 is an equivalent circuit diagram showing a complementary push-pull amplifier according to Embodiment 6 of the present invention. The same reference numerals are assigned to the corresponding parts, and description thereof is omitted. In the figure, 25 is loaded between the gate of the N-type FET 19 and the input terminal 1 (the connection point of the input bias applying resistor 5), and the phase of the N-type FET 19 is adjusted to make this N-type FET 19 as an active element. And a delay element for characteristic adjustment as a characteristic adjustment element that matches the characteristics of the P-type FET 18 as an anti-active element.
[0052]
Next, the operation will be described.
In the complementary push-pull amplifier according to the sixth embodiment shown in FIG. 5, the signal received at the input terminal 1 is fed to the gate of the P-type FET 18 via the DC blocking capacitor 2 on the one hand and to the DC blocking capacitor 3 and characteristics on the other hand. The signal is input to the gate of the N-type FET 19 through the adjustment delay element 25. In the P-type FET 18 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 through the input bias applying resistor 4 and the output bias supplied from the power supply terminal 20, and the operating point is determined. Further, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FET 19 as an active element, the operating point is set by the input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and the output bias supplied from the power supply terminal 20 through the P-type FET 18. The signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0053]
The signals amplified in the P-type FET 18 and the N-type FET 19 are output from the respective drains, sent to the output terminal 17 through the DC blocking capacitor 16, and both are combined and output to the outside. Thus, by loading the characteristic adjusting delay element 25 between the gate of the N-type FET 19 and the input terminal 1, the phase of the N-type FET 19 can be delayed. Therefore, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform by adjusting the delay time (line length of the delay line) of the characteristic adjusting delay element 25. Here, the source of the N-type FET 19 is grounded by the ground terminal 21, and the drain-source potentials of the P-type FET 18 and the N-type FET 19 are supplied from the power supply terminal 20.
[0054]
As described above, according to the sixth embodiment, as in the case of the first and second embodiments, downsizing of the circuit, lowering of cost associated with a single power supply, and multistage connection are realized. Furthermore, since the characteristic adjustment delay element 25 is loaded between the gate of the N-type FET 19 and the input terminal 1, adjusting the characteristic adjustment delay element 25 allows the N-type FET 19 to be By delaying the phase, the characteristics of the N-type FET 19 and the P-type FET 18 can be made uniform, and it is possible to obtain an effect that a complementary push-pull amplifier having a low distortion characteristic can be realized.
[0055]
In this case as well, as in each of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 5, and an input / output matching circuit may be used.
[0056]
Embodiment 7 FIG.
FIG. 6 is an equivalent circuit diagram showing a complementary push-pull amplifier according to Embodiment 7 of the present invention. The same reference numerals are assigned to the corresponding parts, and the description thereof is omitted. In the figure, 26 is an active element in a pair of complementary elements used in this complementary push-pull amplifier, and 27 is also an anti-active element. Reference numeral 28 denotes a first P-type FET, and reference numeral 29 denotes a first N-type FET whose drain is connected to the gate of the first P-type FET 28. Reference numeral 30 denotes a second N-type FET, and reference numeral 31 denotes a second P-type FET whose drain is connected to the gate of the second N-type FET 30.
[0057]
The active element 26 is configured by a Darlington circuit including the first P-type FET 28 and the first N-type FET 29, and the anti-active element 27 is configured by a Darlington circuit including the second N-type FET 30 and the second P-type FET 31. The first P-type FET 28 and the second N-type FET 30 are connected to each other at their sources. The input terminal 1 is connected to the gate of the first N-type FET 29 and the gate of the second P-type FET 31 via the DC blocking capacitor 2 or 3, and the output terminal 17 is connected to the first P-type FET 28 and the second P-type FET 31. The N-type FET 30 is connected to the source of the second N-type FET 30 via the DC blocking capacitor 16.
[0058]
Next, the operation will be described.
In the complementary push-pull amplifier according to the seventh embodiment shown in FIG. 6, the signal received at the input terminal 1 is applied to the gates of the first N-type FET 29 and the second P-type FET 31 via the DC blocking capacitor 2 or 3. Entered. Here, the second P-type FET 31 and the second N-type FET 30 in the anti-active element 27 form a Darlington circuit, and each current amplification factor of the second P-type FET 31 and the second N-type FET 30. It operates as a P-type FET having a large current amplification factor approximately equal to the product of Similarly, the first N-type FET 29 and the first P-type FET 28 in the active element 26 form a Darlington circuit. The current amplification factors of the first N-type FET 29 and the first P-type FET 28 are the same. It operates as an N-type FET having a large current amplification factor approximately equal to the product of
[0059]
In the second P-type FET 31 and the second N-type FET 30 constituting the anti-active element 27, the input bias supplied from the power supply terminal 6 and the power supply terminal 20 are supplied via the input bias applying resistor 4. An operating point is determined by the output bias, and a signal corresponding to a phase from 180 ° to 360 ° of the input signal is amplified from the operating point. On the other hand, in the first N-type FET 29 and the first P-type FET 28 constituting the active element 26, the input bias supplied from the power supply terminal 7 via the input bias applying resistor 5 and the second N-type FET 30 are changed. The operating point is determined by the output bias supplied from the power supply terminal 20 and the signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0060]
The signal amplified by the anti-active element 27 composed of an equivalent P-type FET composed of a Darlington circuit is supplied from the source of the second N-type FET 30, and the signal amplified by the active element 26 composed of an equivalent N-type FET is the first. 1 is output from the source of each P-type FET 28. The outputs of the active element 26 and the anti-active element 27 are sent to the output terminal 17 via the DC blocking capacitor 16, and both are combined and output to the outside. Here, the sources of the first P-type FET 28 and the first N-type FET 29 are grounded by the ground terminal 21, and the first N-type FET 29, the second N-type FET 30, and the first N-type FET 30 are connected from the power supply terminal 20. The drain-source potentials of the P-type FET 28 and the second P-type FET 31 are supplied.
[0061]
As described above, according to the sixth embodiment, as in the case of the first embodiment, it is possible to realize circuit miniaturization, cost reduction associated with a single power source, and multistage connection. Further, the first P-type FET 28 and the first N-type FET 29 are Darlington connected to form an equivalent N-type FET, and the second N-type FET 30 and the second P-type FET 31 are Darlington connected to be equivalent. Since the P-type FET is configured, the current amplification factors of the equivalently configured N-type FET and P-type FET are determined by the first P-type FET 28 and the first N-type FET 29 constituting them. Current amplification factor, or the product of the current amplification factor of the second N-type FET 30 and the second P-type FET 31, the N-type FET serving as the active element 26 of the complementary push-pull amplifier, And the reactive element 27 That it becomes automatically equal without characteristics of P-type FET is adjusted, effects such as it is possible to realize an excellent amplifier low distortion characteristics, and high output characteristics can be obtained.
[0062]
In this case, as in the case of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 6, and an input / output matching circuit may be used.
[0063]
Embodiment 8 FIG.
FIG. 7 is an equivalent circuit diagram showing a complementary push-pull amplifier according to the eighth embodiment of the present invention. The same reference numerals are assigned to the corresponding parts, and the description thereof is omitted. In the figure, 32 is an active element in a pair of complementary elements used in this complementary push-pull amplifier, and 33 is also an anti-active element. Reference numeral 34 denotes a first P-type FET, and reference numeral 35 denotes a first N-type FET whose drain is connected to the gate of the first P-type FET 34. 36 is a second N-type FET, and 37 is a second P-type FET whose drain is connected to the gate of the second N-type FET 36.
[0064]
Reference numeral 38 denotes a third N-type FET having a gate connected to the drain of the first P-type FET 34, a drain connected to the source of the first P-type FET 34, and a source connected to the source of the first N-type FET 35. It is. Reference numeral 39 denotes a fourth N-type FET whose gate is connected to the source of the second N-type FET 36 and whose drain is connected to the drain of the second N-type FET 36 and the source of the second P-type FET 37. The first P-type FET 34, the first N-type FET 35, and the third N-type FET 38, the second N-type FET 36, the second P-type FET 37, and the fourth N-type FET 39 are respectively Darlington. A circuit is formed.
[0065]
The active element 32 is configured by a Darlington circuit including the first P-type FET 34, the first N-type FET 35, and the third N-type FET 38, and the second N-type FET 36, the second P-type FET 37, and the fourth The anti-active element 33 is configured by a Darlington circuit including the N-type FET 39. The drain of the third N-type FET 38, the source of the first P-type FET 34, and the source of the fourth N-type FET 39 are connected to each other. The input terminal 1 is connected to the gate of the first N-type FET 35 and the gate of the second P-type FET 37 via the DC blocking capacitor 2 or 3, and the output terminal 17 is the source of the first P-type FET 34. The drain of the third N-type FET 38 and the source of the fourth N-type FET 39 are connected via the DC blocking capacitor 16.
[0066]
Next, the operation will be described.
In the complementary push-pull amplifier according to the eighth embodiment shown in FIG. 7, the signal received at the input terminal 1 is applied to the gates of the first N-type FET 35 and the second P-type FET 37 via the DC blocking capacitor 2 or 3. Entered. Here, the second P-type FET 37, the second N-type FET 36, and the fourth N-type FET 39 in the anti-active element 33 form a Darlington circuit. It operates as a P-type FET having a large current amplification factor approximately equal to the product of the current amplification factors of the N-type FET 36 and the fourth N-type FET 39. Similarly, the first N-type FET 35, the first P-type FET 34, and the third N-type FET 38 in the active element 32 form a Darlington circuit. It operates as an N-type FET having a large current amplification factor approximately equal to the product of the current amplification factors of the P-type FET 34 and the third N-type FET 38.
[0067]
In the second P-type FET 37, the second N-type FET 36, and the fourth N-type FET 39 constituting the anti-active element 33, the input bias supplied from the power supply terminal 6 via the input bias applying resistor 4, and The operating point is determined by the output bias supplied from the power supply terminal 20, and the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified from the operating point. On the other hand, in the first N-type FET 35, the first P-type FET 34, and the third N-type FET 38 constituting the active element 32, the input bias supplied from the power supply terminal 7 via the input bias applying resistor 5, and The operating point is determined by the output bias supplied from the power supply terminal 20 via the fourth N-type FET 39, and the signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0068]
The signal amplified by the anti-active element 33 composed of an equivalent P-type FET composed of a Darlington circuit is amplified from the source of the fourth N-type FET 39, and the signal amplified by the active element 32 composed of an equivalent N-type FET is It is output from the source of the first P-type FET 34 and the drain of the third N-type FET 38, respectively. The outputs of the active element 32 and the anti-active element 33 are sent to the output terminal 17 via the DC blocking capacitor 16, and both are combined and output to the outside. Here, the sources of the first N-type FET 35 and the third N-type FET 38 are grounded by the ground terminal 21, and the first, second, third and fourth N-type FETs 35, 36 are connected from the power supply terminal 20. , 38, 39, and the drain-source potentials of the first and second P-type FETs 34, 37 are supplied.
[0069]
As described above, according to the eighth embodiment, as in the first and second embodiments, the circuit is reduced in size, and the cost reduction and the multi-stage connection due to the single power supply are realized. In addition, the first P-type FET 34, the first N-type FET 35, and the third N-type FET 38 are Darlington connected to form an equivalent N-type FET, and the second N-type FET 36 and the second N-type FET 36 2 P-type FET 37 and fourth N-type FET 39 are Darlington connected to form an equivalent P-type FET, so that the current amplification factor of the equivalently configured N-type FET and P-type FET is The characteristics of the N-type FET serving as the active element 32 of the complementary push-pull amplifier and the P-type FET serving as the anti-active element 33 are approximately equal to the product of the current amplification degrees of the respective FETs constituting them. Without adjustment Therefore, low distortion characteristics can be realized, and high output can be obtained by using N-type FETs (third N-type FET 38 and fourth N-type FET 39) as the final stage transistors. It is possible to obtain an effect that a complementary push-pull amplifier having excellent characteristics can be realized.
[0070]
In this case as well, as in the case of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 7, and an input / output matching circuit may be used.
[0071]
Embodiment 9 FIG.
  FIG. 8 is an equivalent circuit diagram showing a complementary push-pull amplifier according to the ninth embodiment of the present invention. In the figure, 1a, 1bAre input terminals, 2a, 2b, 3a, 3b are DC blocking capacitors, 4a, 4b, 5a, 5b are input bias applying resistors, 6a, 6b, 7a, 7b are power supply terminals, 16a, 16b are DC blocking capacitors, 17 Is an output terminal, 18a and 18b are P-type FETs as anti-active elements, 19a and 19b are N-type FETs as active elements, 20 is a power supply terminal, and 21 is a ground terminal. It is a part equivalent to those of Embodiment 1 attached and shown.
[0072]
  The complementary push-pull amplifier according to the ninth embodiment is a combination of the two complementary push-pull amplifiers according to the first embodiment shown in FIG. 1 in parallel. That is,Input terminal 1a,One push-pull circuit is constituted by the DC blocking capacitors 2a and 3a, the input bias applying resistors 4a and 5a, the power supply terminals 6a and 7a, the DC blocking capacitor 16a, the P-type FET 18a, and the N-type FET 19a.Input terminal 1b,The other push-pull circuit is constituted by the DC blocking capacitors 2b and 3b, the input bias applying resistors 4b and 5b, the power supply terminals 6b and 7b, the DC blocking capacitor 16b, the P-type FET 18b, and the N-type FET 19b.The input terminals 1a and 1b are configured to receive signals having a phase difference of 180 °.In addition, OutThe force terminal 17, the power supply terminal 20, and the ground terminal 21 are shared by both complementary push-pull amplifiers.
[0073]
  Next, the operation will be described.
  Each push-pull circuit performs the same operation as in the first embodiment. Input terminal 1a, 1bReceived at180 degrees out of phaseThe signals are input to the gates of the P-type FETs 18a and 18b and the gates of the N-type FETs 19a and 19b through the DC blocking capacitors 2a and 3a or 2b and 3b, respectively. In the P-type FETs 18a and 18b, the operating point is determined by the input bias supplied from the power supply terminals 6a and 6b and the output bias supplied from the power supply terminal 20 via the input bias applying resistors 4a and 4b. From the point, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the N-type FETs 19a and 19b, the input bias supplied from the power supply terminals 7a and 7b through the input bias applying resistors 5a and 5b and the output bias supplied from the power supply terminal 20 through the P-type FETs 18a and 18b. The operating point is determined at, and the signal corresponding to the phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0074]
Thus, since the amplifier formed by the two sets of push-pull circuits constitutes a differential amplifier circuit, the point A connecting the sources of the N-type FETs 19a and 19b of each push-pull circuit is the virtual ground point. Become. The signals output from the P-type FET 18a and the N-type FET 19a are synthesized at the point B connecting their drains. Similarly, signals output from the P-type FET 18b and the N-type FET 19b are synthesized at a point C connecting their drains. Further, the signals synthesized at the points B and C are sent to the output terminal 17 via the DC blocking capacitors 16a and 16b, synthesized and outputted to the outside. The source of the N-type FET 19 is grounded by the ground terminal 21, and the drain-source potential of the P-type FET 18 and the N-type FET 19 is supplied from the power supply terminal 20. Further, the supply of the output bias to the drains of the P-type FETs 18a and 18b and the N-type FETs 19a and 19b is commonly performed by a single power supply terminal 20.
[0075]
As described above, according to the ninth embodiment, as in the case of the first and second embodiments, downsizing of the circuit, reduction in cost associated with the use of a single power supply, and multistage connection are realized. Furthermore, the push-pull circuit composed of the P-type FET 18a and the N-type FET 19a and the push-pull circuit composed of the P-type FET 18b and the N-type FET 19b constitute a differential amplifier circuit, and the point A becomes a virtual ground point. Therefore, both the signals output from the N-type FET 18a and the P-type FET 19a and the signals output from the N-type FET 18b and the P-type FET 19b are completely centered on a voltage that is half the power supply voltage. Effects such as being able to realize low strain characteristics can be obtained
[0076]
In this case as well, as in the case of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 8, and an input / output matching circuit may be used.
[0077]
Embodiment 10 FIG.
FIG. 9 is an equivalent circuit diagram showing a complementary push-pull amplifier according to the tenth embodiment of the present invention. The same reference numerals are used for the corresponding parts, and description thereof is omitted. In the figure, 40 is a PNP bipolar transistor constituting an anti-active element instead of the P-type FET 18, and 41 is an NPN bipolar transistor similarly constituting an active element instead of the N-type FET 19. The emitter of the PNP bipolar transistor 40 is connected to the power supply terminal 20, and the emitter of the NPN bipolar transistor 41 is connected to the ground terminal 21. The base of the PNP bipolar transistor 40 and the base of the NPN bipolar transistor 41 are connected to each other as the input terminal 1, and the collector of the PNP bipolar transistor 40 and the collector of the NPN bipolar transistor 41 are connected to each other as the output terminal 17. .
[0078]
As described above, the complementary push-pull amplifier according to the tenth embodiment uses the P-type FET 18 used as the anti-active element of the pair of complementary elements by the PNP bipolar transistor 40 and is used as the active element. The N-type FET 19 is replaced by the NPN bipolar transistor 41, the gate of the P-type FET 18 or N-type FET 19 is made to correspond to the base of the PNP bipolar transistor 40 or the NPN bipolar transistor 41, the source corresponds to the emitter, and the drain corresponds to the collector. This is different from the complementary push-pull amplifier in the first embodiment.
[0079]
Next, the operation will be described.
In the complementary push-pull amplifier according to the tenth embodiment shown in FIG. 9, the signal received at input terminal 1 is input to the bases of PNP bipolar transistor 40 and NPN bipolar transistor 41 via DC blocking capacitor 2 or 3. . In the PNP bipolar transistor 40 as an anti-active element, the operating point is determined by the input bias supplied from the power supply terminal 6 and the output bias supplied from the power supply terminal 20 via the input bias applying resistor 4, and its operation From the point, the signal corresponding to the phase from 180 ° to 360 ° of the input signal is amplified. On the other hand, in the NPN bipolar transistor 41 as an active element, an input bias supplied from the power supply terminal 7 through the input bias applying resistor 5 and an output bias supplied from the power supply terminal 20 through the PNP bipolar transistor 40 are used. An operating point is determined, and a signal corresponding to a phase from 0 ° to 180 ° of the input signal is amplified from the operating point.
[0080]
The signals amplified by the PNP bipolar transistor 40 and the NPN bipolar transistor 41 are output from the respective collectors, sent to the output terminal 17 through the DC blocking capacitor 16, and both are combined and output to the outside. The output sides of the PNP bipolar transistor 40 and the NPN bipolar transistor 41 are high impedance. The emitter of the NPN bipolar transistor 41 is grounded by the ground terminal 21, and the collector-emitter potentials of the PNP bipolar transistor 40 and the NPN bipolar transistor 41 are supplied from the power supply terminal 20. The supply of the output bias to the collectors of the PNP bipolar transistor 40 and the NPN bipolar transistor 41 is commonly performed at a single power supply terminal 20.
[0081]
As described above, according to the tenth embodiment, during the complementary push-pull amplification operation, the output side of the PNP bipolar transistor 40 and the NPN bipolar transistor 41 becomes high impedance, and an inductor for applying an output bias is not required. The effect that the circuit can be reduced in size can be obtained.
[0082]
In addition, since different bias voltages can be applied to the PNP bipolar transistor 40 and the NPN bipolar transistor 41, the effect that the adjustment of the bias point of each bipolar transistor can be realized.
[0083]
Further, since the power supply terminal 20 for supplying a bias to the collectors of the PNP bipolar transistor 40 and the NPN bipolar transistor 41 can be made common and a single power supply, the price can be reduced. Further, the collector of the NPN bipolar transistor 41 can be directly used as a power supply. Since the bias is supplied via the PNP bipolar transistor 40 without being connected, it is possible to achieve a multi-stage connection and to obtain a high gain.
[0084]
In this case as well, as in the case of the above embodiments, the input bias configuration is not limited to the configuration shown in FIG. 9, and an input / output matching circuit may be used.
[0085]
As described above, as the tenth embodiment, the case where the present invention is applied to the complementary push-pull amplifiers according to the first and second embodiments has been described. In addition, the complementary types according to the third to ninth embodiments described above are also used. It is also possible to apply to a push-pull amplifier, and there are the same effects as those of the embodiments.
[0086]
Embodiment 11 FIG.
10 is an explanatory view showing a complementary push-pull amplifier according to an eleventh embodiment of the present invention. The same reference numerals are given to the corresponding parts, and the description thereof is omitted. In the figure, reference numeral 42 denotes a single semiconductor substrate on which a pair of complementary elements formed of active elements and reactive elements are mounted. In the tenth embodiment, DC blocking capacitors 2 and 3, input bias applying resistors 4 and 5, DC forming an active element and an anti-active element of a complementary push-pull amplifier using a pair of complementary elements, The blocking capacitor 16, the P-type FET 18, and the N-type FET 19 are configured on the same semiconductor substrate 42.
[0087]
Since the operation is the same as that of the complementary push-pull amplifier according to the first embodiment of the present invention, the description thereof is omitted here.
[0088]
Thus, in the complementary push-pull amplifier according to the eleventh embodiment, in addition to the effect of the complementary push-pull amplifier according to the first embodiment, a pair of complementary elements are formed on the same semiconductor substrate 42. As a result, it is possible to achieve an effect that the price can be reduced and the entire circuit can be downsized.
[0089]
As described above, the case where the present invention is applied to the complementary push-pull amplifier according to the first embodiment has been described as the eleventh embodiment. However, the present invention is also applicable to the complementary push-pull amplifier according to the second to tenth embodiments. It is also possible to achieve the same effects as those of the respective embodiments.
[0090]
【The invention's effect】
  According to the present invention, the active element of a pair of complementary elements is composed of an N-type FET whose source is grounded, and the anti-active element is composed of a P-type FET whose source is connected to the power supply terminal. Ground, connect the source of the P-type FET to the power supply, connect the gate connection point of both to the input terminal via a capacitor, use the connection point of both drains as the output terminal, Since it is configured to give different voltages, adjustment of the bias point of each FET can be realized, and the power supply terminal for supplying a bias to the drains of the P-type FET and N-type FET can be made common and single power supply. In addition, the N-type FET drain is not directly connected to the power supply, but a bias is supplied via the P-type FET, enabling multi-stage connection. There is an effect that is obtained complementary push-pull amplifier capable of high gain of Te. In addition, since the bias point of the N-type FET and the P-type FET is set to class A or class AB, the output side of each FET becomes high impedance, and an inductor for applying an output bias is not required, so that the circuit can be reduced in size. There is an effect.In addition, since the characteristic adjusting element such as a characteristic adjusting inductor or a characteristic adjusting resistor is loaded between the source and the ground terminal of the N type FET, the gain of the N type FET can be reduced. Further, since the phase can be delayed, the characteristics of the N-type FET and the P-type FET can be aligned by adjusting this characteristic adjusting element, and as a result, the distortion characteristics can be improved. effective.
[0093]
According to the present invention, since the characteristic adjustment element is loaded between the gate and the input terminal of the N-type FET, the phase delay of the N-type FET or the gain reduction and the phase delay can be performed. Therefore, by adjusting this characteristic adjusting element, the characteristics of the N-type FET and the P-type FET can be made uniform, and the distortion characteristics can be improved.
[0094]
According to the present invention, since the characteristic adjusting resistor is used as the characteristic adjusting element, the gain of the N-type FET can be reduced and the phase can be delayed by adjusting the resistance value of the characteristic adjusting resistor. Thus, there is an effect that the characteristics of the N-type FET and the P-type FET can be aligned.
[0095]
According to the present invention, since the characteristic adjusting delay element is used as the characteristic adjusting element, the phase of the N-type FET can be delayed by adjusting the delay time of the characteristic adjusting delay element. There is an effect that the characteristics of the p-type FET and the p-type FET can be made uniform.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a first embodiment and a second embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a third embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a fourth embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a fifth embodiment of the present invention.
FIG. 5 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a sixth embodiment of the present invention.
FIG. 6 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a seventh embodiment of the present invention.
FIG. 7 is an equivalent circuit diagram showing a complementary push-pull amplifier according to an eighth embodiment of the present invention.
FIG. 8 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a ninth embodiment of the present invention.
FIG. 9 is an equivalent circuit diagram showing a complementary push-pull amplifier according to a tenth embodiment of the present invention.
FIG. 10 is an explanatory diagram showing a complementary push-pull amplifier according to an eleventh embodiment of the present invention.
FIG. 11 is an equivalent circuit diagram showing a conventional complementary push-pull amplifier.
[Explanation of symbols]
1 Input terminal, 2, 3, DC blocking capacitor, 2a, 2b, 3a, 3b DC blocking capacitor, 4,5 Input bias application resistor, 4a, 4b, 5a, 5b Input bias application resistor, 6, 7 Power supply terminal , 6a, 6b, 7a, 7b Power supply terminal, 16 DC blocking capacitor, 16a, 16b DC blocking capacitor, 17 output terminal, 18 P type FET, 18a, 18b P type FET, 19 N type FET, 19a, 19b N type FET , 20 power supply terminal, 21 ground terminal, 22 characteristic adjusting inductor (characteristic adjusting element), 23, 24 characteristic adjusting resistor (characteristic adjusting element), 25 characteristic adjusting delay element (characteristic adjusting element), 26 active element, 27 Anti-active element, 28 1st P-type FET, 29 1st N-type FET, 30 2nd N-type FET, 31 2nd P-type FET, 32 Active element, 33 Anti-active element, 34 1st P-type FET, 35 1st N-type FET, 36 2nd N-type FET, 37 2nd P-type FET, 38 3rd N-type FET, 39 1st 4. N-type FET, 40 PNP bipolar transistor, 41 NPN bipolar transistor, 42 Semiconductor substrate.

Claims (6)

In a complementary push-pull amplifier using a pair of complementary elements formed of an active element that amplifies a half-wave of a high-frequency input signal and an anti-active element that amplifies the remaining half-wave of the high-frequency input signal,
The active element is composed of an N-type FET, and the anti-active element is composed of a P-type FET.
A characteristic adjusting element for adjusting the characteristics of the N-type FET and the P-type FET is loaded between the source and the ground terminal of the N-type FET to adjust the gain and phase of the N-type FET, and the P-type Connect the source of the FET to the power supply,
The gate of the N-type FET and the gate of the P-type FET are each connected to the input terminal via a capacitor,
The drain of the N-type FET and the drain of the P-type FET are connected, the connection point is used as an output terminal, different bias voltages are applied to the gates of the N-type FET and the P-type FET, and the N-type FET and A complementary push-pull amplifier characterized in that the bias point of the P-type FET is class A or class AB. As characteristic adjustment device, a complementary push-pull amplifier according to claim 1, characterized by using the characteristic-adjusting inductor. As characteristic adjustment device, a complementary push-pull amplifier according to claim 1, characterized in that using the characteristic adjustment resistor. In a complementary push-pull amplifier using a pair of complementary elements formed of an active element that amplifies a half-wave of a high-frequency input signal and an anti-active element that amplifies the remaining half-wave of the high-frequency input signal,
The active element is composed of an N-type FET, and the anti-active element is composed of a P-type FET.
Grounding the source of the N-type FET and connecting the source of the P-type FET to a power source;
The gate of the N-type FET and the gate of the P-type FET are connected to an input terminal via a capacitor, respectively, and the phase or gain of the N-type FET is set between the gate and the input terminal of the N-type FET. Load the characteristic adjustment element that adjusts the phase and aligns the characteristics of the N-type FET and P-type FET,
The drain of the N-type FET and the drain of the P-type FET are connected, the connection point is used as an output terminal, different bias voltages are applied to the gates of the N-type FET and the P-type FET, and the N-type FET and A complementary push-pull amplifier characterized in that the bias point of the P-type FET is class A or class AB. 5. The complementary push-pull amplifier according to claim 4 , wherein a characteristic adjusting resistor is used as the characteristic adjusting element. 5. The complementary push-pull amplifier according to claim 4 , wherein a characteristic adjusting delay element is used as the characteristic adjusting element.

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