JPH0434980A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0434980A JPH0434980A JP2142155A JP14215590A JPH0434980A JP H0434980 A JPH0434980 A JP H0434980A JP 2142155 A JP2142155 A JP 2142155A JP 14215590 A JP14215590 A JP 14215590A JP H0434980 A JPH0434980 A JP H0434980A
- Authority
- JP
- Japan
- Prior art keywords
- region
- channel region
- soi
- mosfet
- body contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 16
- 238000002955 isolation Methods 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 19
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 25
- 239000010410 layer Substances 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000000969 carrier Substances 0.000 description 8
- 239000012535 impurity Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁体基板上の半導体層に形成されたＭ ＯＳ
（Ｍｅｔａｌ ０ｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔ
ｏｒ）型電界効果トランジスタ（以下、ｒｓｏ １−Ｍ
０３ＦＥＴＪと略称する）に関し、特に、ソース・ドレ
イン間の耐圧の改善に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS transistor formed in a semiconductor layer on an insulating substrate.
(Metal Oxide Sem1conduct
or) type field effect transistor (rso 1-M
03FETJ), in particular, it relates to improving the withstand voltage between the source and drain.
第５図は従来のＳｏ Ｉ−ＭＯＳＦＥＴの平面図、第６
図は従来のＳｏ Ｉ−ＭＯＳＦＥＴの断面図である。シ
リコン基板１上に絶縁体１１２が形成されており、絶縁
体層２上にシリコン層３が形成されている。シリコンＮ
３内において、低い、ｐ型不純物濃度（たとえば、１０
１に−１０”ａ ｔ ｏｍｓ／ｃＩａ）を有するチャン
ネル領域８が形成されており、高いｎ型不純物濃度（た
とえば１０Ｉ９−１０”ａ ｔ ｏｍｓ／ｃｊ）を有す
るソース領域９とドレイン領域１０がそれぞれチャネル
領域８の一方側と他方側に接して形成されている。Figure 5 is a plan view of a conventional So I-MOSFET, Figure 6 is a plan view of a conventional So I-MOSFET.
The figure is a cross-sectional view of a conventional So I-MOSFET. An insulator 112 is formed on a silicon substrate 1 , and a silicon layer 3 is formed on an insulator layer 2 . Silicon N
3, a low p-type impurity concentration (for example, 10
A channel region 8 having a high n-type impurity concentration (for example, 10I9-10"a toms/cj) is formed, and a source region 9 and a drain region 10 having a high n-type impurity concentration (for example, 10I9-10"a toms/cj) are formed. They are formed in contact with one side and the other side of the channel region 8.
チャネル領域８上にはゲート誘電体薄膜４が形成されて
おり、誘電体薄膜４上にゲート電極５が形成されている
。シリコン層３とゲート電極５は層間絶縁膜１２によっ
て覆われている。眉間絶縁膜１２にはコンタクトホール
１３が開けられ、コンタクトホールに対応する導電体１
４が形成されている。A gate dielectric thin film 4 is formed on the channel region 8 , and a gate electrode 5 is formed on the dielectric thin film 4 . Silicon layer 3 and gate electrode 5 are covered with interlayer insulating film 12 . A contact hole 13 is formed in the glabella insulating film 12, and a conductor 1 corresponding to the contact hole is formed.
4 is formed.
以上のように構成されたＳｏ Ｉ−ＭＯＳＦＥＴにおい
て、ゲート電極５に正の電圧を印加するとき、ｐ型のチ
ャネル領域８の上層部にｎ導電型のキャリア（電子）が
誘引され、その上層部はソース領域９およびドレイン領
域１０と同じｎ導電型に反転させられる。したがって、
ソース領域９とドレイン領域１０との間で電流が流れる
ことが可能となる。また、チャンネル領域８の上層部に
誘引されるｎ型キャリアの濃度はゲート電圧によって変
化するので、チャンネル領域８を流れる電流量をゲート
電圧によって制御することができる。In the So I-MOSFET configured as described above, when a positive voltage is applied to the gate electrode 5, n-conductivity type carriers (electrons) are attracted to the upper layer part of the p-type channel region 8, and the upper layer part is inverted to the same n conductivity type as the source region 9 and drain region 10. therefore,
Current can flow between source region 9 and drain region 10. Further, since the concentration of n-type carriers attracted to the upper layer of the channel region 8 changes depending on the gate voltage, the amount of current flowing through the channel region 8 can be controlled by the gate voltage.
これがＭＯＳＦＥＴの動作原理である。This is the operating principle of MOSFET.
シリコン層が比較的厚い（たとえば、約５０００人厚さ
）場合、ゲート電圧を印加してＳＯＩ−ＭＯＳ Ｆ Ｅ
Ｔを動作状態にするとき、チャンネル領域８内でキャリ
アが高速に加速される。チャンネル領域８内で加速され
たキャリアはドレイン領域１０の近傍で衝突電離によっ
て電子と正孔のペアを発生させる。この発生した電子は
ｎ＋型のドレイン領域１０に流れ込む、しかし、正孔は
チャネル領域８内に蓄積されて電位を上昇させるので、
チャネル電流を増加させ、ドレイン電圧とドレイン電流
の関係を表す曲線上に好ましくないキンク効果を生じさ
せる。このキンク効果は、たとえばアイ イー イー
イー エレクトロン デバイス レター 第９巻阻２．
９７−９９頁１９８８（ＩＥＥＥ Ｅｌｅｃｔｒｏｎ
Ｄｅｖｉｃｅ Ｌｅｔｔｅｒ、 Ｖｏｌ、９＋ Ｎｏ
、２＋ｐｐ、 ９７−９９．１９８８）において述べら
れている。If the silicon layer is relatively thick (e.g., approximately 5000 nm thick), applying a gate voltage will cause the SOI-MOS F E
When T is activated, carriers are accelerated within the channel region 8 at high speed. The carriers accelerated in the channel region 8 generate electron-hole pairs near the drain region 10 by collision ionization. These generated electrons flow into the n+ type drain region 10, but the holes are accumulated in the channel region 8 and increase the potential.
This increases the channel current and causes an undesirable kink effect on the drain voltage versus drain current curve. This kink effect, for example,
E-Electron Device Letter Volume 9 2.
pp. 97-99 1988 (IEEE Electron
Device Letter, Vol, 9+ No.
, 2+pp, 97-99.1988).
一方、非常に薄い（たとえば、５００人−１５００人の
厚さ）シリコン層３を有する薄膜ＳＯ■−ＭＯＳＦＥＴ
は、厚いシリコン層３を有する通常のＳｏＩ−ＭＯＳＦ
ＥＴに比べて優れた特性を有している。たとえば、その
薄いチャネル領域８はゲート電極５に電圧を印加するこ
とによって全体が空乏層化され、また電位もゲート電極
により制御されるため、電流がゲート電極５により制御
できないパンチスルー現象や、ゲート長が短いときにゲ
ートしきい値電圧が異常に低くなるショートチャンネル
効果が低減される。On the other hand, a thin film SO■-MOSFET with a very thin (e.g. 500-1500 nm thick) silicon layer 3
is a normal SoI-MOSF with a thick silicon layer 3
It has superior properties compared to ET. For example, the entire thin channel region 8 is made into a depletion layer by applying a voltage to the gate electrode 5, and the potential is also controlled by the gate electrode. The short channel effect, in which the gate threshold voltage becomes abnormally low when the length is short, is reduced.
しかし、チャンネル領域８全体が完全に空乏層化される
とき、チャンネル領域８内のボテンシャルが通常のＭＯ
Ｓ Ｆ ＥＴにおける場合より高くなる。したがって、
ソース領域９とチャンネル領域８の間の電気的障壁が低
くなる上、前述の衝突電離によって生じた正孔がチャン
ネル領域８内に一時的に蓄積されれば、チャンネル領域
８内のポテンシャルがさらに上昇し、ソース領域９から
チャン
ンネル領域目内に電子が急激に注入される。すなわち、
薄膜Ｓｏｌ−ＭＯＳＦＥＴにおいては、ソース・ドレイ
ン間の耐圧が低くなりやすいという問題がある。これは
第７図に示されている。ＳＯＩ層の厚い場合のキンク効
果及び薄い場合のソース・ドレイン間の耐圧の低下は共
にチャンネル領域が電気的に浮いている事（基板浮遊効
果という）が原因である。However, when the entire channel region 8 is completely depleted, the potential within the channel region 8 is
higher than in SFET. therefore,
In addition to lowering the electrical barrier between the source region 9 and the channel region 8, if the holes generated by the aforementioned impact ionization are temporarily accumulated in the channel region 8, the potential within the channel region 8 further increases. However, electrons are rapidly injected from the source region 9 into the channel region. That is,
Thin film Sol-MOSFETs have a problem in that the withstand voltage between the source and drain tends to be low. This is shown in FIG. The kink effect when the SOI layer is thick and the reduction in breakdown voltage between the source and drain when the SOI layer is thin are both caused by the fact that the channel region is electrically floating (referred to as the substrate floating effect).
以上のような従来の問題点に鑑み、本発明の目的は、基
板浮遊効果が改善されたＳＯＩ−ＭＯＳＦＥＴを提供す
ることにある。In view of the above conventional problems, an object of the present invention is to provide an SOI-MOSFET with improved substrate floating effect.
本発明にかかるＭＯＳ Ｆ ＥＴ半導体装置は、ＳＯＩ
−ＭＯＳＦＥＴの分離用に設けた絶縁膜を一部開口して
余剰キャリア引き抜き用のボディーコンタクトを設けた
ものである。The MOS FET semiconductor device according to the present invention is an SOI
- A part of the insulating film provided for MOSFET isolation is opened to provide a body contact for extracting excess carriers.
この発明における分離用絶縁膜に設けられたボディーコ
ンタクトはトランジスタのチャンネル領域で発生した余
剰キャリアがウェル領域を通ってボディーコンタクト部
より引き抜かれる。このため、基板浮遊効果によるＳ／
Ｄ耐圧の低下あるいはキンク効果の発生を抑えることが
できる。In the body contact provided in the isolation insulating film in this invention, surplus carriers generated in the channel region of the transistor are extracted from the body contact portion through the well region. Therefore, S/
D It is possible to suppress a decrease in breakdown voltage or the occurrence of a kink effect.
第１図は本発明の一実施例によるＳｏ １−ＭＯ５ＦＥ
Ｔの平面図、第２図は第１図のＸ−Ｘ断面図、第３図は
Ｙ−Ｙ断面図である。FIG. 1 shows a So 1-MO5FE according to an embodiment of the present invention.
2 is a sectional view taken along the line XX in FIG. 1, and FIG. 3 is a sectional view taken along the line YY in FIG.
本実施例においては、以下の点を除き、従来の半導体装
置と同様であるので同一番号を付し、その説明を省略す
る。ＳＯＩ−ＭＯＳＦＥＴの分離用として分離用絶縁膜
６を用いてあり、分離用絶縁膜６下には、チャネル領域
と同一導電型のＰ型の不純物が、例えば１０ ”〜１０
”ａｔｏｍ’ｓ ／ａＪ導入されたウェル領域１１が
形成されている。This embodiment is similar to the conventional semiconductor device except for the following points, so the same reference numerals are given and the explanation thereof will be omitted. An isolation insulating film 6 is used for isolation of the SOI-MOSFET, and under the isolation insulating film 6, a P-type impurity having the same conductivity type as the channel region is present, for example, 10" to 10".
A well region 11 into which "atom's/aJ" is introduced is formed.
また、分離用絶縁膜６の一部は開口されてボディコンタ
クト７を介してボディー用配線層１５が接続されている
。Further, a part of the isolation insulating film 6 is opened and connected to the body wiring layer 15 via the body contact 7.
次に動作について説明する。Next, the operation will be explained.
チャネル領域８とドレイン領域１０の境界の高電界領域
での衝突電離により発生した余剰キャリア、ここではＮ
ＭＯＳＦＥＴであるので正孔は、ゲート電極５下のチャ
ネル領域８を通って分離用絶縁膜６下のウェル領域１１
に流れる。ここで、ウェル領域１１はボディーコンタク
ト７を介してボディー用配線層１５が接続されているた
めここより糸外に引き抜かれる。Excess carriers generated by impact ionization in the high electric field region at the boundary between the channel region 8 and the drain region 10, here N
Since it is a MOSFET, the holes pass through the channel region 8 under the gate electrode 5 and reach the well region 11 under the isolation insulating film 6.
flows to Here, since the well region 11 is connected to the body wiring layer 15 via the body contact 7, it is pulled out from here.
したがって、チャネル領域８に正孔が蓄積する事が無く
なり、いわゆる、基板浮遊効果が低減される。Therefore, holes are not accumulated in the channel region 8, and the so-called substrate floating effect is reduced.
よってＳｏＩ−ＭＯＳＦＥＴのＳｏｌ膜厚が厚い時に見
られたＩｄ−Ｖｄ特性にくびれが生ずるキンク効果やＳ
ＯＩ膜厚が薄い時に見られた８７０間耐圧の低下が抑え
られ、第４図に示す様な優れたトランジスタ特性が得ら
れる。Therefore, the kink effect and S
The decrease in breakdown voltage between 870 and 870 that occurs when the OI film is thin is suppressed, and excellent transistor characteristics as shown in FIG. 4 are obtained.
また、ボディーコンタクト７は複数のトランジスタに共
通して設ければよく、面積の増加はほとんど必要としな
い。Further, the body contact 7 may be provided in common to a plurality of transistors, and there is almost no need for an increase in area.
なお、上記実施例ではＮＭＯＳＦＥＴについて述べたが
、ＰＭＯＳＦＥＴでも導電性が逆になるだけで、同様の
効果が得られる。Although NMOSFET was described in the above embodiment, the same effect can be obtained with PMOSFET only by having the conductivity reversed.
また、上記実施例では半導体層としてシリコン層を用い
たが、いずれの半導体材料を用いても同様の効果が得ら
れるのは言うまでもない。Further, although a silicon layer was used as the semiconductor layer in the above embodiment, it goes without saying that similar effects can be obtained using any semiconductor material.
以上のように、この発明によればＳｏ Ｉ −ＭＯＳＦ
ＥＴにおいてトランジスタの分離に分離用絶縁膜を用い
、さらに、分離用絶縁膜を貫通してウェル領域にボディ
ーコンタクトを設けたため、トランジスタのゲート電極
下のチャネル領域で発生した余剰キャリアを引き抜く事
が可能で基板浮遊効果によるキンク効果、８７０間耐圧
の低下に対してこれを改善できる効果がある。As described above, according to the present invention, So I-MOSF
In ET, an isolation insulating film is used to isolate transistors, and a body contact is provided in the well region by penetrating the isolation insulating film, making it possible to extract excess carriers generated in the channel region under the gate electrode of the transistor. This has the effect of improving the kink effect due to the substrate floating effect and the decrease in breakdown voltage between 870 and 870 mm.
第１図はこの発明の一実施例による半導体装置を示す平
面図、第２図は第１図のＸ−Ｘ断面図、第３図は第１図
のＹ−Ｙ断面図、第４図は本発明の一実施例による半導
体装置による薄膜ＳＯＩ−ＭＯＳ Ｆ ＥＴのＩｄ、−
Ｖｄ特性図、第５図は従来の半導体装置を示す平面図、
第６図は第５図のＡ−Ａ断面図、第７図は従来の薄膜Ｓ
ｏ Ｉ−ＭＯＳＦＥＴのＩｄ−Ｖｄ特性図である。
図において、１はシリコン基板、２は絶縁体層、３はシ
リコン層、４は誘電体薄膜、５はゲート電極、６は分離
用絶縁膜、７はボディーコンタクト、８はチャネル領域
、９はソース領域、１０はドレイン領域、１１はウェル
領域、１２は眉間絶縁膜、１０はドレイン領域、１１は
ウェル領域、１２は層間絶縁膜、１３はコンタクトホー
ル、１４は配線層、１５はボディー用配線層。
なお、図中、同一符号は同−又は相当部分を示す。FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line XX in FIG. 1, FIG. 3 is a cross-sectional view taken along the Y-Y line in FIG. 1, and FIG. Id, - of a thin film SOI-MOS FET as a semiconductor device according to an embodiment of the present invention
Vd characteristic diagram, FIG. 5 is a plan view showing a conventional semiconductor device,
Figure 6 is a sectional view taken along line A-A in Figure 5, and Figure 7 is a conventional thin film S.
o It is an Id-Vd characteristic diagram of I-MOSFET. In the figure, 1 is a silicon substrate, 2 is an insulator layer, 3 is a silicon layer, 4 is a dielectric thin film, 5 is a gate electrode, 6 is an isolation insulating film, 7 is a body contact, 8 is a channel region, and 9 is a source 10 is a drain region, 11 is a well region, 12 is an insulating film between eyebrows, 10 is a drain region, 11 is a well region, 12 is an interlayer insulating film, 13 is a contact hole, 14 is a wiring layer, 15 is a body wiring layer . In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
導体装置において、 絶縁体基板上に形成された半導体層と、 該半導体層上に設けられた、誘電体薄膜を挟んで形成さ
れたゲート電極と、 該ゲート電極下に設けられた第１導電型のチャネル領域
と、 前記ゲート電極下の前記チャネル領域を挟んで設けられ
た第２導電型のソース領域およびドレイン領域と、 前記半導体層に設けられた分離用絶縁膜と、該分離絶縁
膜下に設けられた第１導電型のウェル領域と、 前記分離絶縁膜を開口して設けられたボディーコンタク
トと、 該ボディーコンタクトに接続されたボディー用配線層と
を含む事を特徴とする半導体装置。(1) In a MOSFET semiconductor device formed on a semiconductor layer on an insulator, a semiconductor layer formed on an insulator substrate, and a gate electrode formed on the semiconductor layer with a dielectric thin film sandwiched therebetween. a channel region of a first conductivity type provided under the gate electrode; a source region and a drain region of a second conductivity type provided with the channel region under the gate electrode sandwiched therebetween; and a source region and a drain region of a second conductivity type provided in the semiconductor layer. a well region of a first conductivity type provided under the isolation insulating film; a body contact provided by opening the isolation insulating film; and a body contact connected to the body contact. 1. A semiconductor device comprising a wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2142155A JPH0434980A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2142155A JPH0434980A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0434980A true JPH0434980A (en) | 1992-02-05 |
Family
ID=15308643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2142155A Pending JPH0434980A (en) | 1990-05-30 | 1990-05-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434980A (en) |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877978A (en) * | 1996-03-04 | 1999-03-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
| US5929476A (en) * | 1996-06-21 | 1999-07-27 | Prall; Kirk | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
| KR100224664B1 (en) * | 1996-11-20 | 1999-10-15 | 윤종용 | Soi transistor and the manufacturing method thereof |
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| US6933569B2 (en) | 2002-12-06 | 2005-08-23 | Nec Corporation | Soi mosfet |
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| JP2007005780A (en) * | 2005-05-26 | 2007-01-11 | Semiconductor Energy Lab Co Ltd | Semiconductor device and method of manufacturing the same |
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-
1990
- 1990-05-30 JP JP2142155A patent/JPH0434980A/en active Pending
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| US6081443A (en) * | 1996-03-04 | 2000-06-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
| KR100299750B1 (en) * | 1996-03-04 | 2001-11-30 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor storage device |
| US5877978A (en) * | 1996-03-04 | 1999-03-02 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device |
| US6586304B2 (en) | 1996-06-21 | 2003-07-01 | Micron Technology, Inc. | Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors |
| US5929476A (en) * | 1996-06-21 | 1999-07-27 | Prall; Kirk | Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors |
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| US9608619B2 (en) | 2005-07-11 | 2017-03-28 | Peregrine Semiconductor Corporation | Method and apparatus improving gate oxide reliability by controlling accumulated charge |
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| US9660590B2 (en) | 2008-07-18 | 2017-05-23 | Peregrine Semiconductor Corporation | Low-noise high efficiency bias generation circuits and method |
| US9831857B2 (en) | 2015-03-11 | 2017-11-28 | Peregrine Semiconductor Corporation | Power splitter with programmable output phase shift |
| US9948281B2 (en) | 2016-09-02 | 2018-04-17 | Peregrine Semiconductor Corporation | Positive logic digitally tunable capacitor |
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| US10236872B1 (en) | 2018-03-28 | 2019-03-19 | Psemi Corporation | AC coupling modules for bias ladders |
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