KR20070009750A - Serial sampling capacitor and analog to digital converter using it - Google Patents

Abstract

A serial sampling capacitor and an ADC(Analog to Digital Converter) using the same are provided to prevent a malfunction of the ADC by lowering an impedance of a serial sampling capacitor. A serial sampling capacitor structure includes two serial capacitors(C1,C2), and a transistor(M1). The serial sampling capacitor structure is used to design an ADC. The transistor(M1) is located between a common mode voltage and a middle node between two serial capacitors(C1,C2). The transistor(M1) performs a switch function. The serial sampling capacitor structure resets a voltage of the middle node into the common mode voltage by operating a reset clock before two serial capacitors(C1,C2) perform sampling. The reset clock is partially overlapped with a sampling clock. The serial sampling capacitor structure prevents a malfunction of the ADC by lowering an impedance of a serial sampling capacitor.

Description

Serial sampling capacitor and analog to digital converter using it}

1 illustrates two capacitors in a common common centroid manner.

 2A illustrates a case in which unit capacitors C1 to C4 are connected in parallel, and FIG. 2B illustrates a case in which unit capacitors C1 to C4 are connected in series.

3 is a circuit in which two sampling capacitors are connected in series in an MDAC circuit having a gain of 2V / V.

Figure 4 shows an embodiment of a series sampling capacitor according to the present invention.

FIG. 5 simulates a voltage change at an intermediate node in the configuration as shown in FIG. 4.

6 illustrates one embodiment of an analog-to-digital converter using a series sampling capacitor.

FIG. 7 illustrates a FFT (Fast-Fourier Transform) of a digital signal lamp output from an ADC.

The present invention relates to an analog / digital converter, and more particularly, to a sampling capacitor structure of an ADC and an analog / digital converter using the same.

Analog-to-digital converters (ADCs) are circuits for converting and converting input analog signals into digital signals and are essential in various data communication and signal processing systems.

The specifications required for the ADC vary depending on the system being applied. In recent years, as wireless communication and portable equipment are developed, satisfying the signal performance of the system and minimizing power consumption is of the utmost importance. It became matter.

In general, the most power-consuming part of the ADC is op-amps related to various sampling, for example, pipelined analog-to-digital converters suitable for realizing high sampling rates. In the case of (ADC), op-amps in a multiplying digital-to-analog converter (MDAC) correspond to this.

In order to reduce the power consumption of circuits such as MDAC, the proposed method has to share the required operational amplifiers according to the clock or optimize the number of stages required and the resolution required for each stage. Rather than reducing the power of the op amp itself, it reduces power consumption by reducing the number of op amps needed across the ADC.

The power consumption of each op-amp depends on the performance required by the MDAC with the op amp. One of the decisive factors for implementing this performance is the sampling capacitor.

In ADCs, the value of the sampling capacitor depends on the mismatch between each capacitor, kT / C noise, charge leakage, and linearity, the most important of which is mismatch and kT / C noise.

When implementing an ADC that requires high resolution near 10 bits in a standard digital CMOS process, it is necessary to implement a capacitor of a certain size to prevent performance degradation due to mismatch. op-amp) power consumption. In particular, the required capacitor value is often larger than the size of the capacitor to satisfy the kT / C noise.

(W는 커패시터의 면적, a는 공정에 좌우되는 상수이다.)로 나타낼 수 있다.For example, in a typical process capacitor mismatch is a function of area

(W is the area of the capacitor, a is a constant depending on the process).

Here, when implementing a 10-bit pipeline ADC consisting of 1.5 bits per stage, 3σ of the capacitor mismatch in the first stage should be less than 2-10.

인 공정에서 커패시터의 크기는

이고, 커패시터 밀도(density)가

라면, 이는 3.6pF의 커패시턴스(capacitance)를 나타내게 되어, kT/C 잡음에 의해 요구되는 1pF의 커패시턴스(capacitance)보다 훨씬 큰 값을 가지게 된다.in this case

In the process, the size of the capacitor

Where the capacitor density is

In this case, it represents a capacitance of 3.6 pF, which is much larger than the capacitance of 1 pF required by kT / C noise.

Therefore, if the power consumption of the op-amp increases in proportion to the capacitance value, the power dissipation increases by more than 70% due to capacitor mismatch.

One common layout method for reducing capacitor mismatch is a common centroid method in which capacitors are divided into unit capacitors and arranged in alternation.

1 illustrates two capacitors in a common common centroid.

Unit capacitors C1 and C4 configure one capacitor to form another capacitor, C2 and C3 to minimize mismatch between the two capacitors from the first process gradient. In this case, it is common to connect C1 and C4 and C2 and C3 in parallel.

2A illustrates a case where unit capacitors C1 to C4 are connected in parallel, and FIG. 2B illustrates a case where unit capacitors C1 to C4 are connected in series.

Comparing FIG. 2A and FIG. 2B, the layout of the same unit capacitor is used to layout, while the effects of mismatch are the same, while the capacitance of CsA and CsB connected in series is the capacitance of CpA and CpB connected in parallel. 1/4 of.

This result is intuitive because it is the difference between connecting the same unit capacitors in series and in parallel. However, this can also be confirmed by the following mathematical model.

라고 표현할 수 있다. 이 때

는 랜덤 에러(random error)로서 0의 평균과

의 표준 변차(standard deviation)를 가지는 표준정규분포(standard normal distribution)를 따른다고 하자(

). 이 때 병렬 연결에 의한 커패시터 CpA와 CpB의 커패시턴스 불일치(mismatch)와 직렬 연결에 의한 커패시터 CsA와 CsB의 커패시턴스 불일치(mismatch)는 다음과 같이 나타낼 수 있다.The capacitance of each capacitor C1 ~ C4

Can be expressed. At this time

Is a random error that is the average of zero

Suppose that the standard normal distribution has a standard deviation of

). At this time, the capacitance mismatch between the capacitors CpA and CpB due to the parallel connection and the capacitance mismatch between the capacitors CsA and CsB due to the series connection can be expressed as follows.

와

는 동일하게

분포를 따르므로 결국 두 커패시터들은 커패시턴스는 4배의 차이를 가지면서 동일한 정합(matching) 특성을 보임을 확인할 수 있다.here

Wow

Equally

As a result of the distribution, the two capacitors show four times the capacitance and the same matching characteristic.

Now, let's look at how the two capacitors are connected in series and the sampling capacitor is different from the case of using one capacitor.

3 is a circuit in which two sampling capacitors are connected in series in an MDAC circuit having a gain of 2V / V.

In the aforementioned manner, when there is a random error, the voltage transfer function of the MDAC may be implemented as follows.

. In order for the MDAC circuit with one sampling capacitor and the above MDAC circuit to have the same signal characteristics, the values of the sampling capacitors of the two cases must be identical. Become large

.

배 줄어들게 되며, 만일 n개의 단위 커패시터들을 직렬 연결하여 똑같은 샘플링 커패시터를 구성할 시에는

배 줄어들게 된다. 그리고 MDAC과 같은 회로에 직렬 샘플링 커패시터를 적절히 이용할 경우, 커패시터 불일치(mismatch)에 의해 요구되 는 커패시턴스 보다 매우 낮은 샘플링 커패시턴스를 구현할 수 있게 되어(kT/C 잡음이 요구하는 샘플링 커패시턴스보다도 낮게 구현이 가능하다) 저전력 ADC 설계를 용이하게 한다.Thus, mismatches in series sampling capacitors are

If you configure the same sampling capacitor by connecting n unit capacitors in series,

Will be reduced. In addition, the proper use of series sampling capacitors in circuits such as MDAC allows for a much lower sampling capacitance than the capacitance required by capacitor mismatch (lower than the sampling capacitance required by kT / C noise). Facilitates low-power ADC design

There are some difficulties in implementing a series sampling capacitor in an actual circuit, and most importantly, when unit capacitors are connected in series, intermediate nodes connected between unit capacitors have high impedance. Furthermore, in practice, antenna rules are often applied to reverse the diode across the capacitor. Therefore, during the MDAC operation, the intermediate nodes of the unit capacitors may bootstrap due to high impedance, which causes the ADC to malfunction by turning on the reverse diode.

SUMMARY OF THE INVENTION The present invention provides a series sampling capacitor structure and an analog / digital converter using the same to reduce the impedance of a capacitor connected in series and to prevent malfunction of the analog / digital converter.

The series sampling capacitor structure according to the present invention for solving the above technical problem is a series sampling capacitor structure used to design an analog-to-digital converter, two series capacitors (C1, C2); And a transistor M1 disposed between an intermediate node X between the two series capacitors C1 and C2 and a common mode voltage, and serving as a switch. The two series capacitors C1 are included. The C2) operates a reset clock just before sampling to reset the voltage of the intermediate node X to a common mode voltage.

An analog / digital converter using a series sampling capacitor according to the present invention for solving the technical problem is a sample & hold circuit; Comprising a transistor (M1) located between the intermediate node (X) between the two series capacitor (C1, C2) and the common mode voltage (common mode voltage) and acts as a switch, the two series capacitor (C1, C2) A plurality of stages provided with a series sampling capacitor having a function of operating a reset clock just before sampling to reset the voltage of the intermediate node X to a common mode voltage; Flash ADCs; And a digital error correction circuit for correcting errors of the plurality of stages and the flash ADC.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Figure 4 shows an embodiment of a series sampling capacitor according to the present invention.

A switch using transistor M1 was connected between the middle node X of the two series capacitors C1 and C2 and the common mode voltage V _CM , and the reset clock was operated just before the sampling capacitors sampled. The voltage of the intermediate node is reset to the common mode voltage.

In practice, the reset clock may be configured to slightly overlap with the sampling clock as shown on the right side of FIG. However, this clock configuration does not attenuate the ADC's overall performance because the settling time of the sampling capacitor's input voltage depends on the settling time of the op-amp.

FIG. 5 simulates a voltage change at an intermediate node in the configuration as shown in FIG. 4.

As shown in FIG. 5, after a short time, the intermediate node voltage reaches the desired common mode voltage.

FIG. 6 illustrates an embodiment of an analog-to-digital converter using a serial sampling capacitor, and includes a sample & hold circuit 610, a plurality of stages 620, a flash ADC 630, and a digital error correction circuit 640. .

Designed 100MHz 10bit pipeline ADC using 0.18㎛ CMOS process, Flash ADC 630 consisting of 7 1.5bit / stage 620 and 3bit, Sample & Hold (S / H) circuit 610, Digital It consists of an error correction (Digital Error Correction) circuit 640.

The sample & hold circuit 610 samples an input analog signal according to a clock frequency and then holds the signal until a clock is applied.

The plurality of stages 620 may vary in the number of stages and the number of bits that each stage needs to process according to specifications required by the pipeline ADC.

Each of the stages 620 includes a MDAC, which is operated by a clock transmission method called a pipeline method and consists of series sampling capacitors.

Flash ADC 630 is a suitable ADC to handle small bits at high speed. Pipeline ADCs process several bits of signals that need to be processed eventually.

The digital error correction circuit 640 adds up the respective digital signals received through the plurality of stages 620 and the flash ADC 630 to correct errors that may occur at each stage when the digital signal is finally completed.

FIG. 7 illustrates a FFT (Fast-Fourier Transform) of a digital signal lamp output from an ADC.

Simulation results show excellent signal characteristics with 60 dB of Signal to Noise and Distortion Ratio (SNDR) and 67 dB of Spurious Free Dynamic Range (SFDR) with 9.5 bits of effective number of bits (ENOB) at 100 MHz. In addition, the power dissipation consumes only 26µs at 1.8V, consuming less power than other ADCs with the same specifications.

As described above, the present invention has been described with reference to the embodiments illustrated in the drawings, which are merely exemplary, and it should be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention, the malfunction of the analog-to-digital converter can be prevented by lowering the impedance of the series sampling capacitor.

Claims (3)

In the series sampling capacitor structure used to design the analog to digital converter, Two series capacitors C1 and C2; And And a transistor (M1) positioned between an intermediate node (X) between the two series capacitors (C1, C2) and a common mode voltage and serving as a switch. The two series capacitors C1 and C2 operate a reset clock just before sampling to reset the voltage of the intermediate node X to a common mode voltage. Series sampling capacitor structure. The method of claim 1, wherein the reset clock is A series sampling capacitor structure characterized in that a predetermined portion overlaps a sampling clock. In the analog-to-digital converter, A sample / hold circuit for sampling the input analog signal according to a clock frequency and then holding the signal until a clock is applied; Comprising a transistor (M1) located between the intermediate node (X) between the two series capacitor (C1, C2) and the common mode voltage (common mode voltage) and acts as a switch, the two series capacitor (C1, C2) A plurality of stages having a series sampling capacitor structure having a function of operating a reset clock just before sampling to reset the voltage of the intermediate node X to a common mode voltage; A flash ADC connected to the last stage of the plurality of stages to process several bits of signals to be finally processed; And And a digital error correction circuit for correcting errors of the plurality of stages and the flash ADC.

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