JP5532400B2 - スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法 - Google Patents

スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法 Download PDF

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JP5532400B2
JP5532400B2 JP2009526863A JP2009526863A JP5532400B2 JP 5532400 B2 JP5532400 B2 JP 5532400B2 JP 2009526863 A JP2009526863 A JP 2009526863A JP 2009526863 A JP2009526863 A JP 2009526863A JP 5532400 B2 JP5532400 B2 JP 5532400B2
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mask
forming
active device
contact
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JP2010503218A5 (https=
JP2010503218A (ja
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ケー． リー，ジョン
キム，ヒュンテ
エル． ストックス，リチャード
シー． トラン，ルアン
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マイクロン テクノロジー， インク．
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2009526863A 2006-08-29 2007-08-28 スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法 Active JP5532400B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/511,541 US7960797B2 (en) 2006-08-29 2006-08-29 Semiconductor devices including fine pitch arrays with staggered contacts
US11/511,541 2006-08-29
PCT/US2007/076970 WO2008027876A2 (en) 2006-08-29 2007-08-28 Semiconductor devices including fine pitch arrays with staggered contacts and methods for designing and fabricating the same

Publications (3)

Publication Number Publication Date
JP2010503218A JP2010503218A (ja) 2010-01-28
JP2010503218A5 JP2010503218A5 (https=) 2012-12-06
JP5532400B2 true JP5532400B2 (ja) 2014-06-25

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JP2009526863A Active JP5532400B2 (ja) 2006-08-29 2007-08-28 スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法

Country Status (7)

Country Link
US (2) US7960797B2 (https=)
EP (1) EP2057676B1 (https=)
JP (1) JP5532400B2 (https=)
KR (1) KR101173723B1 (https=)
CN (1) CN101506967B (https=)
TW (1) TWI369756B (https=)
WO (1) WO2008027876A2 (https=)

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JP2012199381A (ja) * 2011-03-22 2012-10-18 Toshiba Corp 半導体装置およびその製造方法
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CN109983564B (zh) * 2016-11-16 2023-05-02 东京毅力科创株式会社 亚分辨率衬底图案化的方法
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CN108735711B (zh) * 2017-04-13 2021-04-23 中芯国际集成电路制造(北京)有限公司 一种半导体器件及其制备方法、电子装置
US10361158B2 (en) * 2017-08-29 2019-07-23 Micron Technology, Inc. Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch
US10559492B2 (en) * 2017-11-15 2020-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning methods for semiconductor devices and structures resulting therefrom
KR102665246B1 (ko) 2018-07-03 2024-05-09 삼성전자주식회사 반도체 장치 및 이의 제조 방법
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Also Published As

Publication number Publication date
US8367482B2 (en) 2013-02-05
TW200822285A (en) 2008-05-16
KR20090057052A (ko) 2009-06-03
EP2057676B1 (en) 2019-11-06
WO2008027876A2 (en) 2008-03-06
US20110223761A1 (en) 2011-09-15
US20080054483A1 (en) 2008-03-06
US7960797B2 (en) 2011-06-14
CN101506967A (zh) 2009-08-12
EP2057676A2 (en) 2009-05-13
KR101173723B1 (ko) 2012-08-13
CN101506967B (zh) 2013-03-13
WO2008027876A3 (en) 2008-06-19
JP2010503218A (ja) 2010-01-28
TWI369756B (en) 2012-08-01

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