JP2010503218A5 - - Google Patents
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- Publication number
- JP2010503218A5 JP2010503218A5 JP2009526863A JP2009526863A JP2010503218A5 JP 2010503218 A5 JP2010503218 A5 JP 2010503218A5 JP 2009526863 A JP2009526863 A JP 2009526863A JP 2009526863 A JP2009526863 A JP 2009526863A JP 2010503218 A5 JP2010503218 A5 JP 2010503218A5
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- trenches
- aperture
- semiconductor device
- device structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/511,541 US7960797B2 (en) | 2006-08-29 | 2006-08-29 | Semiconductor devices including fine pitch arrays with staggered contacts |
| US11/511,541 | 2006-08-29 | ||
| PCT/US2007/076970 WO2008027876A2 (en) | 2006-08-29 | 2007-08-28 | Semiconductor devices including fine pitch arrays with staggered contacts and methods for designing and fabricating the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010503218A JP2010503218A (ja) | 2010-01-28 |
| JP2010503218A5 true JP2010503218A5 (https=) | 2012-12-06 |
| JP5532400B2 JP5532400B2 (ja) | 2014-06-25 |
Family
ID=39136779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009526863A Active JP5532400B2 (ja) | 2006-08-29 | 2007-08-28 | スタガードコンタクトを持つファインピッチアレイを含む半導体デバイスと、その設計および製造のための方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7960797B2 (https=) |
| EP (1) | EP2057676B1 (https=) |
| JP (1) | JP5532400B2 (https=) |
| KR (1) | KR101173723B1 (https=) |
| CN (1) | CN101506967B (https=) |
| TW (1) | TWI369756B (https=) |
| WO (1) | WO2008027876A2 (https=) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100833201B1 (ko) * | 2007-06-15 | 2008-05-28 | 삼성전자주식회사 | 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법 |
| JP2007103410A (ja) * | 2005-09-30 | 2007-04-19 | Elpida Memory Inc | 密集コンタクトホールを有する半導体デバイス |
| KR100834267B1 (ko) * | 2007-05-07 | 2008-05-30 | 주식회사 하이닉스반도체 | 노광 마스크 및 이를 이용한 반도체 소자의 콘택홀 제조방법 |
| US7939451B2 (en) * | 2007-06-07 | 2011-05-10 | Macronix International Co., Ltd. | Method for fabricating a pattern |
| US8481417B2 (en) | 2007-08-03 | 2013-07-09 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts and methods to form same |
| US8283258B2 (en) * | 2007-08-16 | 2012-10-09 | Micron Technology, Inc. | Selective wet etching of hafnium aluminum oxide films |
| US8062971B2 (en) * | 2008-03-19 | 2011-11-22 | Infineon Technologies Ag | Dual damascene process |
| KR101409840B1 (ko) * | 2008-06-04 | 2014-06-20 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
| US8058732B2 (en) * | 2008-11-20 | 2011-11-15 | Fairchild Semiconductor Corporation | Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same |
| US8541311B2 (en) * | 2010-12-22 | 2013-09-24 | GlobalFoundries, Inc. | Integrated circuit fabrication methods utilizing embedded hardmask layers for high resolution patterning |
| JP2012199381A (ja) * | 2011-03-22 | 2012-10-18 | Toshiba Corp | 半導体装置およびその製造方法 |
| US8586478B2 (en) * | 2011-03-28 | 2013-11-19 | Renesas Electronics Corporation | Method of making a semiconductor device |
| US9536952B2 (en) | 2014-05-12 | 2017-01-03 | Intersil Americas LLC | Body contact layouts for semiconductor structures |
| CN109983564B (zh) * | 2016-11-16 | 2023-05-02 | 东京毅力科创株式会社 | 亚分辨率衬底图案化的方法 |
| JP6939497B2 (ja) * | 2017-12-13 | 2021-09-22 | 富士電機株式会社 | 抵抗素子 |
| CN108735711B (zh) * | 2017-04-13 | 2021-04-23 | 中芯国际集成电路制造(北京)有限公司 | 一种半导体器件及其制备方法、电子装置 |
| US10361158B2 (en) * | 2017-08-29 | 2019-07-23 | Micron Technology, Inc. | Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch |
| US10559492B2 (en) * | 2017-11-15 | 2020-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Patterning methods for semiconductor devices and structures resulting therefrom |
| KR102665246B1 (ko) | 2018-07-03 | 2024-05-09 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
| US10777562B1 (en) * | 2019-03-14 | 2020-09-15 | Micron Technology, Inc. | Integrated circuity, DRAM circuitry, methods used in forming integrated circuitry, and methods used in forming DRAM circuitry |
| US11217594B2 (en) * | 2019-09-05 | 2022-01-04 | Nanya Technology Corporation | Semiconductor device and method for fabricating the same |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4267632A (en) * | 1979-10-19 | 1981-05-19 | Intel Corporation | Process for fabricating a high density electrically programmable memory array |
| EP0912996B1 (en) | 1996-07-18 | 2002-01-02 | Advanced Micro Devices, Inc. | Integrated circuit which uses an etch stop for producing staggered interconnect lines |
| KR100506101B1 (ko) * | 1996-11-14 | 2006-04-21 | 텍사스 인스트루먼츠 인코포레이티드 | 메모리 셀 어레이 제조방법 및 메모리 셀 어레이 |
| US6016000A (en) * | 1998-04-22 | 2000-01-18 | Cvc, Inc. | Ultra high-speed chip semiconductor integrated circuit interconnect structure and fabrication method using free-space dielectrics |
| FR2786609B1 (fr) | 1998-11-26 | 2003-10-17 | St Microelectronics Sa | Circuit integre a capacite interlignes reduite et procede de fabrication associe |
| CN1184682C (zh) * | 1999-03-03 | 2005-01-12 | 株式会社日立制作所 | 半导体集成电路器件及其制造方法 |
| JP2002289815A (ja) | 2001-03-23 | 2002-10-04 | Hitachi Ltd | 半導体記憶装置 |
| JP4911838B2 (ja) * | 2001-07-06 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| KR100450671B1 (ko) * | 2002-02-26 | 2004-10-01 | 삼성전자주식회사 | 스토리지 노드 콘택플러그를 갖는 반도체 소자의 제조방법 |
| KR100502410B1 (ko) * | 2002-07-08 | 2005-07-19 | 삼성전자주식회사 | 디램 셀들 |
| KR100448899B1 (ko) * | 2002-08-20 | 2004-09-16 | 삼성전자주식회사 | 상변환 기억 소자 |
| JP2004228308A (ja) * | 2003-01-22 | 2004-08-12 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| KR100532424B1 (ko) | 2003-03-18 | 2005-11-30 | 삼성전자주식회사 | 반도체 메모리 장치 및 그 제조방법 |
| US7115993B2 (en) * | 2004-01-30 | 2006-10-03 | Tokyo Electron Limited | Structure comprising amorphous carbon film and method of forming thereof |
| KR100672816B1 (ko) * | 2004-03-16 | 2007-01-22 | 삼성전자주식회사 | 반도체 메모리 장치의 캐패시터 형성방법 |
| JP5172069B2 (ja) * | 2004-04-27 | 2013-03-27 | 富士通セミコンダクター株式会社 | 半導体装置 |
| US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
| US7638878B2 (en) * | 2006-04-13 | 2009-12-29 | Micron Technology, Inc. | Devices and systems including the bit lines and bit line contacts |
-
2006
- 2006-08-29 US US11/511,541 patent/US7960797B2/en active Active
-
2007
- 2007-08-28 KR KR1020097006151A patent/KR101173723B1/ko active Active
- 2007-08-28 WO PCT/US2007/076970 patent/WO2008027876A2/en not_active Ceased
- 2007-08-28 EP EP07841450.5A patent/EP2057676B1/en active Active
- 2007-08-28 CN CN2007800316680A patent/CN101506967B/zh active Active
- 2007-08-28 JP JP2009526863A patent/JP5532400B2/ja active Active
- 2007-08-29 TW TW096132106A patent/TWI369756B/zh active
-
2011
- 2011-05-23 US US13/113,468 patent/US8367482B2/en active Active
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