JP5500798B2 - Ｓｏｉ基板の作製方法及び半導体装置の作製方法 - Google Patents

Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Download PDF

Info

Publication number
JP5500798B2
JP5500798B2 JP2008201449A JP2008201449A JP5500798B2 JP 5500798 B2 JP5500798 B2 JP 5500798B2 JP 2008201449 A JP2008201449 A JP 2008201449A JP 2008201449 A JP2008201449 A JP 2008201449A JP 5500798 B2 JP5500798 B2 JP 5500798B2
Authority
JP
Japan
Prior art keywords
single crystal
substrate
crystal semiconductor
film
seed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008201449A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009065134A (ja
JP2009065134A5 (https=
Inventor
智昭 森若
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008201449A priority Critical patent/JP5500798B2/ja
Publication of JP2009065134A publication Critical patent/JP2009065134A/ja
Publication of JP2009065134A5 publication Critical patent/JP2009065134A5/ja
Application granted granted Critical
Publication of JP5500798B2 publication Critical patent/JP5500798B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
JP2008201449A 2007-08-10 2008-08-05 Ｓｏｉ基板の作製方法及び半導体装置の作製方法 Expired - Fee Related JP5500798B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008201449A JP5500798B2 (ja) 2007-08-10 2008-08-05 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007208932 2007-08-10
JP2007208932 2007-08-10
JP2008201449A JP5500798B2 (ja) 2007-08-10 2008-08-05 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Publications (3)

Publication Number Publication Date
JP2009065134A JP2009065134A (ja) 2009-03-26
JP2009065134A5 JP2009065134A5 (https=) 2011-09-15
JP5500798B2 true JP5500798B2 (ja) 2014-05-21

Family

ID=40346931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008201449A Expired - Fee Related JP5500798B2 (ja) 2007-08-10 2008-08-05 Ｓｏｉ基板の作製方法及び半導体装置の作製方法

Country Status (3)

Country Link
US (2) US7795114B2 (https=)
JP (1) JP5500798B2 (https=)
KR (1) KR101456564B1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8314009B2 (en) * 2007-09-14 2012-11-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
JP5654206B2 (ja) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法及び該ｓｏｉ基板を用いた半導体装置
US8048754B2 (en) * 2008-09-29 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing single crystal semiconductor layer
JP5611571B2 (ja) * 2008-11-27 2014-10-22 株式会社半導体エネルギー研究所 半導体基板の作製方法及び半導体装置の作製方法
JP5607399B2 (ja) * 2009-03-24 2014-10-15 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5593107B2 (ja) * 2009-04-02 2014-09-17 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP5866088B2 (ja) * 2009-11-24 2016-02-17 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5755931B2 (ja) 2010-04-28 2015-07-29 株式会社半導体エネルギー研究所 半導体膜の作製方法、電極の作製方法、２次電池の作製方法、および太陽電池の作製方法
US8896964B1 (en) 2013-05-16 2014-11-25 Seagate Technology Llc Enlarged substrate for magnetic recording medium

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6461943A (en) 1987-09-02 1989-03-08 Seiko Epson Corp Semiconductor device and manufacture thereof
JPH0618926A (ja) 1992-07-02 1994-01-28 Sharp Corp 液晶表示用大型基板およびその製造方法
US6534409B1 (en) * 1996-12-04 2003-03-18 Micron Technology, Inc. Silicon oxide co-deposition/etching process
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2000012864A (ja) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2000124092A (ja) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd 水素イオン注入剥離法によってｓｏｉウエーハを製造する方法およびこの方法で製造されたｓｏｉウエーハ
JP2003031779A (ja) * 2001-07-13 2003-01-31 Mitsubishi Electric Corp Ｓｏｉウェハの製造方法
JP3785067B2 (ja) 2001-08-22 2006-06-14 株式会社東芝 半導体素子の製造方法
JP4772258B2 (ja) * 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4103447B2 (ja) 2002-04-30 2008-06-18 株式会社Ｉｈｉ 大面積単結晶シリコン基板の製造方法
JP2004025360A (ja) 2002-06-25 2004-01-29 Nakamura Tome Precision Ind Co Ltd 微細作業用３次元動作機構
US6818529B2 (en) * 2002-09-12 2004-11-16 Applied Materials, Inc. Apparatus and method for forming a silicon film across the surface of a glass substrate
JP2004134675A (ja) 2002-10-11 2004-04-30 Sharp Corp Ｓｏｉ基板、表示装置およびｓｏｉ基板の製造方法
US7508034B2 (en) * 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
FR2855909B1 (fr) * 2003-06-06 2005-08-26 Soitec Silicon On Insulator Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat
US7199397B2 (en) * 2004-05-05 2007-04-03 Au Optronics Corporation AMOLED circuit layout
JP3998677B2 (ja) * 2004-10-19 2007-10-31 株式会社東芝 半導体ウェハの製造方法
US7691730B2 (en) 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
US7456080B2 (en) * 2005-12-19 2008-11-25 Corning Incorporated Semiconductor on glass insulator made using improved ion implantation process
US7608521B2 (en) * 2006-05-31 2009-10-27 Corning Incorporated Producing SOI structure using high-purity ion shower
EP1978554A3 (en) * 2007-04-06 2011-10-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate comprising implantation and separation steps

Also Published As

Publication number Publication date
US20090042362A1 (en) 2009-02-12
US7795114B2 (en) 2010-09-14
KR20090016391A (ko) 2009-02-13
JP2009065134A (ja) 2009-03-26
US7994023B2 (en) 2011-08-09
US20110008946A1 (en) 2011-01-13
KR101456564B1 (ko) 2014-10-31

Similar Documents

Publication Publication Date Title
JP5500798B2 (ja) Ｓｏｉ基板の作製方法及び半導体装置の作製方法
CN101504930B (zh) Soi衬底的制造方法
JP5503866B2 (ja) Ｓｏｉ基板の作製方法
KR101400699B1 (ko) 반도체 기판 및 반도체 장치 및 그 제조 방법
KR101561855B1 (ko) Ｓｏｉ기판의 제작방법
JP5438919B2 (ja) 半導体装置製造用基板の作製方法
JP4574721B2 (ja) Ｓｏｉ基板及びその作製方法並びに半導体装置及びその作製方法
JP5486781B2 (ja) 半導体装置の作製方法
JP5459900B2 (ja) 半導体装置の作製方法
JP5386193B2 (ja) Ｓｏｉ基板の作製方法
JP5201967B2 (ja) 半導体基板の作製方法および半導体装置の作製方法
US20090223628A1 (en) Manufacturing apparatus of composite substrate and manufacturing method of composite substrate with use of the manufacturing apparatus

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20110617

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20110617

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110801

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110801

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130730

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130731

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130830

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131217

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140128

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140225

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140311

R150 Certificate of patent or registration of utility model

Ref document number: 5500798

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees