JP5500781B2 - Ｓｏｉ基板の製造方法 - Google Patents

Ｓｏｉ基板の製造方法 Download PDF

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Publication number
JP5500781B2
JP5500781B2 JP2008110291A JP2008110291A JP5500781B2 JP 5500781 B2 JP5500781 B2 JP 5500781B2 JP 2008110291 A JP2008110291 A JP 2008110291A JP 2008110291 A JP2008110291 A JP 2008110291A JP 5500781 B2 JP5500781 B2 JP 5500781B2
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layer
substrate
semiconductor substrate
ions
semiconductor
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Expired - Fee Related
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JP2008110291A
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Japanese (ja)
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JP2008311627A5 (https=
JP2008311627A (ja
Inventor
英人 大沼
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2008110291A priority Critical patent/JP5500781B2/ja
Publication of JP2008311627A publication Critical patent/JP2008311627A/ja
Publication of JP2008311627A5 publication Critical patent/JP2008311627A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP2008110291A 2007-05-17 2008-04-21 Ｓｏｉ基板の製造方法 Expired - Fee Related JP5500781B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008110291A JP5500781B2 (ja) 2007-05-17 2008-04-21 Ｓｏｉ基板の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007132085 2007-05-17
JP2007132085 2007-05-17
JP2008110291A JP5500781B2 (ja) 2007-05-17 2008-04-21 Ｓｏｉ基板の製造方法

Publications (3)

Publication Number Publication Date
JP2008311627A JP2008311627A (ja) 2008-12-25
JP2008311627A5 JP2008311627A5 (https=) 2011-06-02
JP5500781B2 true JP5500781B2 (ja) 2014-05-21

Family

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Family Applications (1)

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JP2008110291A Expired - Fee Related JP5500781B2 (ja) 2007-05-17 2008-04-21 Ｓｏｉ基板の製造方法

Country Status (3)

Country Link
US (3) US7666757B2 (https=)
EP (1) EP1993128A3 (https=)
JP (1) JP5500781B2 (https=)

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JP5275608B2 (ja) 2007-10-19 2013-08-28 株式会社半導体エネルギー研究所 半導体基板の作製方法
TWI493609B (zh) * 2007-10-23 2015-07-21 半導體能源研究所股份有限公司 半導體基板、顯示面板及顯示裝置的製造方法
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7820527B2 (en) * 2008-02-20 2010-10-26 Varian Semiconductor Equipment Associates, Inc. Cleave initiation using varying ion implant dose
US7939389B2 (en) 2008-04-18 2011-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5552276B2 (ja) * 2008-08-01 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5263509B2 (ja) * 2008-09-19 2013-08-14 信越半導体株式会社 貼り合わせウェーハの製造方法
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
CN102203904B (zh) 2008-10-30 2013-11-20 S.O.I.探测硅绝缘技术公司 形成具有减小的晶格应变的半导体材料层、半导体结构、装置的方法及包含具有减小的晶格应变的半导体材料层、半导体结构、装置的工程衬底
JP5478199B2 (ja) * 2008-11-13 2014-04-23 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8043938B2 (en) * 2009-05-14 2011-10-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and SOI substrate
JP5866088B2 (ja) * 2009-11-24 2016-02-17 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP5471379B2 (ja) * 2009-12-04 2014-04-16 株式会社村田製作所 圧電デバイスの製造方法
EP2330697A1 (en) * 2009-12-07 2011-06-08 S.O.I.Tec Silicon on Insulator Technologies Semiconductor device having an InGaN layer
JP2011124738A (ja) * 2009-12-10 2011-06-23 Murata Mfg Co Ltd 圧電デバイスの製造方法
JP2011227369A (ja) * 2010-04-22 2011-11-10 Hitachi Displays Ltd 画像表示装置及びその製造方法
JP5851113B2 (ja) * 2010-04-26 2016-02-03 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
KR101850540B1 (ko) * 2010-10-13 2018-04-20 삼성전자주식회사 후면 수광 이미지 센서를 갖는 반도체 소자
JP5917861B2 (ja) * 2011-08-30 2016-05-18 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法
US8883612B2 (en) * 2011-09-12 2014-11-11 Infineon Technologies Austria Ag Method for manufacturing a semiconductor device
JP6315262B2 (ja) 2014-06-12 2018-04-25 ソニー株式会社 固体撮像素子、固体撮像素子の製造方法、及び、撮像装置
FR3036223B1 (fr) * 2015-05-11 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats
US9725312B1 (en) * 2016-02-05 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Preconditioning to enhance hydrophilic fusion bonding
CN107154379B (zh) * 2016-03-03 2020-01-24 上海新昇半导体科技有限公司 绝缘层上顶层硅衬底及其制造方法
FR3065322B1 (fr) * 2017-04-18 2019-06-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un dispositif d'affichage a matrice de leds
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FR3094559B1 (fr) * 2019-03-29 2024-06-21 Soitec Silicon On Insulator Procédé de transfert de paves d’un substrat donneur sur un substrat receveur
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Also Published As

Publication number Publication date
US8030174B2 (en) 2011-10-04
US20100087046A1 (en) 2010-04-08
US20080286939A1 (en) 2008-11-20
JP2008311627A (ja) 2008-12-25
US7666757B2 (en) 2010-02-23
EP1993128A3 (en) 2010-03-24
US20110315900A1 (en) 2011-12-29
EP1993128A2 (en) 2008-11-19

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