JP5448895B2 - 静電気放電保護装置及び方法 - Google Patents
静電気放電保護装置及び方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Description
図1は、従来のHVNW装置を示す図である。p+ドープガードリング(guard−ring)2が円形装置を囲繞する。ガードリング2の内側にn+ドープソース4がある。ソース4の内側には高電圧N(HVNW)ウェル6、及び、n+ドープドレイン8がある。
4 n+ドープソース
6 高電圧nウェル
8 n+ドープドレイン
20、22、32、120 フィールド酸化膜
24 nドープ領域
26 pドープウェル
28 ゲート構造
30、102 基板
34、52 nドレイン拡散領域
36 nウェル
40、56、142 コンタクト
50 ドレイン
54 n+ドープ領域
104 エピタキシャル基板
106、110、114、122、128 レジスト層
108 pウェル
112 高電圧nウェル
116 ディープウェル
118、132、138 ハードマスク層
124 pウェル中のn+領域
126 ディープ中のn+領域
130 p+領域
134 ゲート構造
136 誘電層
140 開口
Claims (12)
- 静電気放電(ESD)保護装置であって、
基板に配置されたpウェルと、
前記基板に配置されたnウェルと、
前記基板中の前記pウェルと前記nウェルの間に配置された高電圧nウェル(HVNW)と、
前記pウェルに配置されたソースn+領域と、
前記nウェルに配置された複数のドレインn+領域であって、前記の複数のドレインn+領域は、少なくとも100個のドレインn+領域を含み、各ドレインn+領域のすべての縁端は、他のドレインn+領域のすべての縁端から少なくとも約1μm離れていることと、
からなることを特徴とするESD保護装置。 - 更に、複数のコンタクトを有し、各ドレインn+領域が少なくとも一つのそれぞれのコンタクトに電気的に結合することを特徴とする請求項1に記載のESD保護装置。
- 前記nウェルは、4000μm 2 と5000μm2の間の面積を有し、前記の複数のドレインn+領域は、4μm 2 と6μm2の間の面積を有することを特徴とする請求項1に記載のESD保護装置。
- 前記nウェルは、4000μm 2 と5000μm2の間の面積を有することを特徴とする請求項1に記載のESD保護装置。
- 前記の複数のドレインn+領域は集団化され、前記集団は前記nウェルに中心的に位置決めされることを特徴とする請求項1に記載のESD保護装置。
- 前記nウェルは、4000μm 2 と5000μm2の間の面積を有し、前記集団は、2000μm 2 と2500μm2の間の面積に配置されることを特徴とする請求項5に記載のESD保護装置。
- 前記nウェルは、4000μm 2 と5000μm2の間の面積を有し、前記の複数のドレインn+領域の集団の集中は、15μm2当たり1個のドレインn+領域と25μm2当たり1個のドレインn+領域の間であることを特徴とする請求項5に記載のESD保護装置。
- 静電気放電(ESD)保護装置用のドレインであって、
ドープウェルと、
前記ドープウェル内の複数の高ドープ領域であって、各高ドープ領域は、他の全ての高ドープ領域から物理的に分離され(physically isolated)、前記の複数の高ドープ領域は、少なくとも100個の高ドープ領域を有し、前記の複数の高ドープ領域の各々は、少なくとも1μm隔てられていることと、
少なくとも一つのコンタクトが、各高ドープ領域に電気的に結合される複数のコンタクトと、からなることを特徴とするESD保護装置用のドレイン。 - 前記の複数の高ドープ領域は、15μm2当たり1個の高ドープ領域と25μm2当たり1個の高ドープ領域の間の集中により前記ドープウェル中でクラスタ化されることを特徴とする請求項8に記載のESD保護装置のドレイン。
- 前記ドープウェルはnドープウェルで、前記の複数の高ドープ領域は、n+ドープ領域であることを特徴とする請求項8に記載のESD保護装置のドレイン。
- pウェルを半導体基板に形成するステップと、
高電圧nウェルを前記半導体基板中に形成するステップと、
ディ−プnウェルを前記高電圧nウェルに形成するステップと、
複数のn+領域を前記ディ−プnウェルに形成するステップであって、前記の複数のドレインn+領域は、少なくとも100個のn+領域を含み、各n+領域のすべての縁端は、他のドレインn+領域のすべての縁端から少なくとも約1μm離れているステップと、
からなることを特徴とする静電気放電装置を形成する方法。 - 更に、各n+領域に電気的に結合するコンタクトを形成するステップを含むことを特徴とする請求項11に記載の方法。
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Application Number | Priority Date | Filing Date | Title |
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US15054209P | 2009-02-06 | 2009-02-06 | |
US61/150,542 | 2009-02-06 | ||
US12/609,803 | 2009-10-30 | ||
US12/609,803 US8378422B2 (en) | 2009-02-06 | 2009-10-30 | Electrostatic discharge protection device comprising a plurality of highly doped areas within a well |
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JP2010183081A JP2010183081A (ja) | 2010-08-19 |
JP5448895B2 true JP5448895B2 (ja) | 2014-03-19 |
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US (2) | US8378422B2 (ja) |
JP (1) | JP5448895B2 (ja) |
KR (1) | KR101121327B1 (ja) |
CN (1) | CN101800213B (ja) |
TW (1) | TWI405318B (ja) |
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US8476684B2 (en) * | 2010-09-29 | 2013-07-02 | Analog Devices, Inc. | Field effect transistors having improved breakdown voltages and methods of forming the same |
CN104425583B (zh) * | 2013-08-20 | 2018-05-04 | 旺宏电子股份有限公司 | 半导体装置及其制造方法 |
US9496251B2 (en) * | 2014-09-24 | 2016-11-15 | United Microelectronics Corporation | Electrostatic discharge protector |
TWI632683B (zh) * | 2014-11-26 | 2018-08-11 | 聯華電子股份有限公司 | 高壓金氧半導體電晶體元件 |
TWI678790B (zh) * | 2019-04-10 | 2019-12-01 | 旺宏電子股份有限公司 | 靜電放電防護元件 |
US11817447B2 (en) | 2019-12-10 | 2023-11-14 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection element and semiconductor devices including the same |
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