CN101800213B - 静电放电防护装置、其制造方法及用于其的漏极 - Google Patents

静电放电防护装置、其制造方法及用于其的漏极 Download PDF

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CN101800213B
CN101800213B CN2010101140078A CN201010114007A CN101800213B CN 101800213 B CN101800213 B CN 101800213B CN 2010101140078 A CN2010101140078 A CN 2010101140078A CN 201010114007 A CN201010114007 A CN 201010114007A CN 101800213 B CN101800213 B CN 101800213B
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许明松
李建兴
冯耀武
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例涉及一种静电放电防护装置、其制造方法及用于其的漏极。一实施例为一静电放电防护装置，包含一p型阱区位于一基材中，一n型阱区位于此基材中，一高电压n型阱区位于此基材中及n型阱区与p型阱区之间，一n+源极区位于此p型阱区中，及多个n+漏极区位于此n型阱区中。

Description

静电放电防护装置、其制造方法及用于其的漏极
技术领域
本发明涉及静电放电(ESD)防护装置及其制造方法，且特别涉及一种保护高电压半导体装置的静电放电防护装置及其制造方法。
背景技术
静电可在集成电路附近产生极高的电压，而使集成电路遭受静电放电事件(ESD event)。当静电能量释放时，可产生高电流通过集成电路装置。例如，当某人带有静电并碰触集成电路的插脚(pin)时，释放至集成电路上的静电可产生高电压及高电流至集成电路的输入或输出缓冲器。既然静电放电具有毁坏装置及整个集成电路的潜在危险，其对于半导体装置是不可轻忽的问题。
集成电路通常会将静电放电防护装置整合于其中。静电放电防护装置可提供路径给电流，以使静电放电瞬间发生时，将静电放电导致静电放电防护装置而非流经受其保护的装置。在静电放电防护装置中，传统是使用高电压n型阱区装置，特别是用以防护高电压半导体装置。
发明内容
依照本发明一实施例所述的一种静电放电(ESD)防护装置，包括：一p型阱区，位于一基材中；一n型阱区，位于此基材中；一高电压n型阱区(HVNW)，位于此基材中的此n型阱区及此p型阱区之间；一n+源极区域，位于此p型阱区中；以及多个n+漏极区域，位于此n型阱区中。
依照本发明另一实施例所述的一种用于静电放电(ESD)装置的漏极，包括：一掺杂阱区；多个高度掺杂区域，位于此掺杂阱区中，其中每个高度掺杂阱区与所有其他高度掺杂区域物理性隔离(physically isolated)；以及多个接触点，其中至少一接触点电性连接至每个高度掺杂区域。
依照本发明又一实施例所述的一种静电放电防护装置的制造方法，包括：形成一p型阱区于一半导体基材中；形成一高电压n型阱区于此半导体基材中；形成一深n型阱区于此高电压n型阱区中；以及形成n+区域于此深n型阱区中。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附附图，作详细说明如下。
附图说明
图1显示为一传统高电压n型阱区装置的输出(layout)。
图2显示为一传统高电压n型阱区装置的剖面图。
图3A显示为一传统高电压n型阱区装置的漏极的平视图。
图3B显示为一传统高电压n型阱区装置的漏极的剖面图。
图4A显示为依照本发明一实施例的静电放电装置的漏极的平视图。
图4B显示为依照本发明一实施例的静电放电装置的漏极的剖面图。
图5A-图5J显示为依照本发明一实施例的静电放电装置的制造过程。
并且，上述附图中的附图标记说明如下：
2～防护环               4～n+掺杂源极
6～高电压n型阱区        8～n+掺杂漏极
20、22、32～场氧化层
24～n型掺杂区域         26～p型掺杂阱区
28～栅极结构            30～基材
34～n型漏极扩散区域     36～n型阱区
40～接触点              50～漏极
52～n型漏极扩散区域     54～n型掺杂区域
56～接触点              102～基材
104～外延基材           106～光致抗蚀剂层
108～p型阱区            110～光致抗蚀剂层
112～高电压n型阱区      114～光致抗蚀剂层
116～深n型阱区          118～硬掩模层
120～场氧化层           122～光致抗蚀剂层
124～p型阱区中的n+区域
126～深n型阱区中的n+区域
128～光致抗蚀剂层    130～p+区域
132～硬掩模层        134～栅极结构
136～介电层          138～硬掩模
140～开口            142～接触点
具体实施方式
以下将详细讨论本发明各种实施例的制造及使用方法。然而值得注意的是，本发明所提供的许多可行的发明概念可实施在各种特定范围中。这些特定实施例仅用于举例说明本发明的制造及使用方法，但非用于限定本发明的范围。
本发明将描述特定范围中的对应实施例，称为静电放电(ESD)防护装置。
图1显示为传统高电压n型阱区(HVNW)装置。P+掺杂防护环2(guard-ring)环绕此圆形装置。防护环2内为n+掺杂源极4。源极4内为高电压n型阱区6及n+掺杂漏极8。
图2显示为图1中的传统装置沿着X-X轴切的剖面图。两个场氧化层20及22将防护环2隔离。源极4位于n型漏极扩散区域24中。防护环2及n型掺杂区域24皆位于p型掺杂阱区26中。位于基材30上的栅极结构28自n型掺杂区域24的内部边缘延伸至另一场氧化层32并将其部分覆盖。部分的栅极28及场氧化层32覆盖高电压n型阱区6。场氧化层32延伸至漏极8的外缘。漏极8位于n型阱区36中的n型漏极扩散区域34。n型阱区36延伸至高电压n型阱区6。
通常，此传统装置电性连接在集成电路的输入/输出垫之间。当静电放电发生的瞬间，装置即启动并将电流导离其他在集成电路上的装置。
图3A及图3B显示为传统装置的漏极8。图3A显示为漏极8的平视图。图3B显示为漏极8的剖面图。在两图中，n+掺杂漏极8皆是由一个含多个接触点40的n+掺杂区域组成。接触点40紧密集中在漏极8的中央。通常，接触点40为集中在漏极8中央的直径约12μm的区域内，漏极8的直径为约50μm。
如以下更详尽的讨论，在单一n+掺杂区域中的接触点40浓度可造成电流聚集在靠近群组边缘的接触点40。靠近群组边缘的接触点与源极之间的路径相较于内部接触点与源极之间的路径具有较低的电阻。因此，通常较多的电流是流经外部的接触点。当流经外部接触点的电流增加，会导致这些接触点过热而毁损，且最终将导致整个装置毁损。
图4A及图4B显示为本发明的一实施例。图4A显示为漏极50的平视图，图4B显示为漏极50的剖面图。在两图中，n型漏极扩散区域52中具有多个n+掺杂区域54并构成漏极50。每个n+掺杂区域54具有一接触点56。每个n型漏极区域54的直径为约2.5μm，且n型阱区36的直径为约75μm。换句话说，n型漏极区域54及n型阱区36的面积各自为4.91μm2及4,420μm2。然而，本领域普通技术人员可知这些数值会随着本发明的技术需求而有所增减，例如n型漏极区域54及n型阱区36的面积可各自介于4至6μm2之间及4,000至5,000μm2之间。
再者，本发明的一实施例具有约100个n+掺杂区域，虽然其可能会有所变动。这些n+掺杂区域54集中在n型阱区36中心面积约2,000至2,500μm2的区域中，例如在中心面积约2,200μm2的区域中。每个n+掺杂区域54的边缘与其他n+掺杂区域54的每个边缘间隔至少1μm。因此，此1μm的距离作为所有n+掺杂区域54之间的缓冲。如此，n+掺杂区域54群聚(clustered)在n型阱区中，n+掺杂区域54于n型阱区中的浓度为约1个/15-25平方微米(μm2)，较佳为1个/19平方微米(μm2)。虽然前述已针对特定实施例描述其尺寸，然而本领域普通技术人员可知此尺寸可随任何特定应用而变化，且仍不脱离本发明的范围。
在这些实施例中，n+掺杂区域或漏极的性质通常可随着创造这些具有接触点56的多个独立n+掺杂区域54而有所改良，以避免过量的电流流经外部接触点造成接触点损坏。通常，当流经n+掺杂区域或漏极的电流增加时，n+掺杂区域或漏极中的电阻也会增加。再者，一般已知的是，两接触点之间的距离可影响两接触点之间的电阻，特别是在半导体装置中，两接触点间的距离较长通常会有较大的电阻(假设全部的接点及其他变数为相等的)。
因此，对于图3A及图3B所示的传统装置来说，在n+掺杂源极4之间最小的电阻为在电流流经的n+掺杂源极4及与其最接近的外部接触点之间。因为全部接触点40皆位于单一的n+掺杂漏极8中，所有其他变数皆相等，且因为传统装置的每个接触点40共用相同的n+掺杂漏极8，使其无法有效地使用n+掺杂漏极8的电阻性质来影响电流流经每个接触点40。因此，当静电放电防护事件发生且电流流至n+掺杂漏极时，由于至外部接触点具有最短的路径，这些外部接触点可能会接收大量的电流，且会因高电流对这些接触点带来高热损坏而无法作用。
然而，在本发明实施例中使用多个各自含有接触点56的n+掺杂区域54。因此，每个n+掺杂区域54可有效地使电流流经每个接触点56。在静电放电事件发生前，n+掺杂区域56通常不会决定哪一个接触点56至源极之间有最小电阻，但源极与每个接触点56之间的距离决定了至哪一个接触点56有最小电阻。因此，在静电放电事件刚开始时，电流有较多的可能是流经n+掺杂区域54及最外部的接触点56。但当电流流经n+掺杂区域的量增加时，电流所流经的n+掺杂区域的电阻也会增加。如此，当外部接触点56的电阻增加至大于某些内部接触点56的程度时，电流将开始流经内部接触点56。此特征其可由将n+掺杂区域分隔而使每个接触点56分隔以达成。通过分隔这些n+掺杂区域54，每个接触点56的电阻性质可独立操作。相对于传统装置由于无法独立操作n+掺杂漏极电阻以区别这些接触点40，则无法利用这些性质。因此，本发明所提供的实施例可使电流更一致的流经接触点56，以减少这些接触点56的热损坏。
图5A-图5J显示为依照本发明实施例制造静电放电(ESD)装置的工艺。在图5A中，外延基材104形成在基材102上。在图5B中，将光致抗蚀剂层106图案化以暴露外延基材中欲形成p型阱区108的区域。掺杂p型杂质至外延基材104中以形成p型阱区108，并接着移除光致抗蚀剂层106。在图5C中，将在外延基材104上的光致抗蚀剂层106图案化，以暴露出外延基材104中欲形成高电压n型阱区112的区域。掺杂n型杂质至外延基材中形成高电压n型阱区112。接着，移除光致抗蚀剂层110。
在图5D中，形成一光致抗蚀剂层114，暴露出外延基材104中欲形成深n型阱区116的区域。接着，掺杂n型杂质至外延基材104中以形成深n型阱区116。
在图5E中，形成场氧化层120在外延基材104上由掩模层108所暴露的区域。或者，场氧化层120可为浅沟槽隔离(STI)。
在图5F中，将在外延基材104上的另一光致抗蚀剂层122图案化，以暴露出一部分的p型阱区108及一部分的深n型阱区116。此深n型阱区116的暴露区域由多个分布于深n型阱区116的表面区域所组成。接着，添加n型杂质以在p型阱区108形成n+区域124及在深n型阱区116中形成多个n+区域126。在图5G中，将光致抗蚀剂层128图案化以暴露出p型阱区中欲形成p+区域130的区域。接着，掺杂P型杂质至此暴露区域中。
图5H显示为一介电层(未显示)形成在外延基材104上及一多晶硅层(未显示)形成在此介电层上。将硬掩模层132图案化以覆盖多晶硅层上的将要形成栅极结构的区域。接着，蚀刻多晶硅层及介电层以在外延基材104上形成栅极结构134，或也可使用其他本领域公知工艺来形成栅极结构134。
在图5I中，移除硬掩模层132及形成介电层136于外延基材104上。形成硬掩模138于介电层136上并将其图案化以暴露出介电层136中将要形成接触点的区域。接着，蚀刻介电层136以形成开口140，并移除硬掩模138。如图5J所示，接着将介电层136中的开口填满金属以形成接触点142，且由研磨将所有多出的金属移除，例如化学机械研磨。
虽然本发明已以数个较佳实施例公开如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。
此外，本发明的范围不限定于本说明书所述的特定程序、机器、制造、物质的组合、功能、方法或步骤。本领域普通技术人员将可依照本发明所揭示的现有或未来所发展的特定程序、机器、制造、物质的组合、功能、方法或步骤达成相同的功能或相同的结果。因此本发明的保护范围包含这些程序、机器、制造、物质的组合、功能、方法或步骤。

Claims (13)

1.一种静电放电防护装置，包括：
一p型阱区，位于一基材中；
一n型阱区，位于该基材中，且被该p型阱区围绕；
一高电压n型阱区，位于该基材中的该n型阱区及该p型阱区之间；
栅极结构，位于该基材上，覆盖部分的该高电压n型阱区；
一n+源极区域，位于该p型阱区中；以及
多个n+漏极区域，位于该n型阱区中，其中每个n+漏极区域皆电性连接至少一对应的接触点。
2.如权利要求1所述的静电放电防护装置，其中该n型阱区的面积介于4,000至5,000μm2之间，且其中每个n+漏极区域的面积介于4至6μm2之间。
3.如权利要求1所述的静电放电防护装置，其中该n型阱区的面积介于4,000至5,000μm2之间，且其中每个n+漏极区域的每个边距离其他该n+漏极区域的每个边至少1μm。
4.如权利要求1所述的静电放电防护装置，其中该多个n+漏极区域包含至少100个n+漏极区域。
5.如权利要求1所述的静电放电防护装置，其中该多个n+漏极区域聚集成为一群组，且该群组位于该n型阱区中央。
6.如权利要求5所述的静电放电防护装置，其中该n型阱区的面积介于4,000至5,000μm2之间，且其中该群组位于一面积为2,000至2,500μm2的区域中。
7.如权利要求5所述的静电放电防护装置，其中该n型阱区的面积介于4,000至5,000μm2之间，且其中由多个n+漏极区域组成的该群组的浓度为每15-25μm2一个n+漏极区域。
8.一种用于静电放电装置的漏极，包括：
一掺杂阱区；
多个高度掺杂区域，位于该掺杂阱区中，其中每个高度掺杂区域与所有其他高度掺杂区域物理性隔离；以及
多个接触点，其中至少一接触点电性连接至该多个高度掺杂区域中的每个高度掺杂区域。
9.如权利要求8所述的用于静电放电装置的漏极，其中所述多个高度掺杂区域群聚在该掺杂阱区中，其浓度为每15-25μm2一个高度掺杂区域。
10.如权利要求8所述的用于静电放电装置的漏极，其中每个高度掺杂区域彼此之间相隔至少1μm。
11.如权利要求8所述的用于静电放电装置的漏极，其中所述多个高度掺杂区域包含至少100个高度掺杂区域。
12.如权利要求8所述的用于静电放电装置的漏极，其中该掺杂阱区为n型阱区，且其中该多个高度掺杂区域为n+型阱区。
13.一种静电放电防护装置的制造方法，包括：
形成一p型阱区于一半导体基材中；
形成一高电压n型阱区于该半导体基材中；
形成一深n型阱区于该高电压n型阱区中，该深n型阱区于该半导体基材中的深度较该高电压n型阱区深；
形成多个n+漏极区域于该深n型阱区中，其中每个n+漏极区域与所有其他n+漏极区域物理性隔离；
形成多个接触点和一栅极结构于该半导体基材上，其中至少一接触点电性连接至每个n+漏极区域，该栅极结构覆盖部分的该高电压n型阱区。
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CN101800213A (zh) 2010-08-11
US20100200922A1 (en) 2010-08-12
US8551835B2 (en) 2013-10-08
JP2010183081A (ja) 2010-08-19
JP5448895B2 (ja) 2014-03-19
US20130157430A1 (en) 2013-06-20
TW201030932A (en) 2010-08-16
TWI405318B (zh) 2013-08-11
US8378422B2 (en) 2013-02-19
KR101121327B1 (ko) 2012-03-09

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