CN101180738B - 不对称高电压器件和制造方法 - Google Patents

不对称高电压器件和制造方法 Download PDF

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CN101180738B
CN101180738B CN2006800106368A CN200680010636A CN101180738B CN 101180738 B CN101180738 B CN 101180738B CN 2006800106368 A CN2006800106368 A CN 2006800106368A CN 200680010636 A CN200680010636 A CN 200680010636A CN 101180738 B CN101180738 B CN 101180738B
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cmos
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西奥多·莱塔维奇
赫尔曼·埃芬
罗伯特·库克
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Koninklijke Philips NV
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Abstract

一种不对称半导体器件(10)及其形成方法，其中可在工艺中使用设计用于2.75或5.5V最大操作的栅极氧化物厚度来制造25V器件。所述器件包括：浅槽隔离(STI)区(12)，其在一个晶胞的漏极区(18)和栅极区(20)之间形成电介质以允许高电压操作；和在所述晶胞内摹制的n型阱(14)和p型阱(24)。

Description

不对称高电压器件和制造方法
本申请要求2005年3月31日提出的序列号为60/666,923、标题为“COMPLEMENTARY ASYMMETRIC HIGH VOLTAGE DEVICES AND METHODOF FABRICATION”的同时未决的美国临时专利申请的优先权，所述专利申请通过参考而被并入本文。
技术领域
本发明通常涉及半导体器件结构，更加具体地说，涉及一种具有在漏极和栅极之间形成电介质的浅槽隔离(STI)区的半导体器件结构。
背景技术
当前，传统的横向扩散金属氧化物半导体器件(LDMOS)被广泛的用于电源管理和汽车集成电路。这种器件例如见诸于Ludikhuize，A.W.在2000年5月22-25日召开的第12届国际研讨会Power Semiconductor Devices and ICs学报(第11-18页)上发表的“A Review of RESURF Technology”，上述文献在本文中作为参考。
本文讨论的是用于横向扩展漏极或LDMOS器件结构的当前现有技术的设计和性能。这些器件是通过专有过程制造的，或者这些器件被集成在现有互补金属氧化物半导体(CMOS)型工艺流程中。在这些器件设计中，通过在轻微掺杂漏极半导体扩展上生长较厚的场效氧化区来形成漏极或漂移扩展区。所述较厚的场效氧化区用于支持漏极-栅极施加电压，而不会降低MOS器件的沟道区域上的栅极氧化物。轻微掺杂漏极区中的掺杂受最大漏极电压和在前向安全操作区域中和在瞬时最大电压应力下的器件鲁棒性的限制。LDMOS器件结构的制造涉及对用于所制造的每种类型的器件(n沟道和p沟道)的标准CMOS工艺流程添加至少两个屏蔽电平。在漏极和栅极之间生长厚的热氧化层所需的热预算严重限制了以相同集成工艺流程制造的CMOS部件的性能。
因此，需要一种改进的CMOS器件，其能提供能被用于移动电源管理集成电路(PMU)应用的低成本技术基础。
发明内容
本发明使用深亚微米CMOS工艺流程的工艺模块来构成扩展漏极高电压器件，而不是设计高电压结构和试图将它集成到现有的工艺流程中。具体地说，深亚微米CMOS的浅槽隔离结构用于在高电压器件的漏极和栅极之间形成厚的电介质区，而CMOS的栅极氧化物和阱注入物(well implant)用于设计不对称非自动对齐扩展漏极高电压器件。这样做的一个好处是在现有的深亚微米工艺流程中不用附加的掩膜就能制造高电压器件。单一的高能量注入掩膜(例如，深n阱注入)被添加到基线CMOS工艺流程以提供高电压器件与基片的隔离，并提供耗尽电荷以对击穿电离轨道定形，其对于一些功率集成电路应用是必需的。
因为现有的CMOS工艺模块用于制造高电压器件，所以传统方案的添加漂移掺杂层和厚场效氧化区的工艺复杂性被消除了。这给出了成本和性能的益处，因为并不会干扰基线深亚微米工艺构成高电压部件。
按照第一方面，本发明提供一种不对称CMOS器件，其包括：浅槽隔离(STI)区，其在一个晶胞的漏极区和栅极区之间形成电介质以允许高电压操作；和在所述晶胞内摹制的n型阱和p型阱。
按照第二方面，本发明提供一种形成不对称(CMOS)器件的方法，包括：形成第一种类型的深阱注入物；在所述深阱注入物上面而在漏极区和一部分栅极区下面形成第一种类型的第一阱注入物；在与所述漏极位置相邻的一部分栅极位置下面的第一阱注入物中形成浅槽隔离(STI)区；在源极区下面形成第二种类型的第二阱注入物。
按照第三方面，本发明提供一种形成不对称CMOS器件的方法，包括步骤：在外延层和基片层上面形成第一种类型的深阱注入物；在漏极区和一部分栅极区下面形成第一种类型摹制的第一阱注入物；在源极区下面形成第二种类型摹制的第二阱注入物；在一个晶胞的漏极区和栅极区之间形成浅槽隔离(STI)区以允许高电压操作；和其中使用从下述的组中选择的基线CMOS流程来制造所述器件，所述组由以下构成：5伏基线CMOS流程，其中利用近似12.3-15.0nm的栅极氧化物厚度，并且所述第一和第二阱注入物包括高电压p阱注入物和高电压n阱注入物；和2.5伏基线CMOS工艺流程，其中利用近似5.0-5.4nm的栅极氧化物厚度，并且所述第一和第二阱注入物包括n型阱(NW)和p型阱(PW)。
本发明的一个特征是可将STI区并入到晶体管的有效晶胞中，而不是仅仅使用它来隔离CMOS。一个另外的新见识是可将定标的CMOS工艺模块用于形成电压高得多的晶体管的沟道和扩展漏极区，而不用对所述工艺加入额外的掩膜。高电压设计的2D布局提供了稳健的高电压性能，在特定的布局设计和CMOS基线STI模块的最佳化中存在相当大量的知识产权。使用NMOS和PMOS基线CMOS工艺模块通过匹配阈值电压特性可容易地获得互补高电压器件。
附图说明
本发明的这些和其它方面通过下面结合附图对本发明的各方面的详细说明将变得更加容易理解，其中：
图1表示根据本发明一个实施例的被集成到5伏CMOS工艺中的不对称高电压器件的剖面布局，所述不对称高电压器件具有在一个晶胞的漏极和栅极之间制造的浅槽隔离(STI)区。
图2表示作为用于图1的漏偏压函数的碰撞电离的仿真。
图3表示用于使用5V或2.5V基线CMOS模块制造的互补EDMOS器件的测量电流/电压(IV)特性和截止电压特性。
图4表示根据本发明一个实施例的具有环类结构的表面布局。
图5表示根据本发明一个实施例的具有线性结构的表面布局。
图6表示根据本发明一个实施利的分别用于5V和2.5V部件的倒阱表。
具体实施方式
此处所述的该实施例提供一种高电压CMOS或扩展漏极高电压器件领域中的新半导体器件。规定一种设计和工艺技术以通过在器件的栅极和漏极之间提供较厚的电介质区域来极大地增加互补NMOS和PMOS器件的击穿电压。所述电介质区是在没有额外工艺步骤的情况下加入的，因为使用了浅槽隔离(STI)工艺模块。其结果是在设计用于2.75或5.5V最大操作的栅极氧化物厚度的工艺中就能制造＞25V的器件。这提供了低成本技术基础，可将该低成本技术基础用于类似移动电源管理集成电路(PMU)应用这样的应用。
图1表示一个扩展漏极n沟道器件(EDNMOS)10的剖面图，所述扩展漏极n沟道器件被制造使得在所述器件结构的晶胞中形成一个浅槽隔离区(STI)12。STI12在漏极区18和栅极区20之间形成一个厚的电介质区，其能够支持比设计用于基线CMOS工艺流程高得多的电压。
所示器件10包括DN阱(深n阱注入)层22、在源极区16下面的HPW(高电压p阱注入)层24和在漏极区18和一部分栅极区20下面的HNW(高电压n阱注入)层14。在该情况下，STI12位于HNW层30内，并在漏极18和源极16之间形成一个厚的电介质区。简单地通过使所述阱颠倒，即，使用低电压PMOS工艺模块形成扩展漏极PMOS(EDPMOS)就能实现扩展漏极p沟道器件。在DN阱层22下面的是外延(EPI)层21和P++基片23。
目前有两个阱和栅极氧化物厚度可用于制造高电压晶体管：
栅极氧化物1(GO1)＝近似5.0-5.4nm厚，具有2.5V(倒)阱、高电压p阱注入物(HPW)和高电压n阱注入物(HNW)；或者
栅极氧化物2(GO2)＝近似12.3-15.0nm厚，具有5V(倒)阱、p阱注入物(PW)和n阱注入物(NW)。
图1中的器件10是使用基线CMOS流程的5V CMOS工艺模块(即GO2)制造的。HPW24是扩散用于5V NMOS的沟道，HNW14是扩散用于5V PMOS的沟道。也可使用所述2.5V模块来代替具有NW的HNW14和具有PW的HPW24并使用薄的GO1栅极氧化物。使用GO1或GO2制造的EDMOS器件可阻止超过25V的电压，该电压远高于设计用于基线晶体管的电压。
如可以看出的，多晶硅栅极区20在STI12上扩展，从而允许厚的STI电介质支持漏极-栅极电压。这会打破栅极氧化物厚度的标准定标法则来应用电压。定义扩展漏极器件的击穿电压的一个重要设计参数是STI边缘26上的漏极扩展光致抗蚀剂掩膜的重叠部分28(即，通过HNW14形成的区域)。HNW电荷将重掺杂的漏极区18与器件区24的沟道区分离开。在许多情况中，最佳性能是通过使重叠距离28为负获得的，即漏极扩展光致抗蚀剂掩膜被从STI边缘26拉远，从而使STI12能够阻止被注入的几乎所有(倒)阱电荷，从而只使注入横向散布用于定义漏极扩展剂量。
用于定义器件的BVds(击穿电压)的另外的重要布局参数如下。EDNMOS器件10的STI12上的HNW14的掩膜重叠或欠重叠“HNW olpSTI”28是非常重要的，如同EDPMOS器件的STI12上的HPW(未示)。多晶硅栅极区20的HPW24重叠“HWP olp PS”30应被设置得足够大以给出与相应的NMOS元件(PMOS的HNW)相同的导通阈值电压。Vto是通过HPW区24中的电荷总量确定的。因为它是掩膜定义的，所以重叠30必须足够大以给出完全的表面浓度以获得与导出的较低电压阱相同的阈值电压。
图2和图3表示使用5V或2.5V基线CMOS模块制造的互补EDMOS器件的测量电流/电压(IV)特性和截止电压特性，所述5V和2.5V基线CMOS模块都具有并列放置在栅极区20和漏极18区之间的STI层12。该器件构成的一个额外优点是通过提供对于器件10来说是固有的压载阻抗，沿STI侧壁的漏极阻抗改进了前向SOA(安全操作区)和ESD(静电放电)。
在图2中，能够看出对于GO2 EDMOS器件的测量IV曲线示出了BVds＝25V和一个良好的前向安全操作区。类似于在图2中，能够看出对于GO1 EDMOS器件的测量IV曲线示出了BVds＝25V和一个良好的前向安全操作区。
图2和图3表示这样的实验结果：可将该设计技术用于制造具有足够高电压操作(25V)的器件来将电源管理功能包括到基线CMOS工艺流程中。这些图是扩展工艺和器件仿真的结果，以定义这些扩展漏极结构的最佳布局和设计，并最终在一个集成工艺流程内构成这些器件以改进所述观念。这些器件还包含一个额外注入的深NW(DN阱22)，其用于将所述扩展漏极与基片分离开。设计所述器件使得横向击穿低于垂直击穿。
器件仿真表示2D布局完全定义了这些元件的行为，所述布局是所述2.5V和5V工艺模块不能被改变的唯一自由度，因为基线2.5V和5V部件的性能必须要保证。
器件10的2D表面布局对于在被设计只用于低电压(＜5V)的工艺中保持较高的电压(即25V)也是重要的。在一个示意实施例中，当晶体管距所述表面的2D布局处于环形形状使得圆柱区域中的STI宽度大于在线性区域中的STI宽度时，获得稳健的高电压性能。在图4中示出了一个实例，其中示出了环形器件40的左上角。在右下角(即环中心)是漏极区50，所述漏极区50由多晶硅栅极区52包围。另外在所述环外部的是源极区54。STI区56在栅极区52内侧部分的下面形成一个围绕漏极区50的环。STI区56包括线性区48和圆柱区46。在本实施例中，圆柱区46中的STI宽度42近似为线性区48中的STI宽度42的1.5倍。这会减轻圆柱区46中的电场和避免穿通耗尽。
图5表示具有线性2D布局的EDNMOS器件60的表面布局的一个示意实施例，其也提供了减小的高电压泄漏。在这种情况中，栅极区66位于源极区62和漏极区64之间。在器件60中，p+体触点(由宽度68定义的)被向上拉至栅极边缘以沿晶体管的边缘形成用于使源极62失活的减活源极区69。这种布置提供了更好的高电压性能，即降低了高电压泄漏和沟道穿通电流。图5还示出对于漏极扩展HNW72在STI74上的重叠部分70。这是一个正重叠70，然而负重叠可以给出更好的性能。
用于形成这种器件的示意剂量和材料参数如下。可使用大约4微米厚的p--外延层21(图1)来制造p++基片23。可以利用大约5.0-5.4nm的GO1氧化物厚度或大约12.3-15nm的GO2氧化物厚度。STI12可具有大约0.35-0.45微米的深度。图6表示用于5V和2.5V部件的示意倒阱表，其包括种类、剂量和能量。在所述器件晶胞内摹制n型和p型阱注入物用以形成源极和漏极触点。所述器件可例如包括用于基片隔离的DN阱注入物1-2MeV 5e12cm-231磷和用于深度隔离的DP阱注入物500-700keV 1e13cm-211硼(其中，31磷和11硼是注入物种类，即分别用于n型和p型掺杂的磷和硼)。
所述制造工艺中包括的步骤基本上如下：
(1)在外延层和基片层上形成第一种类型的深阱注入物22；
(2)在漏极区18和一部分栅极区20下面形成摹制的第一种类型的第一阱注入物14；
(3)在源极区16下面形成摹制的第二种类型的第二阱注入物24；
(4)在漏极区18和栅极区20之间的第一阱注入物14中形成浅槽隔离(STI)区12以允许高电压操作；和
(5)其中使用从下述的组中选择的基线互补金属氧化物半导体(CMOS)流程来制造该器件，所述组包括：
(a)5伏基线CMOS流程，其中利用近似12.3-15.0nm的栅极氧化物厚度，并且所述第一和第二阱注入物包括高电压p阱注入物(24)和高电压n阱注入物(14)；和
(b)2.5伏基线CMOS工艺流程，其中利用近似5.0-5.4nm的栅极氧化物厚度，并且所述第一和第二阱注入物包括n型阱(NW)和p型阱(PW)。
注意不对称互补器件是增强模式器件，这意味着通过设计在零栅极-源极电压下没有电流。这与耗尽模式器件正相反，在耗尽模式器件中在零栅极-源极电压下存在电流。另外，耗尽模式构成是通过有意重叠NW和PW注入物以形成补偿沟道区获得的，而增强模式器件通过限定不允许在沟道区中重叠NW和PW。
为了阐释和说明的目的，已经给出了本发明的说明。但并不意指将本发明尽述或限制为所披露的精确形式，很明显，能够做出许多修改和变形。这种对于本领域技术人员来说可以说是明显的修改和变形都意在包括在由所附权利要求所定义的本发明的范围内。

Claims (16)

1.一种不对称互补金属氧化物半导体CMOS器件(10)，包括：
浅槽隔离STI区(12)，其在器件单元的漏极区(18)和栅极区(20)之间形成电介质以允许高电压操作；和
在所述器件单元内图案化的第一导电类型的第一阱(14)和第二导电类型的第二阱(24)，
其中，所述第一导电类型的第一阱形成于漏极区(18)和一部分栅极区(20)之下，
浅槽隔离区(12)形成于与漏极位置相邻的栅极位置的一部分之下的第一阱中；以及
所述第二导电类型的第二阱形成于源极区(16)之下。
2.根据权利要求1所述的不对称CMOS器件，还包括用于提供衬底隔离的深N阱(22)，其中所述深N阱通过注入能量为1-2MeV、注入剂量为5e12cm-2、注入种类为31磷来形成。
3.根据权利要求1所述的不对称CMOS器件，还包括被成形为环形的表面布局，其中漏极区位于所述环的中心，而STI区位于漏极区周围。
4.根据权利要求3所述的不对称CMOS器件，其中STI区的表面布局包括线性部分(48)和圆角部分(46)，并且其中所述圆角部分(46)的宽度(42)是所述线性部分(48)的宽度(44)的至少1.2倍。
5.根据权利要求1所述的不对称CMOS器件，还包括线性的表面布局，其包括沿表面布局的器件边缘布置的减活源极区(69)。
6.根据权利要求1所述的不对称CMOS器件，其中所述不对称CMOS器件是使用5伏基线互补金属氧化物半导体工艺流程形成的，其中利用了12.3-15.0nm的栅极氧化物厚度，并且所述第一阱包括高电压n阱(14)，所述第二阱包括高电压p阱(24)。
7.根据权利要求1所述的不对称CMOS器件，其中所述不对称CMOS器件是使用2.5伏基线互补金属氧化物半导体工艺流程形成的，其中利用了5.0-5.4nm的栅极氧化物厚度，并且所述第一阱包括n型阱，所述第二阱包括p型阱。
8.一种形成不对称互补金属氧化物半导体CMOS器件(10)的方法，包括步骤：
形成第一导电类型的深阱(22)；
在所述深阱上面而在漏极区(18)和一部分栅极区(20)下面形成第一导电类型的第一阱(14)；
在与漏极位置相邻的栅极位置的一部分下面、在第一阱中形成浅槽隔离STI区(12)；
在源极区(16)下面形成第二导电类型的第二阱(24)。
9.根据权利要求8所述的方法，其中所述STI区为0.35-0.45微米厚。
10.根据权利要求8所述的方法，其中所述不对称CMOS器件(10)是使用5伏基线互补金属氧化物半导体工艺流程形成的，其中利用了12.3-15.0nm的栅极氧化物厚度，并且所述第一阱包括高电压n阱(14)，所述第二阱包括高电压p阱(24)。
11.根据权利要求8所述的方法，其中所述不对称CMOS器件(10)是使用2.5伏基线互补金属氧化物工艺流程形成的，其中利用了5.0-5.4nm的栅极氧化物厚度，并且所述第一阱包括n型阱，所述第二阱包括p型阱。
12.根据权利要求8所述的方法，其中使用注入能量为1-2MeV、注入剂量为5e12cm-2、注入种类为31磷来形成所述深阱以提供衬底隔离。
13.根据权利要求8所述的方法，其中所述不对称CMOS器件的表面布局被成形为环形，其中漏极区位于所述环的中心，而STI区位于漏极区周围。
14.根据权利要求13所述的方法，其中STI区的表面布局包括线性部分(48)和圆角部分(46)，并且其中所述圆角部分(46)的宽度(42)是所述线性部分的宽度(44)的至少1.2倍。
15.根据权利要求8所述的方法，其中所述不对称CMOS器件的表面布局为线性的，并且所述表面布局包括沿表面布局的器件边缘布置的减活源极区。
16.一种形成不对称互补金属氧化物半导体CMOS器件(10)的方法，包括步骤：
在外延层和衬底层上面形成第一导电类型的深阱(22)；
在漏极区(18)和一部分栅极区(20)下面形成图案化的第一导电类型的第一阱(14)；
在源极区(16)下面形成图案化的第二导电类型的第二阱(24)；
在漏极区(18)和栅极区(20)之间在第一阱中形成浅槽隔离STI区(12)以允许高电压操作，其中STI区(12)形成于与漏极位置相邻的栅极位置的一部分之下的第一阱中；以及；
其中使用从下述的组中选择的基线CMOS流程来制造所述不对称CMOS器件，所述组包括：
5伏基线CMOS工艺流程，其中利用了12.3-15.0nm的栅极氧化物厚度，并且所述第一阱包括高电压n阱(14)，所述第二阱包括高电压p阱(24)；和
2.5伏基线CMOS工艺流程，其中利用了5.0-5.4nm的栅极氧化物厚度，并且所述第一阱包括n型阱，所述第二阱包括p型阱。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007072304A2 (en) * 2005-12-19 2007-06-28 Nxp B.V. Integrated high voltage diode and manufacturing method therefof
US8378422B2 (en) * 2009-02-06 2013-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge protection device comprising a plurality of highly doped areas within a well
US8575702B2 (en) * 2009-11-27 2013-11-05 Magnachip Semiconductor, Ltd. Semiconductor device and method for fabricating semiconductor device
US8461647B2 (en) * 2010-03-10 2013-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having multi-thickness gate dielectric
JP5492610B2 (ja) * 2010-03-11 2014-05-14 パナソニック株式会社 半導体装置及びその製造方法
JP5683163B2 (ja) 2010-07-29 2015-03-11 ルネサスエレクトロニクス株式会社 半導体装置
CN102610521B (zh) * 2011-01-19 2014-10-08 上海华虹宏力半导体制造有限公司 非对称高压mos器件的制造方法及结构
US8536648B2 (en) * 2011-02-03 2013-09-17 Infineon Technologies Ag Drain extended field effect transistors and methods of formation thereof
US8846492B2 (en) * 2011-07-22 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a stressor and method of forming the same
US8822295B2 (en) * 2012-04-03 2014-09-02 International Business Machines Corporation Low extension dose implants in SRAM fabrication
CN103839803B (zh) * 2012-11-23 2018-11-06 中国科学院微电子研究所 一种平面型igbt结构的制备方法
CN103839802B (zh) * 2012-11-23 2018-09-11 中国科学院微电子研究所 一种沟槽型igbt结构的制作方法
CN109166924B (zh) * 2018-08-28 2020-07-31 电子科技大学 一种横向mos型功率半导体器件及其制备方法
US11049967B2 (en) * 2018-11-02 2021-06-29 Texas Instruments Incorporated DMOS transistor having thick gate oxide and STI and method of fabricating
CN111508843B (zh) * 2019-01-31 2023-07-14 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0897411A (ja) * 1994-09-21 1996-04-12 Fuji Electric Co Ltd 横型高耐圧トレンチｍｏｓｆｅｔおよびその製造方法
US5953599A (en) * 1997-06-12 1999-09-14 National Semiconductor Corporation Method for forming low-voltage CMOS transistors with a thin layer of gate oxide and high-voltage CMOS transistors with a thick layer of gate oxide
US6172401B1 (en) * 1998-06-30 2001-01-09 Intel Corporation Transistor device configurations for high voltage applications and improved device performance
US6144069A (en) * 1999-08-03 2000-11-07 United Microelectronics Corp. LDMOS transistor
US6548874B1 (en) * 1999-10-27 2003-04-15 Texas Instruments Incorporated Higher voltage transistors for sub micron CMOS processes
US6501139B1 (en) * 2001-03-30 2002-12-31 Matrix Semiconductor, Inc. High-voltage transistor and fabrication process
WO2002095833A1 (en) * 2001-05-15 2002-11-28 Virtual Silicon Technology, Inc. High voltage n-channel ldmos devices built in a deep submicron cmos process
US6593621B2 (en) * 2001-08-23 2003-07-15 Micrel, Inc. LDMOS field effect transistor with improved ruggedness in narrow curved areas
ITTO20030013A1 (it) * 2003-01-14 2004-07-15 St Microelectronics Srl Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione.
US6876035B2 (en) * 2003-05-06 2005-04-05 International Business Machines Corporation High voltage N-LDMOS transistors having shallow trench isolation region
US6900101B2 (en) * 2003-06-13 2005-05-31 Texas Instruments Incorporated LDMOS transistors and methods for making the same
US6825531B1 (en) * 2003-07-11 2004-11-30 Micrel, Incorporated Lateral DMOS transistor with a self-aligned drain region
US7005354B2 (en) * 2003-09-23 2006-02-28 Texas Instruments Incorporated Depletion drain-extended MOS transistors and methods for making the same
US6924531B2 (en) * 2003-10-01 2005-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. LDMOS device with isolation guard rings
SE0303099D0 (sv) * 2003-11-21 2003-11-21 Infineon Technologies Ag Method in the fabrication of a monolithically integrated high frequency circuit
US7145203B2 (en) * 2004-04-26 2006-12-05 Impinj, Inc. Graded-junction high-voltage MOSFET in standard logic CMOS
US7151296B2 (en) * 2004-11-03 2006-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage lateral diffused MOSFET device
US20060108641A1 (en) * 2004-11-19 2006-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Device having a laterally graded well structure and a method for its manufacture

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