JP5426051B2 - 回路基板内に電気絶縁部を設けるための方法 - Google Patents
回路基板内に電気絶縁部を設けるための方法 Download PDFInfo
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- JP5426051B2 JP5426051B2 JP2013508370A JP2013508370A JP5426051B2 JP 5426051 B2 JP5426051 B2 JP 5426051B2 JP 2013508370 A JP2013508370 A JP 2013508370A JP 2013508370 A JP2013508370 A JP 2013508370A JP 5426051 B2 JP5426051 B2 JP 5426051B2
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- notches
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- 238000000034 method Methods 0.000 title claims description 29
- 238000010292 electrical insulation Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims description 14
- 238000003754 machining Methods 0.000 claims description 6
- 239000012530 fluid Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0736—Methods for applying liquids, e.g. spraying
- H05K2203/0746—Local treatment using a fluid jet, e.g. for removing or cleaning material; Providing mechanical pressure using a fluid jet
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Laser Beam Processing (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
2 切欠き
3 切欠き
4 領域
5 領域
6 導電層
7 端部
7′端部
7″ 端部
7′″ 端部
8 端部
8′ 端部
8″ 端部
8′″ 端部
9 ストリップ状領域
9′ ストリップ状領域
Claims (8)
- 溝状の切欠き(2,3)が、加工進路に沿って熱エネルギーの流入によって導電層(6)内に選択的に設けられ、同じ又は異なる複数の切欠き(2,3)の端部(7,7′,8,8′)が互いに結合されることによって、基板上の前記導電層(6)の異なる複数の領域(4,5)間に1つの切欠き(2,3)を設けることで回路基板(1)内に電気絶縁部を設けるための方法において、
最初に、前記導電層(6)のストリップ状領域(9,9′)が、1つ又は異なる複数の切欠き(2,3)の結合すべき複数の端部(7,7′,8,8′)間に保持されているように、当該複数の端部(7,7′,8,8′)が、前記異なる複数の領域(4,5)を絶縁するために重なり合うことなしに互いに平行に配置されることを特徴とする方法。 - 前記複数の端部(7,7′,8,8′)は、前記複数の切欠き(2,3)の湾曲部分又は屈曲部分として設けられることを特徴とする請求項1に記載の方法。
- 結合すべき前記複数の切欠き(2,3)は、平行な加工進路に沿って設けられ、それぞれの前記端部(7,7′,8,8′)は、これらの加工進路に対してほぼ直角に設けられることを特徴とする請求項1又は2に記載の方法。
- 前記複数の端部(7,7′,8,8′)の少なくとも一部が、平行な複数の直線に沿って延在し、当該複数の端部の少なくとも一部自体の間で一定の幅の層の前記ストリップ状領域(9,9′)を包囲することを特徴とする請求項1〜3のいずれか1項に記載の方法。
- 前記端部(7,7′,8,8′)間で包囲された前記ストリップ状領域(9,9′)は、流体の流れによって除去されることを特徴とする請求項1に記載の方法。
- 各端部(7,7′,8,8′)は、その主延在部分に沿って一定の幅を有することを特徴とする請求項1〜5のいずれか1項に記載の方法。
- 追加の1つの弱い部分つまり切欠きが、前記端部(7,7′,8,8′)間の前記基板(6)上の前記導電層(6)の1つの領域の、特に幾何学的な中心内に設けられることを特徴とする請求項1〜6のいずれか1項に記載の方法。
- 前記熱エネルギーの流入は、レーザービームによって実施されることを特徴とする請求項1〜7のいずれか1項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102010019407.7 | 2010-05-04 | ||
DE102010019407A DE102010019407B4 (de) | 2010-05-04 | 2010-05-04 | Verfahren zum Einbringen elektrischer Isolierungen in Leiterplatten |
PCT/DE2011/075048 WO2011137897A2 (de) | 2010-05-04 | 2011-03-23 | Verfahren zum einbringen elektrischer isolierungen in leiterplatten |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013528937A JP2013528937A (ja) | 2013-07-11 |
JP5426051B2 true JP5426051B2 (ja) | 2014-02-26 |
Family
ID=44629534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013508370A Active JP5426051B2 (ja) | 2010-05-04 | 2011-03-23 | 回路基板内に電気絶縁部を設けるための方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US9021691B2 (ja) |
EP (1) | EP2567602B1 (ja) |
JP (1) | JP5426051B2 (ja) |
KR (1) | KR101503580B1 (ja) |
CN (1) | CN102870507B (ja) |
DE (1) | DE102010019407B4 (ja) |
TW (1) | TWI478639B (ja) |
WO (1) | WO2011137897A2 (ja) |
Family Cites Families (31)
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US3214315A (en) | 1962-03-28 | 1965-10-26 | Burton Solomon | Method for forming stamped electrical circuits |
US3587067A (en) * | 1968-07-17 | 1971-06-22 | Philips Corp | Method of manufacturing memory matrices |
US4228514A (en) | 1979-04-16 | 1980-10-14 | Bell Telephone Laboratories, Incorporated | Method and system for determining the wear of a drill bit in real time |
DE3245272A1 (de) * | 1982-12-07 | 1984-06-07 | Ernst Roederstein Spezialfabrik für Kondensatoren GmbH, 8300 Landshut | Verfahren zur herstellung miniaturisierter dick- und duennschichtschaltungen |
US5338645A (en) * | 1986-06-16 | 1994-08-16 | Motorola, Inc. | Three dimensional printed circuits |
KR900004783B1 (ko) * | 1987-07-01 | 1990-07-05 | 가와사끼 쥬고교 주식회사 | 이종재료의 중합체 및 그 제조방법 |
JPS6473090A (en) * | 1987-09-10 | 1989-03-17 | Hitachi Plant Eng & Constr Co | Local etching method |
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JP3399590B2 (ja) | 1993-08-04 | 2003-04-21 | 富士通株式会社 | 配線の切断装置 |
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JP3153682B2 (ja) * | 1993-08-26 | 2001-04-09 | 松下電工株式会社 | 回路板の製造方法 |
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TW284907B (en) | 1995-06-07 | 1996-09-01 | Cauldron Lp | Removal of material by polarized irradiation and back side application for radiation |
WO1997019580A1 (en) * | 1995-11-24 | 1997-05-29 | Philips Electronics N.V. | Method of selectively removing a metallic layer from a non-metallic substrate |
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-
2010
- 2010-05-04 DE DE102010019407A patent/DE102010019407B4/de not_active Expired - Fee Related
-
2011
- 2011-03-23 EP EP11738948.6A patent/EP2567602B1/de active Active
- 2011-03-23 KR KR1020127031654A patent/KR101503580B1/ko active IP Right Grant
- 2011-03-23 JP JP2013508370A patent/JP5426051B2/ja active Active
- 2011-03-23 WO PCT/DE2011/075048 patent/WO2011137897A2/de active Application Filing
- 2011-03-23 CN CN201180022189.9A patent/CN102870507B/zh active Active
- 2011-03-23 US US13/695,888 patent/US9021691B2/en active Active
- 2011-04-29 TW TW100115006A patent/TWI478639B/zh active
Also Published As
Publication number | Publication date |
---|---|
WO2011137897A2 (de) | 2011-11-10 |
CN102870507B (zh) | 2015-07-15 |
DE102010019407A9 (de) | 2013-04-11 |
JP2013528937A (ja) | 2013-07-11 |
DE102010019407A1 (de) | 2011-11-10 |
DE102010019407B4 (de) | 2013-06-27 |
TW201212751A (en) | 2012-03-16 |
US20130055566A1 (en) | 2013-03-07 |
KR20130030268A (ko) | 2013-03-26 |
TWI478639B (zh) | 2015-03-21 |
WO2011137897A3 (de) | 2011-12-29 |
KR101503580B1 (ko) | 2015-03-17 |
EP2567602A2 (de) | 2013-03-13 |
US9021691B2 (en) | 2015-05-05 |
EP2567602B1 (de) | 2014-02-26 |
CN102870507A (zh) | 2013-01-09 |
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