US20120273261A1 - Circuit substrate having a circuit pattern and method for making the same - Google Patents
Circuit substrate having a circuit pattern and method for making the same Download PDFInfo
- Publication number
- US20120273261A1 US20120273261A1 US13/547,494 US201213547494A US2012273261A1 US 20120273261 A1 US20120273261 A1 US 20120273261A1 US 201213547494 A US201213547494 A US 201213547494A US 2012273261 A1 US2012273261 A1 US 2012273261A1
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- United States
- Prior art keywords
- recess
- active metal
- metal layer
- layer structure
- insulative substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/362—Laser etching
- B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/362—Laser etching
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/36—Removing material
- B23K26/40—Removing material taking account of the properties of the material involved
- B23K26/402—Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1646—Characteristics of the product obtained
- C23C18/165—Multilayered product
- C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1689—After-treatment
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/18—Pretreatment of the material to be coated
- C23C18/20—Pretreatment of the material to be coated of organic surfaces, e.g. resins
- C23C18/2006—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30
- C23C18/2013—Pretreatment of the material to be coated of organic surfaces, e.g. resins by other methods than those of C23C18/22 - C23C18/30 by mechanical pretreatment, e.g. grinding, sanding
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/12—Electroplating: Baths therefor from solutions of nickel or cobalt
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/46—Electroplating: Baths therefor from solutions of silver
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/48—Electroplating: Baths therefor from solutions of gold
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
- C25F5/00—Electrolytic stripping of metallic layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/067—Etchants
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/185—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method by making a catalytic pattern by photo-imaging
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/34—Coated articles, e.g. plated or painted; Surface treated articles
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/40—Semiconductor devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2103/00—Materials to be soldered, welded or cut
- B23K2103/50—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26
- B23K2103/56—Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26 semiconducting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09036—Recesses or grooves in insulating substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/09363—Conductive planes wherein only contours around conductors are removed for insulation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0392—Pretreatment of metal, e.g. before finish plating, etching
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/107—Using laser light
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Definitions
- the invention relates to a circuit substrate having a circuit pattern and a method for making the same, and more particularly to a circuit substrate having a circuit pattern formed in a recess in a substrate.
- methods of forming a circuit substrate having a circuit pattern on an insulative substrate can be performed by insert molding the circuit pattern into the insulative substrate or by laminating the circuit pattern with the insulative substrate.
- the aforesaid conventional methods can undesirably increase the thickness of the circuit substrate.
- adjustment of manufacturing equipments in the processing steps of the conventional method is time consuming.
- U.S. Pat. No. 4,865,873 discloses a method for making a circuit substrate having a circuit pattern on a substrate.
- the method includes forming an insulating layer on a substrate, forming a water-soluble layer on the insulating layer, forming a patterned hole extending through the water-soluble layer and the insulating layer by laser ablation, forming an active metal layer in the patterned hole and on the water-soluble layer, and simultaneously electroless depositing a primary metal layer on the active metal layer and dissolving the water-soluble layer in an aqueous plating solution.
- the active metal layer covers a hole wall of the patterned hole as well as the water-soluble layer, electroless plating of the primary metal layer takes place not only at the hole wall but also at the surface of the water-soluble layer, which is undesirable.
- the water-soluble layer will be gradually dissolved in the aqueous plating solution during electroless plating, it can have an adverse effect on electroless plating.
- the thickness of the circuit substrate thus formed is considerably increased.
- an object of the present invention is to provide a circuit substrate that can overcome the aforesaid drawbacks associated with the prior art.
- a circuit substrate that comprises: an insulative substrate having a top surface and formed with a pattern of a recess that is indented from the top surface, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer that is disposed within the recess, that is formed on the bottom wall surface of the recess-defining wall, and that is spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating, a pattern of the patterned active metal layer corresponding in shape to the pattern of the recess; and a primary metal layer plated on the patterned metallic layer structure.
- a method for making a circuit substrate having a circuit pattern comprises: (a) providing an insulative substrate having a top surface; (b) forming a pattern of a recess in the insulative substrate such that the recess is indented from the top surface, the recess being defined by a recess-defining wall having a bottom wall surface and a surrounding wall surface extending upwardly from the bottomwall surface; (c) forming a metallic layer structure on the recess-defining wall of the recess and the top surface of the insulative substrate, the metallic layer structure including at least one active metal layer containing an active metal capable of initiating electroless plating; (d) removing a portion of the metallic layer structure that is disposed along a peripheral edge of the bottom wall surface of the recess-defining wall so as to form the metallic layer structure into a first region which is disposed on the bottom wall surface, and a second region which is physically separated from the first region; and (e) plating
- FIG. 1 is a perspective view illustrating a first step of a method for making the first preferred embodiment of a circuit substrate according to the present invention
- FIG. 2 is a perspective view illustrating a second step of the method for making the first preferred embodiment
- FIG. 3 is a schematic view taken along line III-III of FIG. 2 ;
- FIG. 4 is a perspective view illustrating a third step of the method for making the first preferred embodiment
- FIG. 5 is a schematic view taken along line V-V of FIG. 4 ;
- FIG. 6 is a schematic view illustrating a fourth step of the method for making the first preferred embodiment
- FIG. 7 is a schematic view illustrating a fifth step of the method for making the first preferred embodiment
- FIG. 8 is a perspective view illustrating a sixth step of the method for making the first preferred embodiment
- FIG. 9 is a schematic view taken along line IX-IX of FIG. 8 ;
- FIG. 10 is a schematic view illustrating a first step of a method for making the second preferred embodiment of a circuit substrate according to the present invention.
- FIG. 11 is a schematic view illustrating a second step of the method for making the second preferred embodiment
- FIG. 12 is a schematic view illustrating a third step of the method for making the second preferred embodiment
- FIG. 13 is a schematic view illustrating a fourth step of the method for making the second preferred embodiment
- FIG. 14 is a schematic view illustrating a fifth step of the method for making the second preferred embodiment
- FIG. 15 is a schematic view illustrating a first step of a method for making the third preferred embodiment of a circuit substrate according to the present invention.
- FIG. 16 is a schematic view illustrating a second step of the method for making the third preferred embodiment
- FIG. 17 is a schematic view illustrating a third step of the method for making the third preferred embodiment
- FIG. 18 is a schematic view illustrating a fourth step of the method for making the third preferred embodiment.
- FIG. 19 is a schematic view illustrating a fifth step of the method for making the third preferred embodiment.
- FIGS. 8 and 9 illustrate the first preferred embodiment of a circuit substrate 100 according to the present invention.
- the circuit substrate 100 includes: an insulative substrate 2 having a top surface 21 and formed with a pattern of a recess 20 that is indented from the top surface 21 , the recess 20 being defined by a recess-defining wall 20 ′ that has a bottom wall surface 201 and a surrounding wall surface 202 extending upwardly from the bottom wall surface 201 ; a patterned metallic layer structure 5 including at least one patterned active metal layer 3 disposed within the recess 20 , formed on the bottom wall surface 201 of the recess-defining wall 20 ′, and spaced apart from the surrounding wall surface 202 of the recess-defining wall 20 ′ by a gap 203 , a patterned active metal layer 3 containing an active metal capable of initiating electroless plating, the pattern of the patterned active metal layer 3 corresponding in shape to the pattern of the recess 20 ; and a primary metal layer 4 electroplated on the
- the patterned metallic layer structure 5 and the primary metal layer 4 cooperatively form a circuit pattern 10 that corresponds in shape to the pattern of the recess 20 .
- the circuit pattern 10 has a top surface 101 substantially flush with or disposed slightly above the top surface 21 of the substrate 2 .
- FIGS. 1 to 9 illustrate consecutive steps of a method for making the circuit substrate 100 of the first preferred embodiment according to the present invention.
- the method includes the steps of: (a) providing an insulative substrate 2 having a top surface 21 (see FIG. 1 ); (b) forming a pattern of a recess 20 in the insulative substrate 2 such that the recess 20 is indented from the top surface 21 (see FIGS. 2 and 3 ); (c) forming a metallic layer structure 5 ′ on a recess-defining wall 20 ′ of the recess 20 and the top surface 21 of the insulative substrate 2 , the metallic layer structure 5 ′ including at least one active metal layer 3 ′ containing an active metal capable of initiating electroless plating (see FIGS.
- the active metal of the active metal layer 3 ′ is a reduced active metal.
- the metallic layer structure 5 ′ is formed on the recess-defining wall 20 ′ of the recess 20 and the top surface 21 of the insulative substrate 2 in step (c) by immersing the insulative substrate 2 into an active metal solution containing a non-reduced active metal (not shown) so as to form a non-reduced metal layer containing the non-reduced active metal on the recess-defining wall 20 ′ of the recess 20 and the top surface 21 of the insulative substrate 2 and then reducing the non-reduced active metal of the non-reduced metal layer so as to form the active metal layer 3 ′ containing the reduced active metal on the recess-de fining wall 20 ′ of the recess 20 and the top surface 21 of the insulative substrate 2 .
- the primary metal layer 4 is plated on the first region 51 of the metallic layer structure 5 ′ by electroplating techniques.
- the non-reduced active metal of the non-reduced metal layer is in the form of active metal colloid particles or metal ions.
- the active metal is selected from the group consisting of palladium, rhodium, platinum, iridium, osmium, gold, nickel, iron, and combinations thereof.
- the active metal solution containing the non-reduced active metal is palladium salt solution or palladium-tin colloid solution.
- the primary metal layer 4 is made from a metal selected from the group consisting of copper, nickel, silver, and gold.
- the insulative substrate 2 is made from a material selected from the group consisting of polycarbonate, a combination of acryl resin and acrylonitrile butadiene styrene (ABS) resin, and a combination of polycarbonate and ABS resin.
- ABS acrylonitrile butadiene styrene
- the recess 20 in the insulative substrate 2 is formed by laser or plasma ablation.
- the closed-loop portion of the metallic layer structure 5 ′ is removed by laser ablation.
- FIG. 14 illustrates the second preferred embodiment of a circuit substrate 100 according to the present invention.
- the second preferred embodiment differs from the previous embodiment in that the active metal of the patterned active metal layer 3 is a non-reduced active metal, that the patterned metallic layer structure 5 further includes an intermediate metal layer 6 which is electroless plated on the patterned active metal layer 3 and which has a pattern corresponding to that of the active metal layer 3 , and that the primary metal layer 4 is electroplated on the intermediate metal layer 6 .
- the patterned metallic layer structure 5 and the primary metal layer 4 cooperatively form the circuit pattern 10 .
- FIGS. 10 to 14 illustrate consecutive steps of a method for making the circuit substrate 100 of the second preferred embodiment according to the present invention.
- the method includes the steps of: forming a pattern of a recess 20 in the insulative substrate 2 (see FIG. 10 ); forming a metallic layer structure 5 ′ on a recess-defining wall 20 ′ of the recess 20 and a top surface 21 of the insulative substrate 2 by immersing the insulative substrate 2 into an active metal solution containing a non-reduced active metal (not shown) so as to form an active metal layer 3 ′ containing the non-reduced active metal on the recess-defining wall 20 ′ of the recess 20 and the top surface 21 of the insulative substrate 2 (see FIG.
- the active metal layer 3 ′ of the first region 51 ′ of the metallic layer structure 5 ′ defining the patterned active metal layer 3 of FIG. 14 ; (e) electroplating a primary metal layer 4 on the intermediate metal layer 6 of the first region 51 ′ of the metallic layer structure 5 ′ (see FIG. 13 ); and (f) removing the second region 52 ′ of the metallic layer structure 5 ′ from the insulative substrate 2 by electrolysis (see FIG. 14 ).
- FIG. 19 illustrates the third preferred embodiment of a circuit substrate 100 according to the present invention.
- the third preferred embodiment differs from the first preferred embodiment in that the active metal of the patterned active metal layer 3 is a non-reduced active metal, that the primary metal layer 4 is electroless plated on the patterned active metal layer 3 , and that a top metal layer 7 is formed on the primary metal layer 4 .
- the third preferred embodiment has a structure similar to that of the second preferred embodiment as the primary metal layer 4 and the top metal layer 7 of the third preferred embodiment are equivalent to the intermediate metal layer 6 and the primary metal layer 4 of the second preferred embodiment, respectively.
- FIGS. 15 to 19 illustrate consecutive steps of a method for making the circuit substrate 100 of the third preferred embodiment according to the present invention.
- the method includes the steps of: forming a pattern of a recess 20 in the insulative substrate 2 (see FIG. 15 ); forming a metallic layer structure 5 ′ on a recess-defining wall 20 ′ of the recess 20 and a top surface 21 of the insulative substrate 2 by immersing the insulative substrate 2 into an active metal solution containing a non-reduced active metal (not shown) so as to form an active metal layer 3 ′ containing the non-reduced active metal on the recess-defining wall 20 ′ of the recess 20 and the top surface 21 of the insulative substrate 2 (see FIG.
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Abstract
A circuit substrate includes: an insulative substrate formed with a pattern of a recess, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer disposed within the recess, formed on the bottom wall surface of the recess-defining wall, and spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating; and a primary metal layer plated on the patterned metallic layer structure.
Description
- This application is a continuation-in-part (CIP) of U.S. patent application Ser. No. 13/035,531, filed on Feb. 25, 2011, the entire disclosure of which is incorporated herein by reference.
- 1. Field of the Invention
- The invention relates to a circuit substrate having a circuit pattern and a method for making the same, and more particularly to a circuit substrate having a circuit pattern formed in a recess in a substrate.
- 2. Description of the Related Art
- Conventionally, methods of forming a circuit substrate having a circuit pattern on an insulative substrate can be performed by insert molding the circuit pattern into the insulative substrate or by laminating the circuit pattern with the insulative substrate. However, the aforesaid conventional methods can undesirably increase the thickness of the circuit substrate. Moreover, when the circuit pattern is modified or changed, adjustment of manufacturing equipments in the processing steps of the conventional method is time consuming.
- U.S. Pat. No. 4,865,873 discloses a method for making a circuit substrate having a circuit pattern on a substrate. The method includes forming an insulating layer on a substrate, forming a water-soluble layer on the insulating layer, forming a patterned hole extending through the water-soluble layer and the insulating layer by laser ablation, forming an active metal layer in the patterned hole and on the water-soluble layer, and simultaneously electroless depositing a primary metal layer on the active metal layer and dissolving the water-soluble layer in an aqueous plating solution. Since the active metal layer covers a hole wall of the patterned hole as well as the water-soluble layer, electroless plating of the primary metal layer takes place not only at the hole wall but also at the surface of the water-soluble layer, which is undesirable. Although the water-soluble layer will be gradually dissolved in the aqueous plating solution during electroless plating, it can have an adverse effect on electroless plating. In addition, the thickness of the circuit substrate thus formed is considerably increased.
- Therefore, an object of the present invention is to provide a circuit substrate that can overcome the aforesaid drawbacks associated with the prior art.
- According to one aspect of the present invention, there is provided a circuit substrate that comprises: an insulative substrate having a top surface and formed with a pattern of a recess that is indented from the top surface, the recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface; a patterned metallic layer structure including at least a patterned active metal layer that is disposed within the recess, that is formed on the bottom wall surface of the recess-defining wall, and that is spaced apart from the surrounding wall surface of the recess-defining wall, the patterned active metal layer containing an active metal capable of initiating electroless plating, a pattern of the patterned active metal layer corresponding in shape to the pattern of the recess; and a primary metal layer plated on the patterned metallic layer structure.
- According to another aspect of the present invention, there is provided a method for making a circuit substrate having a circuit pattern. The method comprises: (a) providing an insulative substrate having a top surface; (b) forming a pattern of a recess in the insulative substrate such that the recess is indented from the top surface, the recess being defined by a recess-defining wall having a bottom wall surface and a surrounding wall surface extending upwardly from the bottomwall surface; (c) forming a metallic layer structure on the recess-defining wall of the recess and the top surface of the insulative substrate, the metallic layer structure including at least one active metal layer containing an active metal capable of initiating electroless plating; (d) removing a portion of the metallic layer structure that is disposed along a peripheral edge of the bottom wall surface of the recess-defining wall so as to form the metallic layer structure into a first region which is disposed on the bottom wall surface, and a second region which is physically separated from the first region; and (e) plating a primary metal layer on the first region of the metallic layer structure.
- In drawings which illustrate embodiments of the invention,
-
FIG. 1 is a perspective view illustrating a first step of a method for making the first preferred embodiment of a circuit substrate according to the present invention; -
FIG. 2 is a perspective view illustrating a second step of the method for making the first preferred embodiment; -
FIG. 3 is a schematic view taken along line III-III ofFIG. 2 ; -
FIG. 4 is a perspective view illustrating a third step of the method for making the first preferred embodiment; -
FIG. 5 is a schematic view taken along line V-V ofFIG. 4 ; -
FIG. 6 is a schematic view illustrating a fourth step of the method for making the first preferred embodiment; -
FIG. 7 is a schematic view illustrating a fifth step of the method for making the first preferred embodiment; -
FIG. 8 is a perspective view illustrating a sixth step of the method for making the first preferred embodiment; -
FIG. 9 is a schematic view taken along line IX-IX ofFIG. 8 ; -
FIG. 10 is a schematic view illustrating a first step of a method for making the second preferred embodiment of a circuit substrate according to the present invention; -
FIG. 11 is a schematic view illustrating a second step of the method for making the second preferred embodiment; -
FIG. 12 is a schematic view illustrating a third step of the method for making the second preferred embodiment; -
FIG. 13 is a schematic view illustrating a fourth step of the method for making the second preferred embodiment; -
FIG. 14 is a schematic view illustrating a fifth step of the method for making the second preferred embodiment; -
FIG. 15 is a schematic view illustrating a first step of a method for making the third preferred embodiment of a circuit substrate according to the present invention; -
FIG. 16 is a schematic view illustrating a second step of the method for making the third preferred embodiment; -
FIG. 17 is a schematic view illustrating a third step of the method for making the third preferred embodiment; -
FIG. 18 is a schematic view illustrating a fourth step of the method for making the third preferred embodiment; and -
FIG. 19 is a schematic view illustrating a fifth step of the method for making the third preferred embodiment. - Before the present invention is described in greater detail with reference to the accompanying preferred embodiments, it should be noted herein that like elements are denoted by the same reference numerals throughout the disclosure.
-
FIGS. 8 and 9 illustrate the first preferred embodiment of acircuit substrate 100 according to the present invention. Thecircuit substrate 100 includes: aninsulative substrate 2 having atop surface 21 and formed with a pattern of arecess 20 that is indented from thetop surface 21, therecess 20 being defined by a recess-definingwall 20′ that has abottom wall surface 201 and a surroundingwall surface 202 extending upwardly from thebottom wall surface 201; a patternedmetallic layer structure 5 including at least one patternedactive metal layer 3 disposed within therecess 20, formed on thebottom wall surface 201 of the recess-definingwall 20′, and spaced apart from the surroundingwall surface 202 of the recess-definingwall 20′ by agap 203, a patternedactive metal layer 3 containing an active metal capable of initiating electroless plating, the pattern of the patternedactive metal layer 3 corresponding in shape to the pattern of therecess 20; and aprimary metal layer 4 electroplated on the patternedmetallic layer structure 5. The patternedmetallic layer structure 5 and theprimary metal layer 4 cooperatively form acircuit pattern 10 that corresponds in shape to the pattern of therecess 20. Preferably, thecircuit pattern 10 has atop surface 101 substantially flush with or disposed slightly above thetop surface 21 of thesubstrate 2. -
FIGS. 1 to 9 illustrate consecutive steps of a method for making thecircuit substrate 100 of the first preferred embodiment according to the present invention. The method includes the steps of: (a) providing aninsulative substrate 2 having a top surface 21 (seeFIG. 1 ); (b) forming a pattern of arecess 20 in theinsulative substrate 2 such that therecess 20 is indented from the top surface 21 (seeFIGS. 2 and 3 ); (c) forming ametallic layer structure 5′ on a recess-definingwall 20′ of therecess 20 and thetop surface 21 of theinsulative substrate 2, themetallic layer structure 5′ including at least oneactive metal layer 3′ containing an active metal capable of initiating electroless plating (seeFIGS. 4 and 5 ); (d) removing a closed-loop portion of themetallic layer structure 5′ that is disposed along a peripheral edge of abottom wall surface 201 of the recess-definingwall 20′ so as to form themetallic layer structure 5′ into afirst region 51 which is disposed on thebottom wall surface 201, and asecond region 52 which is physically separated from thefirst region 51 by a gap 203 (seeFIG. 6 ), thefirst region 51 of themetallic layer structure 5′ defining the patternedmetallic layer structure 5 ofFIG. 9 , theactive metal layer 3′ of thefirst region 51 of themetallic layer structure 5′ defining the patternedactive metal layer 3 ofFIG. 9 ; (e) electroplating aprimary metal layer 4 on thefirst region 51 of themetallic layer structure 5′ (seeFIG. 7 ); and (f) removing thesecond region 52 of themetallic layer structure 5′ from theinsulative substrate 2 by electrolysis (seeFIGS. 8 and 9 ). - In this embodiment, the active metal of the
active metal layer 3′ is a reduced active metal. Themetallic layer structure 5′ is formed on the recess-definingwall 20′ of therecess 20 and thetop surface 21 of theinsulative substrate 2 in step (c) by immersing theinsulative substrate 2 into an active metal solution containing a non-reduced active metal (not shown) so as to form a non-reduced metal layer containing the non-reduced active metal on the recess-definingwall 20′ of therecess 20 and thetop surface 21 of theinsulative substrate 2 and then reducing the non-reduced active metal of the non-reduced metal layer so as to form theactive metal layer 3′ containing the reduced active metal on the recess-defining wall 20′ of therecess 20 and thetop surface 21 of theinsulative substrate 2. Theprimary metal layer 4 is plated on thefirst region 51 of themetallic layer structure 5′ by electroplating techniques. - In this invention, the non-reduced active metal of the non-reduced metal layer is in the form of active metal colloid particles or metal ions.
- Preferably, the active metal is selected from the group consisting of palladium, rhodium, platinum, iridium, osmium, gold, nickel, iron, and combinations thereof.
- Preferably, the active metal solution containing the non-reduced active metal is palladium salt solution or palladium-tin colloid solution.
- Preferably, the
primary metal layer 4 is made from a metal selected from the group consisting of copper, nickel, silver, and gold. - Preferably, the
insulative substrate 2 is made from a material selected from the group consisting of polycarbonate, a combination of acryl resin and acrylonitrile butadiene styrene (ABS) resin, and a combination of polycarbonate and ABS resin. - Preferably, the
recess 20 in theinsulative substrate 2 is formed by laser or plasma ablation. - Preferably, the closed-loop portion of the
metallic layer structure 5′ is removed by laser ablation. -
FIG. 14 illustrates the second preferred embodiment of acircuit substrate 100 according to the present invention. The second preferred embodiment differs from the previous embodiment in that the active metal of the patternedactive metal layer 3 is a non-reduced active metal, that the patternedmetallic layer structure 5 further includes anintermediate metal layer 6 which is electroless plated on the patternedactive metal layer 3 and which has a pattern corresponding to that of theactive metal layer 3, and that theprimary metal layer 4 is electroplated on theintermediate metal layer 6. The patternedmetallic layer structure 5 and theprimary metal layer 4 cooperatively form thecircuit pattern 10. -
FIGS. 10 to 14 illustrate consecutive steps of a method for making thecircuit substrate 100 of the second preferred embodiment according to the present invention. The method includes the steps of: forming a pattern of a recess 20 in the insulative substrate 2 (seeFIG. 10 ); forming a metallic layer structure 5′ on a recess-defining wall 20′ of the recess 20 and a top surface 21 of the insulative substrate 2 by immersing the insulative substrate 2 into an active metal solution containing a non-reduced active metal (not shown) so as to form an active metal layer 3′ containing the non-reduced active metal on the recess-defining wall 20′ of the recess 20 and the top surface 21 of the insulative substrate 2 (seeFIG. 10 ) and then electroless plating an intermediate metal layer 6 on the active metal layer 3′ (seeFIG. 11 ); removing a portion of the metallic layer structure 5′ that is disposed along a peripheral edge of a bottom wall surface 201 of the recess-defining wall 20′ so as to form the metallic layer structure 5′ into a first region 51′ which is disposed on the bottom wall surface 201, and a second region 52′ which is physically separated from the first region 51′ by a gap 203 (seeFIG. 12 ), the first region 51′ of the metallic layer structure 5′ defining the patterned metallic layer structure 5 ofFIG. 14 , the active metal layer 3′ of the first region 51′ of the metallic layer structure 5′ defining the patterned active metal layer 3 ofFIG. 14 ; (e) electroplating a primary metal layer 4 on the intermediate metal layer 6 of the first region 51′ of the metallic layer structure 5′ (seeFIG. 13 ); and (f) removing the second region 52′ of the metallic layer structure 5′ from the insulative substrate 2 by electrolysis (seeFIG. 14 ). -
FIG. 19 illustrates the third preferred embodiment of acircuit substrate 100 according to the present invention. The third preferred embodiment differs from the first preferred embodiment in that the active metal of the patternedactive metal layer 3 is a non-reduced active metal, that theprimary metal layer 4 is electroless plated on the patternedactive metal layer 3, and that atop metal layer 7 is formed on theprimary metal layer 4. Although the way of making the third preferred embodiment is different from that of the second preferred embodiment, the third preferred embodiment has a structure similar to that of the second preferred embodiment as theprimary metal layer 4 and thetop metal layer 7 of the third preferred embodiment are equivalent to theintermediate metal layer 6 and theprimary metal layer 4 of the second preferred embodiment, respectively. -
FIGS. 15 to 19 illustrate consecutive steps of a method for making thecircuit substrate 100 of the third preferred embodiment according to the present invention. The method includes the steps of: forming a pattern of a recess 20 in the insulative substrate 2 (seeFIG. 15 ); forming a metallic layer structure 5′ on a recess-defining wall 20′ of the recess 20 and a top surface 21 of the insulative substrate 2 by immersing the insulative substrate 2 into an active metal solution containing a non-reduced active metal (not shown) so as to form an active metal layer 3′ containing the non-reduced active metal on the recess-defining wall 20′ of the recess 20 and the top surface 21 of the insulative substrate 2 (seeFIG. 15 ); removing a portion of the metallic layer structure 5′ that is disposed along a peripheral edge of a bottom wall surface 201 of the recess-defining wall 20′ so as to form the metallic layer structure 5′ into a first region 51 which is disposed on the bottom wall surface 201, and a second region 52 which is physically separated from the first region 51 by a gap 203 (seeFIG. 16 ), the first region 51 of the metallic layer structure 5′ defining the patterned metallic layer structure 5 ofFIG. 19 , the active metal layer 3′ of the first region 51 of the metallic layer structure 5′ defining the patterned active metal layer 3 ofFIG. 19 ; (e) electroless plating a primary metal layer 4 on the active metal layer 3′ of the first region 51 of the metallic layer structure 5′ (seeFIG. 17 ); electroplating a top metal layer 7 on the primary metal layer 4 (seeFIG. 18 ); and (f) removing the second region 52 of the metallic layer structure 5′ from the insulative substrate 2 by electrolysis (seeFIG. 19 ). - By forming a
recess 20 in theinsulative substrate 2 and ametallic layer structure 5′ including at least oneactive metal layer 3′ (which is formed by contacting theinsulative substrate 2 with an active metal solution) in therecess 20 and subsequently removing a portion of themetallic layer structure 5′ from theinsulative substrate 2 according to the method of this invention, the aforesaid drawbacks associated with the prior art can be alleviated. - While the present invention has been described in connection with what are considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Claims (18)
1. A circuit substrate comprising:
an insulative substrate having a top surface and formed with a pattern of a recess that is indented from said top surface, said recess being defined by a recess-defining wall that has a bottom wall surface and a surrounding wall surface extending upwardly from said bottom wall surface;
a patterned metallic layer structure including at least a patterned active metal layer that is disposed within said recess, that is formed on said bottom wall surface of said recess-defining wall, and that is spaced apart from said surrounding wall surface of said recess-defining wall, said patterned active metal layer containing an active metal capable of initiating electroless plating, a pattern of said patterned active metal layer corresponding in shape to the pattern of said recess; and
a primary metal layer plated on said patterned metallic layer structure.
2. The circuit substrate of claim 1 , wherein said active metal is selected from the group consisting of palladium, rhodium, platinum, iridium, osmium, gold, nickel, iron, and combinations thereof.
3. The circuit substrate of claim 1 , wherein said primary metal layer is made from a metal selected from the group consisting of copper, nickel, silver, and gold.
4. The circuit substrate of claim 1 , wherein said insulative substrate is made from a material selected from the group consisting of polycarbonate, a combination of acryl resin and acrylonitrile butadiene styrene (ABS) resin, and a combination of polycarbonate and ABS resin.
5. The circuit substrate of claim 1 , wherein said active metal is reduced.
6. The circuit substrate of claim 1 , wherein said active metal is non-reduced, said patterned metallic layer structure further including an intermediate metal layer electroless plated on said patterned active metal layer, said primary metal layer being electroplated on said intermediate metal layer.
7. A method for making a circuit substrate having a circuit pattern, the method comprising:
(a) providing an insulative substrate having a top surface;
(b) forming a pattern of a recess in the insulative substrate such that the recess is indented from the top surface, the recess being defined by a recess-defining wall having a bottom wall surface and a surrounding wall surface extending upwardly from the bottom wall surface;
(c) forming a metallic layer structure on the recess-defining wall of the recess and the top surface of the insulative substrate, the metallic layer structure including at least one active metal layer containing an active metal capable of initiating electroless plating;
(d) removing a portion of the metallic layer structure that is disposed along a peripheral edge of the bottom wall surface of the recess-defining wall so as to form the metallic layer structure into a first region which is disposed on the bottom wall surface, and a second region which is physically separated from the first region; and
(e) plating a primary metal layer on the first region of the metallic layer structure.
8. The method of claim 7 , wherein, in step (c), the active metal of the active metal layer is a reduced active metal, and the metallic layer structure is formed on the recess-defining wall of the recess and the top surface of the insulative substrate by immersing the insulative substrate into an active metal solution containing a non-reduced active metal so as to form a non-reduced metal layer containing the non-reduced active metal on the recess-defining wall of the recess and the top surface of the insulative substrate and then reducing the non-reduced active metal of the non-reduced metal layer so as to form the active metal layer containing the reduced active metal.
9. The method of claim 8 , wherein, in step (e), the primary metal layer is formed on the first region of the metallic layer structure by electroplating.
10. The method of claim 7 , wherein, in step (c), the active metal of the active metal layer is a non-reduced active metal, and the metallic layer structure is formed on the recess-defining wall of the recess and the top surface of the insulative substrate by immersing the insulative substrate into an active metal solution containing the non-reduced active metal so as to form the active metal layer containing the non-reduced active metal on the recess-defining wall of the recess and the top surface of the insulative substrate and then electroless plating an intermediate metal layer on the active metal layer.
11. The method of claim 10 , wherein, in step (e), the primary metal layer is formed on the intermediate metal layer of the first region of the metallic layer structure by electroplating.
12. The method of claim 7 , wherein, in step (c), the active metal of the active metal layer is a non-reduced active metal, and the metallic layer structure is formed on the recess-defining wall of the recess and the top surface of the insulative substrate by immersing the insulative substrate into an active metal solution containing the non-reduced active metal so as to form the active metal layer containing the non-reduced active metal on the recess-defining wall of the recess and the top surface of the insulative substrate.
13. The method of claim 12 , wherein, in step (e), the primary metal layer is formed on the active metal layer of the first region of the metallic layer structure by electroless plating.
14. The method of claim 13 , further comprising, after step (e), electroplating a top metal layer on the primary metal layer.
15. The method of claim 7 , wherein, in step (b), the recess in the insulative substrate is formed by laser or plasma ablation.
16. The method of claim 7 , wherein, in step (d), the portion of the metallic layer structure is removed by laser ablation.
17. The method of claim 7 , further comprising, after step (e), removing the second region of the metallic layer structure from the insulative substrate.
18. The method of claim 17 , wherein the second region of the metallic layer structure is removed from the insulative substrate by electrolysis.
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US14/933,616 US9474161B2 (en) | 2010-03-12 | 2015-11-05 | Circuit substrate having a circuit pattern and method for making the same |
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US13/547,494 US20120273261A1 (en) | 2010-10-20 | 2012-07-12 | Circuit substrate having a circuit pattern and method for making the same |
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US9295162B2 (en) | 2010-03-12 | 2016-03-22 | Taiwan Green Point Enterprises Co., Ltd. | Non-deleterious technique for creating continuous conductive circuits upon the surfaces of a non-conductive substrate |
US20160186327A1 (en) * | 2014-12-24 | 2016-06-30 | Taiwan Green Point Enterprises Co., Ltd. | Method for forming a circuit pattern on a substrate |
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4988412A (en) * | 1988-12-27 | 1991-01-29 | General Electric Company | Selective electrolytic desposition on conductive and non-conductive substrates |
US5340773A (en) * | 1991-10-16 | 1994-08-23 | Nec Corporation | Method of fabricating a semiconductor device |
US5494781A (en) * | 1993-08-26 | 1996-02-27 | Matsushita Electric Works, Ltd. | Method for manufacturing printed circuit board |
US20020119251A1 (en) * | 2001-02-23 | 2002-08-29 | Chen William T. | Method and apparatus for forming a metallic feature on a substrate |
US20030214486A1 (en) * | 2002-05-17 | 2003-11-20 | Roberts Jerry B. | Correction of memory effect errors in force-based touch panel systems |
US20060030128A1 (en) * | 2004-08-03 | 2006-02-09 | Xiaomei Bu | Structure and method of liner air gap formation |
US20070097154A1 (en) * | 2005-09-15 | 2007-05-03 | Fuji Photo Film Co., Ltd. | Wiring board, method of manufacturing wiring board, and liquid ejection head |
US20090298256A1 (en) * | 2008-06-03 | 2009-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor interconnect air gap formation process |
US20110215477A1 (en) * | 2009-05-06 | 2011-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof |
Family Cites Families (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4066804A (en) | 1969-11-26 | 1978-01-03 | Imperial Chemical Industries Limited | Metal deposition process |
US3853589A (en) | 1970-11-09 | 1974-12-10 | Ici Ltd | Metal deposition process |
US3754939A (en) | 1972-05-23 | 1973-08-28 | Us Army | Electroless deposition of palladium alloys |
US3781596A (en) | 1972-07-07 | 1973-12-25 | R Galli | Semiconductor chip carriers and strips thereof |
DE2418654A1 (en) | 1974-04-18 | 1975-11-06 | Langbein Pfanhauser Werke Ag | PROCESS FOR ELECTRONIC SURFACE METALIZATION OF PLASTIC OBJECTS AND A SUITABLE ACTIVATING BATH TO PERFORM THE PROCESS |
US4264646A (en) | 1979-03-12 | 1981-04-28 | Xerox Corporation | Selectively electrolessly depositing a metal pattern on the surface of a laminar film |
US4574095A (en) | 1984-11-19 | 1986-03-04 | International Business Machines Corporation | Selective deposition of copper |
US4790912A (en) | 1985-06-06 | 1988-12-13 | Techno-Instruments Investments Ltd. | Selective plating process for the electrolytic coating of circuit boards without an electroless metal coating |
US4865873A (en) | 1986-09-15 | 1989-09-12 | General Electric Company | Electroless deposition employing laser-patterned masking layer |
US4882200A (en) | 1987-05-21 | 1989-11-21 | General Electric Company | Method for photopatterning metallization via UV-laser ablation of the activator |
US4963701A (en) | 1988-01-25 | 1990-10-16 | Kabushiki Kaisha Toshiba | Circuit board |
US4877644A (en) | 1988-04-12 | 1989-10-31 | Amp Incorporated | Selective plating by laser ablation |
US4898648A (en) | 1988-11-15 | 1990-02-06 | Pacific Bell | Method for providing a strengthened conductive circuit pattern |
US4946563A (en) | 1988-12-12 | 1990-08-07 | General Electric Company | Process for manufacturing a selective plated board for surface mount components |
US5084299A (en) | 1989-08-10 | 1992-01-28 | Microelectronics And Computer Technology Corporation | Method for patterning electroless plated metal on a polymer substrate |
US4925522A (en) | 1989-08-21 | 1990-05-15 | Gte Products Corporation | Printed circuit assembly with contact dot |
US5086966A (en) | 1990-11-05 | 1992-02-11 | Motorola Inc. | Palladium-coated solder ball |
JP2948366B2 (en) | 1991-09-05 | 1999-09-13 | 塚田理研工業株式会社 | Partial plating method for plastic moldings |
US6325910B1 (en) | 1994-04-08 | 2001-12-04 | Atotch Deutschland Gmbh | Palladium colloid solution and its utilization |
US5525204A (en) | 1994-09-29 | 1996-06-11 | Motorola, Inc. | Method for fabricating a printed circuit for DCA semiconductor chips |
US5924364A (en) | 1997-01-17 | 1999-07-20 | Agfa-Gevaert N.V. | Laser-imagable recording material and printing plate produced therefrom for waterless offset printing |
JPH10209607A (en) | 1997-01-23 | 1998-08-07 | Matsushita Electric Works Ltd | Manufacture of circuit board |
EP1005261B1 (en) | 1997-04-15 | 2003-03-05 | Ibiden Co., Ltd. | Adhesive for electroless plating, feedstock composition for preparing adhesive for electroless plating, and printed wiring board |
DE19731346C2 (en) | 1997-06-06 | 2003-09-25 | Lpkf Laser & Electronics Ag | Conductor structures and a method for their production |
JPH1197824A (en) | 1997-09-22 | 1999-04-09 | Matsushita Electric Works Ltd | Manufacture of circuit board |
WO1999027590A1 (en) | 1997-11-25 | 1999-06-03 | California Institute Of Technology | Fuel cell elements with improved water handling capacity |
US6162365A (en) | 1998-03-04 | 2000-12-19 | International Business Machines Corporation | Pd etch mask for copper circuitization |
US6517894B1 (en) | 1998-04-30 | 2003-02-11 | Ebara Corporation | Method for plating a first layer on a substrate and a second layer on the first layer |
US6188391B1 (en) | 1998-07-09 | 2001-02-13 | Synaptics, Inc. | Two-layer capacitive touchpad and method of making same |
MY139405A (en) | 1998-09-28 | 2009-09-30 | Ibiden Co Ltd | Printed circuit board and method for its production |
JP2000232269A (en) | 1999-02-10 | 2000-08-22 | Nec Toyama Ltd | Printed wiring board and manufacture thereof |
US6359233B1 (en) | 1999-10-26 | 2002-03-19 | Intel Corporation | Printed circuit board multipack structure having internal gold fingers and multipack and printed circuit board formed therefrom, and methods of manufacture thereof |
US6242156B1 (en) | 2000-06-28 | 2001-06-05 | Gary Ganghui Teng | Lithographic plate having a conformal radiation-sensitive layer on a rough substrate |
US6515233B1 (en) | 2000-06-30 | 2003-02-04 | Daniel P. Labzentis | Method of producing flex circuit with selectively plated gold |
US6801438B1 (en) | 2000-10-24 | 2004-10-05 | Touch Future Technolocy Ltd. | Electrical circuit and method of formation |
KR20020071437A (en) | 2001-03-06 | 2002-09-12 | 유승균 | Plating method of metal film on the surface of polymer |
DE10132092A1 (en) | 2001-07-05 | 2003-01-23 | Lpkf Laser & Electronics Ag | Track structures and processes for their manufacture |
JP4208440B2 (en) | 2001-07-19 | 2009-01-14 | 富士フイルム株式会社 | Development processing method for lithographic printing plate precursor |
EP1444705B1 (en) | 2001-09-10 | 2007-08-29 | Microbridge Technologies Inc. | Method for effective trimming of resistors using pulsed heating |
KR100396787B1 (en) | 2001-11-13 | 2003-09-02 | 엘지전자 주식회사 | Wire bonding pad structure of semiconductor package pcb |
US20040149986A1 (en) | 2002-04-16 | 2004-08-05 | Dubowski Jan J. | Multilayer microstructures and laser based method for precision and reduced damage patterning of such structures |
US7361313B2 (en) | 2003-02-18 | 2008-04-22 | Intel Corporation | Methods for uniform metal impregnation into a nanoporous material |
US7656393B2 (en) | 2005-03-04 | 2010-02-02 | Apple Inc. | Electronic device having display and surrounding touch sensitive bezel for user interface and control |
EP1383360B1 (en) | 2002-07-18 | 2007-01-03 | FESTO AG & Co | Injection moulded lead carrier and method of producing the same |
US20050112432A1 (en) | 2002-08-27 | 2005-05-26 | Jonah Erlebacher | Method of plating metal leafs and metal membranes |
US6773760B1 (en) | 2003-04-28 | 2004-08-10 | Yuh Sung | Method for metallizing surfaces of substrates |
WO2005054120A2 (en) | 2003-12-05 | 2005-06-16 | Idaho Research Foundation, Inc. | Polymer-supported metal nanoparticles and method for their manufacture and use |
US7145238B1 (en) | 2004-05-05 | 2006-12-05 | Amkor Technology, Inc. | Semiconductor package and substrate having multi-level vias |
US7291380B2 (en) | 2004-07-09 | 2007-11-06 | Hewlett-Packard Development Company, L.P. | Laser enhanced plating for forming wiring patterns |
US7279407B2 (en) | 2004-09-02 | 2007-10-09 | Micron Technology, Inc. | Selective nickel plating of aluminum, copper, and tungsten structures |
US7719522B2 (en) | 2004-09-24 | 2010-05-18 | Apple Inc. | Raw data track pad device and system |
US7517791B2 (en) | 2004-11-30 | 2009-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
KR100640662B1 (en) * | 2005-08-06 | 2006-11-01 | 삼성전자주식회사 | Semiconductor device having a barrier metal spacer and method of fabricating the same |
US7913644B2 (en) | 2005-09-30 | 2011-03-29 | Lam Research Corporation | Electroless deposition system |
US20070148420A1 (en) | 2005-12-28 | 2007-06-28 | Intel Corporation | Method of making a substrate using laser assisted metallization and patterning with electroless plating without electrolytic plating |
DE102006017630A1 (en) | 2006-04-12 | 2007-10-18 | Lpkf Laser & Electronics Ag | Method for producing a printed conductor structure and a printed conductor structure produced in this way |
JP4903479B2 (en) | 2006-04-18 | 2012-03-28 | 富士フイルム株式会社 | Metal pattern forming method, metal pattern, and printed wiring board |
US7779522B2 (en) | 2006-05-05 | 2010-08-24 | Fujifilm Dimatix, Inc. | Method for forming a MEMS |
US20080001297A1 (en) | 2006-06-30 | 2008-01-03 | Stefanie Lotz | Laser patterning and conductive interconnect/materials forming techniques for fine line and space features |
JP5286046B2 (en) | 2007-11-30 | 2013-09-11 | 株式会社半導体エネルギー研究所 | Method for manufacturing photoelectric conversion device |
EP2124514A1 (en) | 2008-05-23 | 2009-11-25 | Nederlandse Centrale Organisatie Voor Toegepast Natuurwetenschappelijk Onderzoek TNO | Providing a plastic substrate with a metallic pattern |
US9335868B2 (en) | 2008-07-31 | 2016-05-10 | Apple Inc. | Capacitive sensor behind black mask |
US7956548B2 (en) | 2009-04-08 | 2011-06-07 | Kanghong Zhang | Electronic ballast protection |
US20100258173A1 (en) | 2009-04-13 | 2010-10-14 | Joseph Laia | Polishing a thin metallic substrate for a solar cell |
JP5705857B2 (en) * | 2009-09-16 | 2015-04-22 | マラディン テクノロジーズ リミテッドMaradin Technologies Ltd. | Micro-coil device and manufacturing method thereof |
JP5498751B2 (en) * | 2009-10-05 | 2014-05-21 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
TWI412308B (en) * | 2009-11-06 | 2013-10-11 | Via Tech Inc | Circuit substrate and fabricating process thereof |
FR2954580B1 (en) | 2009-12-22 | 2011-12-09 | Commissariat Energie Atomique | METHOD FOR PRODUCING A NON-PLAN MICROELECTRONIC COMPONENT |
US8952919B2 (en) | 2011-02-25 | 2015-02-10 | Taiwan Green Point Enterprises Co., Ltd. | Capacitive touch sensitive housing and method for making the same |
US20120273261A1 (en) | 2010-10-20 | 2012-11-01 | Taiwan Green Point Enterprises Co., Ltd. | Circuit substrate having a circuit pattern and method for making the same |
US8692790B2 (en) | 2011-02-25 | 2014-04-08 | Taiwan Green Point Enterprises Co., Ltd. | Capacitive touch sensitive housing and method for making the same |
US8621749B2 (en) | 2010-03-12 | 2014-01-07 | Taiwan Green Point Enterprises Co., Ltd | Non-deleterious technique for creating continuous conductive circuits |
US20120086101A1 (en) * | 2010-10-06 | 2012-04-12 | International Business Machines Corporation | Integrated circuit and interconnect, and method of fabricating same |
US8318576B2 (en) * | 2011-04-21 | 2012-11-27 | Freescale Semiconductor, Inc. | Decoupling capacitors recessed in shallow trench isolation |
US20120278050A1 (en) | 2011-04-29 | 2012-11-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Accelerated Generation of Circuit Parameter Distribution Using Monte Carlo Simulation |
KR101872520B1 (en) * | 2011-07-28 | 2018-06-29 | 삼성전기주식회사 | Laminated ceramic electronic parts |
-
2012
- 2012-07-12 US US13/547,494 patent/US20120273261A1/en not_active Abandoned
-
2015
- 2015-11-05 US US14/933,616 patent/US9474161B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4988412A (en) * | 1988-12-27 | 1991-01-29 | General Electric Company | Selective electrolytic desposition on conductive and non-conductive substrates |
US5340773A (en) * | 1991-10-16 | 1994-08-23 | Nec Corporation | Method of fabricating a semiconductor device |
US5494781A (en) * | 1993-08-26 | 1996-02-27 | Matsushita Electric Works, Ltd. | Method for manufacturing printed circuit board |
US20020119251A1 (en) * | 2001-02-23 | 2002-08-29 | Chen William T. | Method and apparatus for forming a metallic feature on a substrate |
US20030214486A1 (en) * | 2002-05-17 | 2003-11-20 | Roberts Jerry B. | Correction of memory effect errors in force-based touch panel systems |
US20060030128A1 (en) * | 2004-08-03 | 2006-02-09 | Xiaomei Bu | Structure and method of liner air gap formation |
US20070097154A1 (en) * | 2005-09-15 | 2007-05-03 | Fuji Photo Film Co., Ltd. | Wiring board, method of manufacturing wiring board, and liquid ejection head |
US20090298256A1 (en) * | 2008-06-03 | 2009-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor interconnect air gap formation process |
US20110215477A1 (en) * | 2009-05-06 | 2011-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits including air gaps around interconnect structures, and fabrication methods thereof |
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US9933811B2 (en) | 2010-03-12 | 2018-04-03 | Taiwan Green Point Enterprises Co., Ltd. | Capacitive touch sensitive housing and method for making the same |
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US9420699B2 (en) | 2010-03-12 | 2016-08-16 | Taiwan Green Point Enterprises Co., Ltd. | Non-deleterious technique for creating continuous conductive circuits upon the surfaces of a non-conductive substrate |
US9474161B2 (en) | 2010-03-12 | 2016-10-18 | Taiwan Green Point Enterprises Co., Ltd. | Circuit substrate having a circuit pattern and method for making the same |
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US9021691B2 (en) * | 2010-05-04 | 2015-05-05 | Lpkf Laser & Electronics Ag | Method for introducing electrical insulations in printed circuit boards |
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US20160057865A1 (en) | 2016-02-25 |
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