JP5421142B2 - デジタル遅延線の時間遅延のプロセス、電圧、および温度のばらつき補正を行う装置と方法 - Google Patents

デジタル遅延線の時間遅延のプロセス、電圧、および温度のばらつき補正を行う装置と方法 Download PDF

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Publication number
JP5421142B2
JP5421142B2 JP2010024183A JP2010024183A JP5421142B2 JP 5421142 B2 JP5421142 B2 JP 5421142B2 JP 2010024183 A JP2010024183 A JP 2010024183A JP 2010024183 A JP2010024183 A JP 2010024183A JP 5421142 B2 JP5421142 B2 JP 5421142B2
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delay
circuit
output
signal
input
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JP2010246092A (ja
JP2010246092A5 (enExample
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ジェームズ・シーフェルト
シャオシン・フェン
ウェストン・ロパー
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Honeywell International Inc
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Honeywell International Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00123—Avoiding variations of delay due to integration tolerances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/0013—Avoiding variations of delay due to power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00143—Avoiding variations of delay due to temperature

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
JP2010024183A 2009-04-06 2010-02-05 デジタル遅延線の時間遅延のプロセス、電圧、および温度のばらつき補正を行う装置と方法 Expired - Fee Related JP5421142B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/418,981 2009-04-06
US12/418,981 US8390352B2 (en) 2009-04-06 2009-04-06 Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line

Publications (3)

Publication Number Publication Date
JP2010246092A JP2010246092A (ja) 2010-10-28
JP2010246092A5 JP2010246092A5 (enExample) 2013-03-21
JP5421142B2 true JP5421142B2 (ja) 2014-02-19

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JP2010024183A Expired - Fee Related JP5421142B2 (ja) 2009-04-06 2010-02-05 デジタル遅延線の時間遅延のプロセス、電圧、および温度のばらつき補正を行う装置と方法

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Country Link
US (1) US8390352B2 (enExample)
EP (1) EP2239849B1 (enExample)
JP (1) JP5421142B2 (enExample)
TW (1) TWI525997B (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8390356B2 (en) * 2008-05-08 2013-03-05 Kpit Cummins Infosystems, Ltd. Method and system for open loop compensation of delay variations in a delay line
US20130015837A1 (en) * 2011-07-13 2013-01-17 International Business Machines Corporation On-chip signal waveform measurement circuit
US8850155B2 (en) * 2011-12-19 2014-09-30 Advanced Micro Devices, Inc. DDR 2D Vref training
CN107092383B (zh) * 2012-03-29 2020-09-11 禾瑞亚科技股份有限公司 触摸处理器
US8742815B2 (en) * 2012-06-20 2014-06-03 Qualcomm Incorporated Temperature-independent oscillators and delay elements
US8867595B1 (en) 2012-06-25 2014-10-21 Rambus Inc. Reference voltage generation and calibration for single-ended signaling
US9503088B2 (en) 2013-01-10 2016-11-22 Freescale Semiconductor, Inc. Method and control device for recovering NBTI/PBTI related parameter degradation in MOSFET devices
WO2014210192A1 (en) * 2013-06-25 2014-12-31 Ess Technology, Inc. Delay circuit independent of supply voltage
KR20160009429A (ko) * 2014-07-16 2016-01-26 삼성전자주식회사 Ｐｖｔ 변동에 둔감한 딜레이 컨트롤 시스템 및 그 제어 방법
CN105049043B (zh) * 2015-06-30 2018-05-08 北京时代民芯科技有限公司 一种带有失调校正功能的高速比较器
KR102424896B1 (ko) * 2016-02-25 2022-07-26 에스케이하이닉스 주식회사 데이터 트레이닝 장치 및 이를 포함하는 반도체 장치
US9792964B1 (en) * 2016-09-20 2017-10-17 Micron Technology, Inc. Apparatus of offset voltage adjustment in input buffer
CN106847319B (zh) * 2016-12-23 2021-06-29 深圳市紫光同创电子有限公司 一种fpga电路及窗口信号调整方法
CN108806744B (zh) * 2017-05-05 2020-11-27 中芯国际集成电路制造(上海)有限公司 一种延时产生电路及非易失性存储器读时序产生电路
CN107315442B (zh) 2017-06-30 2019-04-30 上海兆芯集成电路有限公司 控制器与参考电压产生方法
CN107342766B (zh) * 2017-09-02 2023-08-11 合肥学院 一种近阈值电压全数字逐次逼近寄存器延时锁定环系统
CN109900971B (zh) * 2017-12-11 2023-01-24 长鑫存储技术有限公司 脉冲信号的处理方法、装置以及半导体存储器
CN112152596B (zh) * 2019-06-27 2024-03-08 台湾积体电路制造股份有限公司 用于产生脉冲输出的电路及方法
CN111327298B (zh) * 2020-03-12 2021-03-30 湖南毂梁微电子有限公司 一种超高精度数字脉冲信号产生电路及方法
US10911035B1 (en) 2020-05-04 2021-02-02 Nxp Usa, Inc. Fixed-width pulse generator
US20230141595A1 (en) * 2021-11-08 2023-05-11 Advanced Micro Devices, Inc. Compensation methods for voltage and temperature (vt) drift of memory interfaces

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4639688A (en) * 1985-04-18 1987-01-27 The United States Of America As Represented By The Secretary Of The Air Force Wide-band phase locked loop amplifier apparatus
EP0236525B1 (de) * 1986-03-12 1990-12-19 Deutsche ITT Industries GmbH Integrierte Isolierschicht-Feldeffekttransistor-Verzögerungsleitung für Digitalsignale
JPS6369315A (ja) * 1986-09-11 1988-03-29 Sony Corp Ｃｍｏｓ回路を用いた可変遅延装置
US4847870A (en) * 1987-11-25 1989-07-11 Siemens Transmission Systems, Inc. High resolution digital phase-lock loop circuit
US4845388A (en) * 1988-01-20 1989-07-04 Martin Marietta Corporation TTL-CMOS input buffer
US5101117A (en) * 1988-02-17 1992-03-31 Mips Computer Systems Variable delay line phase-locked loop circuit synchronization system
US5021684A (en) * 1989-11-09 1991-06-04 Intel Corporation Process, supply, temperature compensating CMOS output buffer
US5192886A (en) 1990-03-15 1993-03-09 Hewlett-Packard Company Sub-nanosecond calibrated delay line structure
JP3091502B2 (ja) * 1990-03-15 2000-09-25 ヒューレット・パッカード・カンパニー サブナノ秒較正遅延線構造
JP3561792B2 (ja) * 1995-09-06 2004-09-02 株式会社ルネサステクノロジ クロック発生回路
US5666322A (en) * 1995-09-21 1997-09-09 Nec Electronics, Inc. Phase-locked loop timing controller in an integrated circuit memory
DE69839112T2 (de) * 1997-12-19 2008-05-21 Matsushita Electric Industrial Co., Ltd., Kadoma Kammfilter und Steuerverfahren dazu
US5963071A (en) * 1998-01-22 1999-10-05 Nanoamp Solutions, Inc. Frequency doubler with adjustable duty cycle
US6091271A (en) * 1998-06-30 2000-07-18 Lucent Technologies, Inc. Frequency doubling method and apparatus
US6288587B1 (en) * 1999-04-07 2001-09-11 National Science Council Of Republic Of China CMOS pulse shrinking delay element with deep subnanosecond resolution
US6316987B1 (en) * 1999-10-22 2001-11-13 Velio Communications, Inc. Low-power low-jitter variable delay timing circuit
US6377103B1 (en) * 2000-06-28 2002-04-23 Intel Corporation Symmetric, voltage-controlled CMOS delay cell with closed-loop replica bias
US6535735B2 (en) * 2001-03-22 2003-03-18 Skyworks Solutions, Inc. Critical path adaptive power control
US6581017B2 (en) * 2001-06-28 2003-06-17 Intel Corporation System and method for minimizing delay variation in double data rate strobes
US6918048B2 (en) * 2001-06-28 2005-07-12 Intel Corporation System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment
CN1393992A (zh) * 2001-07-02 2003-01-29 朗迅科技公司 包含反馈回路的延迟补偿电路
US6747500B2 (en) * 2001-10-19 2004-06-08 Mitutoyo Corporation Compact delay circuit for CMOS integrated circuits used in low voltage low power devices
US6741522B1 (en) * 2001-11-27 2004-05-25 Lsi Logic Corporation Methods and structure for using a higher frequency clock to shorten a master delay line
US7015740B1 (en) * 2002-10-28 2006-03-21 Cisco Technology, Inc. Self-adjusting programmable on-chip clock aligner
US6801028B2 (en) * 2002-11-14 2004-10-05 Fyre Storm, Inc. Phase locked looped based digital pulse converter
US6853231B2 (en) * 2003-03-31 2005-02-08 Mosaid Technologies Incorporated Timing vernier using a delay locked loop
US7266739B2 (en) * 2003-05-07 2007-09-04 Credence Systems Solutions Systems and methods associated with test equipment
US6940768B2 (en) * 2003-11-04 2005-09-06 Agere Systems Inc. Programmable data strobe offset with DLL for double data rate (DDR) RAM memory
JPWO2005050844A1 (ja) * 2003-11-20 2007-06-14 株式会社アドバンテスト 可変遅延回路
US7178048B2 (en) * 2003-12-23 2007-02-13 Hewlett-Packard Development Company, L.P. System and method for signal synchronization based on plural clock signals
JP2006039830A (ja) * 2004-07-26 2006-02-09 Renesas Technology Corp 半導体集積回路
US7129763B1 (en) * 2004-11-08 2006-10-31 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry by generating frequency error representing error in propagation delay
US7634039B2 (en) * 2005-02-04 2009-12-15 True Circuits, Inc. Delay-locked loop with dynamically biased charge pump
US7123103B1 (en) * 2005-03-31 2006-10-17 Conexant Systems, Inc. Systems and method for automatic quadrature phase imbalance compensation using a delay locked loop
US7388419B2 (en) * 2005-07-22 2008-06-17 Freescale Semiconductor, Inc PVT variation detection and compensation circuit
US7222036B1 (en) * 2006-03-31 2007-05-22 Altera Corporation Method for providing PVT compensation
KR100776903B1 (ko) * 2006-04-24 2007-11-19 주식회사 하이닉스반도체 지연 고정 루프
US7433262B2 (en) * 2006-08-22 2008-10-07 Atmel Corporation Circuits to delay a signal from DDR-SDRAM memory device including an automatic phase error correction
JP2008078995A (ja) * 2006-09-21 2008-04-03 Nec Electronics Corp 移相回路
JP4892402B2 (ja) * 2007-04-25 2012-03-07 ルネサスエレクトロニクス株式会社 半導体集積回路装置
JP2009017151A (ja) * 2007-07-04 2009-01-22 Yokogawa Electric Corp 遅延回路およびそれを用いた信号発生回路
JP5451012B2 (ja) * 2008-09-04 2014-03-26 ピーエスフォー ルクスコ エスエイアールエル Ｄｌｌ回路及びその制御方法
KR100985413B1 (ko) * 2008-10-14 2010-10-06 주식회사 하이닉스반도체 지연회로 및 그를 포함하는 지연고정루프회로

Also Published As

Publication number Publication date
TWI525997B (zh) 2016-03-11
JP2010246092A (ja) 2010-10-28
EP2239849A2 (en) 2010-10-13
US20100253406A1 (en) 2010-10-07
TW201136171A (en) 2011-10-16
EP2239849A3 (en) 2013-12-18
EP2239849B1 (en) 2018-03-14
US8390352B2 (en) 2013-03-05

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