JP5403979B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5403979B2 JP5403979B2 JP2008237539A JP2008237539A JP5403979B2 JP 5403979 B2 JP5403979 B2 JP 5403979B2 JP 2008237539 A JP2008237539 A JP 2008237539A JP 2008237539 A JP2008237539 A JP 2008237539A JP 5403979 B2 JP5403979 B2 JP 5403979B2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Description
本発明の半導体装置の製造方法について、図1乃至図4を参照して説明する。本実施の形態では、より高集積化された高性能な半導体素子を有する半導体装置の一例としてCMOS(相補型金属酸化物半導体:Complementary Metal Oxide Semiconductor)に関して説明する。
本実施の形態では、実施の形態1において、半導体基板より支持基板へ半導体層を接合する工程の異なる例を示す。従って、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
本実施の形態では、実施の形態1において、半導体基板より支持基板へ半導体層を接合する工程の異なる例を示す。従って、実施の形態1と同一部分又は同様な機能を有する部分の繰り返しの説明は省略する。
本実施の形態では、本発明(特に実施の形態3)に適用することができる半導体装置の製造装置の構成について説明する。
本実施の形態では、半導体基板から、それぞれn型歪み電界効果トランジスタとp型歪み電界効果トランジスタに適した半導体層を取り出す構成について示す。
本実施の形態では、高性能、かつ高い信頼性を付与することを目的とした半導体装置の例について説明する。詳しくは半導体装置の一例として、マイクロプロセッサ及び非接触でデータの送受信を行うことのできる演算機能を備えた半導体装置の一例について説明する。
本実施の形態では、本発明に係る半導体装置の実装構造の例を示す。
本実施の形態では、上記実施の形態で示した半導体装置の使用形態の一例について説明する。具体的には、非接触でデータの入出力が可能である半導体装置の適用例に関して、図面を用いて以下に説明する。非接触でデータの入出力が可能である半導体装置は利用の形態によって、RFIDタグ、IDタグ、ICタグ、ICチップ、RFタグ、無線タグ、電子タグまたは無線チップとも呼ばれる。
本実施の形態では、上述した本発明を用いて形成された非接触でデータの入出力が可能である半導体装置の適用例に関して図面を参照して以下に説明する。非接触でデータの入出力が可能である半導体装置は利用の形態によっては、RFIDタグ、IDタグ、ICタグ、ICチップ、RFタグ、無線タグ、電子タグまたは無線チップともよばれる。
本発明によりプロセッサ回路を有するチップ(以下、プロセッサチップ、無線チップ、無線プロセッサ、無線メモリ、無線タグともよぶ)として機能する半導体装置を形成することができる。本発明の半導体装置の用途は広範にわたり、非接触で対象物の履歴等の情報を明確にし、生産・管理等に役立てる商品であればどのようなものにも適用することができる。例えば、紙幣、硬貨、有価証券類、証書類、無記名債券類、包装用容器類、書籍類、記録媒体、身の回り品、乗物類、食品類、衣類、保健用品類、生活用品類、薬品類及び電子機器等に設けて使用することができる。これらの例に関して図11を用いて説明する。
Claims (10)
- 絶縁表面を有する基板上に、
第1の半導体層、第1のゲート絶縁層、第1のゲート電極層、第1のソース電極層及び第1のドレイン電極層を含む第1の電界効果トランジスタと、
前記第1の電界効果トランジスタを覆う第1の絶縁膜と、
前記第1の絶縁膜上に層間絶縁層と、
前記層間絶縁層上に、第2の半導体層、第2のゲート絶縁層、第2のゲート電極層、第2のソース電極層及び第2のドレイン電極層を含む第2の電界効果トランジスタと、
前記第2の電界効果トランジスタを覆う第2の絶縁膜と、
を積層構造で有し、
前記第1の電界効果トランジスタは、前記第1の半導体層と前記絶縁表面を有する基板との間に形成された第1の絶縁層と接合して前記絶縁表面を有する基板上に設けられ、
前記第2の電界効果トランジスタは、前記層間絶縁層上に設けられた第2の絶縁層と接合して前記第1の電界効果トランジスタ上に設けられ、
前記第1の半導体層と、前記第2の半導体層の結晶面方位は互いに異なることを特徴とする半導体装置。 - 絶縁表面を有する基板上に、
第1の半導体層、第1のゲート絶縁層、第1のゲート電極層、第1のソース電極層及び第1のドレイン電極層を含む第1の電界効果トランジスタと、
前記第1の電界効果トランジスタを覆う第1の絶縁膜と、
前記第1の絶縁膜上に層間絶縁層と、
前記層間絶縁層上に、第2の半導体層、第2のゲート絶縁層、第2のゲート電極層、第2のソース電極層及び第2のドレイン電極層を含む第2の電界効果トランジスタと、
前記第2の電界効果トランジスタを覆う第2の絶縁膜と、
を積層構造で有し、
前記第1の電界効果トランジスタは、前記第1の半導体層と前記絶縁表面を有する基板との間に形成された第1の絶縁層と接合して前記絶縁表面を有する基板上に設けられ、
前記第2の電界効果トランジスタは、前記層間絶縁層上に設けられた第2の絶縁層と接合して前記第1の電界効果トランジスタ上に設けられ、
前記第1の半導体層及び前記第2の半導体層は前記層間絶縁層を介して重なっており、
前記第2の半導体層、前記層間絶縁層、前記第2の絶縁層、前記第1のゲート絶縁層を貫通し前記第1の半導体層に達する開口に形成された配線によって、前記第1の電界効果トランジスタ及び前記第2の電界効果トランジスタは電気的に接続されていることを特徴とする半導体装置。 - 請求項2において、前記第1の半導体層と、前記第2の半導体層の結晶面方位は互いに異なることを特徴とする半導体装置。
- 請求項1乃至3のいずれか一項において、前記第1の電界効果トランジスタの導電型がn型であり、前記第2の電界効果トランジスタの導電型がp型であることを特徴とする半導体装置。
- 請求項1乃至4のいずれか一項において、前記第1の絶縁膜は引っ張り応力を有する絶縁膜であり、前記第2の絶縁膜は圧縮応力を有する絶縁膜であることを特徴とする半導体装置。
- 請求項1乃至5のいずれか一項において、前記第1の半導体層と、前記第2の半導体層のチャネル長方向の結晶軸は互いに異なることを特徴とする半導体装置。
- 請求項1乃至6のいずれか一項において、前記第1の半導体層の前記絶縁表面に平行な面の結晶面方位は{100}であり、前記第2の半導体層の前記絶縁表面に平行な面の結晶面方位は{110}であることを特徴とする半導体装置。
- 請求項7において、前記第1の半導体層のチャネル長方向の結晶軸が<100>であり、前記第2の半導体層のチャネル長方向の結晶軸が<110>であることを特徴とする半導体装置。
- 請求項1乃至8のいずれか一項において、前記第1の絶縁膜及び前記第2の絶縁膜は窒化珪素膜、又は窒化酸化珪素膜であることを特徴とする半導体装置。
- 請求項1乃至9のいずれか一項において、前記基板は、ガラス基板である半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2008237539A JP5403979B2 (ja) | 2007-09-21 | 2008-09-17 | 半導体装置 |
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JP2007244824 | 2007-09-21 | ||
JP2007244824 | 2007-09-21 | ||
JP2008237539A JP5403979B2 (ja) | 2007-09-21 | 2008-09-17 | 半導体装置 |
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JP2009094494A JP2009094494A (ja) | 2009-04-30 |
JP5403979B2 true JP5403979B2 (ja) | 2014-01-29 |
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US (1) | US7982250B2 (ja) |
JP (1) | JP5403979B2 (ja) |
CN (1) | CN101393919B (ja) |
TW (1) | TWI458076B (ja) |
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US20090078970A1 (en) | 2009-03-26 |
JP2009094494A (ja) | 2009-04-30 |
TWI458076B (zh) | 2014-10-21 |
US7982250B2 (en) | 2011-07-19 |
CN101393919A (zh) | 2009-03-25 |
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