JP5390346B2 - パッケージ基板の製造方法 - Google Patents

パッケージ基板の製造方法 Download PDF

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Publication number
JP5390346B2
JP5390346B2 JP2009263134A JP2009263134A JP5390346B2 JP 5390346 B2 JP5390346 B2 JP 5390346B2 JP 2009263134 A JP2009263134 A JP 2009263134A JP 2009263134 A JP2009263134 A JP 2009263134A JP 5390346 B2 JP5390346 B2 JP 5390346B2
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Japan
Prior art keywords
dielectric layer
layer
release film
auxiliary dielectric
area
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JP2009263134A
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Japanese (ja)
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JP2010287874A (ja
JP2010287874A5 (enExample
Inventor
▲謹▼銘 劉
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欣興電子股▲フン▼有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2009263134A 2009-06-11 2009-11-18 パッケージ基板の製造方法 Expired - Fee Related JP5390346B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW098119494 2009-06-11
TW098119494A TWI365026B (en) 2009-06-11 2009-06-11 Method for fabricating packaging substrate and base therefor

Publications (3)

Publication Number Publication Date
JP2010287874A JP2010287874A (ja) 2010-12-24
JP2010287874A5 JP2010287874A5 (enExample) 2013-01-10
JP5390346B2 true JP5390346B2 (ja) 2014-01-15

Family

ID=43305372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009263134A Expired - Fee Related JP5390346B2 (ja) 2009-06-11 2009-11-18 パッケージ基板の製造方法

Country Status (3)

Country Link
US (1) US8168513B2 (enExample)
JP (1) JP5390346B2 (enExample)
TW (1) TWI365026B (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008003971A1 (de) * 2008-01-11 2009-07-16 Ledon Lighting Jennersdorf Gmbh Leuchtdiodenanordnung mit Schutzrahmen
TWI365026B (en) * 2009-06-11 2012-05-21 Unimicron Technology Corp Method for fabricating packaging substrate and base therefor
TWI390692B (zh) 2009-06-23 2013-03-21 欣興電子股份有限公司 封裝基板與其製法暨基材
KR101216926B1 (ko) * 2011-07-12 2012-12-28 삼성전기주식회사 캐리어 부재와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법
KR101776322B1 (ko) 2011-09-02 2017-09-07 엘지이노텍 주식회사 칩 패키지 부재 제조 방법
TWI442482B (zh) * 2011-10-17 2014-06-21 Advance Materials Corp 封裝基板之製法
US8685761B2 (en) * 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
JP5955050B2 (ja) * 2012-03-26 2016-07-20 京セラ株式会社 配線基板の製造方法
JP6054080B2 (ja) * 2012-07-20 2016-12-27 新光電気工業株式会社 支持体及びその製造方法、配線基板の製造方法、電子部品装置の製造方法、配線構造体
TWI484600B (zh) * 2012-08-15 2015-05-11 Unimicron Technology Corp 無核心封裝基板及其製法
CN103681586B (zh) * 2012-08-30 2016-07-06 欣兴电子股份有限公司 无核心封装基板及其制法
CN103681559B (zh) * 2012-09-25 2016-11-09 宏启胜精密电子(秦皇岛)有限公司 芯片封装基板和结构及其制作方法
TWI461135B (zh) * 2013-03-01 2014-11-11 Nan Ya Printed Circuit Board 製作電路板之方法
CN104254197B (zh) * 2013-06-27 2017-10-27 碁鼎科技秦皇岛有限公司 电路板及其制作方法
TWI474449B (zh) * 2013-09-27 2015-02-21 旭德科技股份有限公司 封裝載板及其製作方法
TWI474450B (zh) * 2013-09-27 2015-02-21 旭德科技股份有限公司 封裝載板及其製作方法
TWI571994B (zh) * 2015-06-30 2017-02-21 旭德科技股份有限公司 封裝基板及其製作方法
KR101672641B1 (ko) * 2015-07-01 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
KR102396894B1 (ko) * 2016-08-05 2022-05-11 미츠비시 가스 가가쿠 가부시키가이샤 지지 기판, 지지 기판이 부착된 적층체 및 반도체 소자 탑재용 패키지 기판의 제조 방법
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
DE102018215943A1 (de) * 2018-09-19 2020-03-19 Robert Bosch Gmbh Verfahren zum Fügen und elektrischen Kontaktieren von Einzelfolien eines Folienstapels und dessen Verwendung
US10624213B1 (en) * 2018-12-20 2020-04-14 Intel Corporation Asymmetric electronic substrate and method of manufacture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7351300B2 (en) * 2001-08-22 2008-04-01 Semiconductor Energy Laboratory Co., Ltd. Peeling method and method of manufacturing semiconductor device
JP3854910B2 (ja) * 2002-08-21 2006-12-06 日本特殊陶業株式会社 配線基板の製造方法及び配線基板
JP2004087701A (ja) * 2002-08-26 2004-03-18 Nec Toppan Circuit Solutions Toyama Inc 多層配線構造の製造方法および半導体装置の搭載方法
JP4267903B2 (ja) * 2002-11-29 2009-05-27 日本特殊陶業株式会社 多層配線基板の製造方法
JP2004186265A (ja) * 2002-11-29 2004-07-02 Ngk Spark Plug Co Ltd 多層配線基板の製造方法
JP2004214273A (ja) * 2002-12-27 2004-07-29 Ngk Spark Plug Co Ltd 片面積層配線基板の製造方法
JP4866268B2 (ja) * 2007-02-28 2012-02-01 新光電気工業株式会社 配線基板の製造方法及び電子部品装置の製造方法
TWI365026B (en) * 2009-06-11 2012-05-21 Unimicron Technology Corp Method for fabricating packaging substrate and base therefor

Also Published As

Publication number Publication date
US20100314037A1 (en) 2010-12-16
US8168513B2 (en) 2012-05-01
TW201044940A (en) 2010-12-16
TWI365026B (en) 2012-05-21
JP2010287874A (ja) 2010-12-24

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