JP5367955B2 - 動作特性とフリッカーノイズ特性が向上したアナログトランジスタを備える半導体素子及びその製造方法 - Google Patents
動作特性とフリッカーノイズ特性が向上したアナログトランジスタを備える半導体素子及びその製造方法 Download PDFInfo
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- JP5367955B2 JP5367955B2 JP2007135909A JP2007135909A JP5367955B2 JP 5367955 B2 JP5367955 B2 JP 5367955B2 JP 2007135909 A JP2007135909 A JP 2007135909A JP 2007135909 A JP2007135909 A JP 2007135909A JP 5367955 B2 JP5367955 B2 JP 5367955B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060045709A KR100703986B1 (ko) | 2006-05-22 | 2006-05-22 | 동작 특성과 플리커 노이즈 특성이 향상된 아날로그트랜지스터를 구비하는 반도체 소자 및 그 제조 방법 |
| KR10-2006-0045709 | 2006-05-22 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007324589A JP2007324589A (ja) | 2007-12-13 |
| JP2007324589A5 JP2007324589A5 (enExample) | 2010-07-08 |
| JP5367955B2 true JP5367955B2 (ja) | 2013-12-11 |
Family
ID=38160933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007135909A Active JP5367955B2 (ja) | 2006-05-22 | 2007-05-22 | 動作特性とフリッカーノイズ特性が向上したアナログトランジスタを備える半導体素子及びその製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US7952147B2 (enExample) |
| JP (1) | JP5367955B2 (enExample) |
| KR (1) | KR100703986B1 (enExample) |
| CN (1) | CN101079422B (enExample) |
| TW (1) | TWI365537B (enExample) |
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| JP5017958B2 (ja) * | 2006-08-08 | 2012-09-05 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| US7998821B2 (en) * | 2006-10-05 | 2011-08-16 | United Microelectronics Corp. | Method of manufacturing complementary metal oxide semiconductor transistor |
| JP2008182063A (ja) * | 2007-01-25 | 2008-08-07 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| US7671469B2 (en) * | 2007-12-31 | 2010-03-02 | Mediatek Inc. | SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect |
| JP2009164364A (ja) * | 2008-01-08 | 2009-07-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| US8273617B2 (en) | 2009-09-30 | 2012-09-25 | Suvolta, Inc. | Electronic devices and systems, and methods for making and using the same |
| US8421162B2 (en) | 2009-09-30 | 2013-04-16 | Suvolta, Inc. | Advanced transistors with punch through suppression |
| US8530286B2 (en) | 2010-04-12 | 2013-09-10 | Suvolta, Inc. | Low power semiconductor transistor structure and method of fabrication thereof |
| US8338239B2 (en) * | 2010-05-18 | 2012-12-25 | International Business Machines Corporation | High performance devices and high density devices on single chip |
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| DE102004052578B4 (de) * | 2004-10-29 | 2009-11-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Erzeugen einer unterschiedlichen mechanischen Verformung in unterschiedlichen Kanalgebieten durch Bilden eines Ätzstoppschichtstapels mit unterschiedlich modifizierter innerer Spannung |
| US20060105106A1 (en) * | 2004-11-16 | 2006-05-18 | Applied Materials, Inc. | Tensile and compressive stressed materials for semiconductors |
| US7494856B2 (en) * | 2006-03-30 | 2009-02-24 | Freescale Semiconductor, Inc. | Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor |
| US7528029B2 (en) * | 2006-04-21 | 2009-05-05 | Freescale Semiconductor, Inc. | Stressor integration and method thereof |
-
2006
- 2006-05-22 KR KR1020060045709A patent/KR100703986B1/ko active Active
-
2007
- 2007-05-22 JP JP2007135909A patent/JP5367955B2/ja active Active
- 2007-05-22 US US11/802,281 patent/US7952147B2/en active Active
- 2007-05-22 TW TW096118175A patent/TWI365537B/zh active
- 2007-05-22 CN CN2007101050578A patent/CN101079422B/zh active Active
-
2011
- 2011-04-21 US US13/091,327 patent/US8445968B2/en active Active
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2013
- 2013-05-20 US US13/897,908 patent/US20130249016A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| CN101079422A (zh) | 2007-11-28 |
| US8445968B2 (en) | 2013-05-21 |
| KR100703986B1 (ko) | 2007-04-09 |
| US20130249016A1 (en) | 2013-09-26 |
| US7952147B2 (en) | 2011-05-31 |
| US20110233611A1 (en) | 2011-09-29 |
| TWI365537B (en) | 2012-06-01 |
| CN101079422B (zh) | 2012-04-18 |
| TW200818497A (en) | 2008-04-16 |
| JP2007324589A (ja) | 2007-12-13 |
| US20080036006A1 (en) | 2008-02-14 |
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