JP5357121B2 - 半導体装置の製造方法、および電気機器 - Google Patents
半導体装置の製造方法、および電気機器 Download PDFInfo
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- JP5357121B2 JP5357121B2 JP2010208574A JP2010208574A JP5357121B2 JP 5357121 B2 JP5357121 B2 JP 5357121B2 JP 2010208574 A JP2010208574 A JP 2010208574A JP 2010208574 A JP2010208574 A JP 2010208574A JP 5357121 B2 JP5357121 B2 JP 5357121B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Description
図1〜図5は、本発明の実施形態1による半導体装置の製造方法を説明する図であり、図5(c)は、この実施形態1の半導体装置の製造方法により得られる半導体装置の断面構造を示している。なお、図5(c)に示す断面構造における隣接するMOSトランジスタの平面レイアウトは、図6(a)に示す隣接するトランジスタのレイアウトと同様なものである。
100a、100b 素子領域
100c、100f、100g トレンチ分離領域
101 シリコン基板
103 熱酸化膜
103a 熱酸化物層
104 第1のシリコン窒化膜
105 トレンチ溝
106 側壁熱酸化膜
107 埋め込み酸化膜
108a、108c Pウエル領域
108b、108d Nウェル領域
109 第2のシリコン窒化膜
110 厚い熱酸化膜
110a 薄い熱酸化膜
111a 高電圧トランジスタの形成領域
111b 低電圧トランジスタの形成領域
112a、112c N型ソース拡散領域
112b、112d N型ドレイン拡散領域
115a、115c P型ソース拡散領域
115b、115d P型ドレイン拡散領域
113、113a コンタクト電極
114、114a メタル配線
116、116a ゲート絶縁膜
117、117a ゲート電極
118、118a サイドウォール
R1〜R5 レジスト膜
Claims (9)
- 半導体基板上に形成された複数の半導体素子をトレンチ分離領域により分離した半導体装置を製造する方法であって、
該半導体装置は、該複数の半導体素子として、
高電圧で動作する高電圧半導体素子と、
低電圧で動作する低電圧半導体素子とを含み、
該半導体基板の表面に、該半導体素子が形成されるべき素子領域を分離するようトレンチ分離溝を形成するステップと、
該トレンチ分離溝に誘電体材料を埋め込んでトレンチ分離領域を形成するステップと、
該半導体基板の表面に、該トレンチ分離領域を覆い、かつ該トレンチ分離領域からはみ出して該トレンチ分離領域に接する素子領域に所定のオーバーラップ量で重なるよう選択的に酸化防止膜を形成するステップと、
該酸化防止膜をマスクとして、該高電圧半導体素子が形成されるべき高電圧素子領域および該低電圧半導体素子が形成されるべき低電圧素子領域のいずれにも、該高電圧半導体素子で必要となる耐圧を満たす厚い熱酸化膜を形成するステップと、
該低電圧素子領域に形成した厚い熱酸化膜を除去して、該低電圧半導体素子で必要となる耐圧を満たす薄い熱酸化膜を形成するステップと
を含み、
該酸化防止膜と該素子領域とがオーバーラップするオーバーラップ領域では、該酸化防止膜の下側に、該酸化防止膜の下側以外の素子領域に形成される熱酸化膜の膜厚より厚い酸化物層が形成されている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記トレンチ分離領域を形成するステップは、
前記半導体基板であるシリコン基板に形成したトレンチ分離溝内面に熱酸化によりトレンチ内熱酸化膜を形成するステップを有し、
該レンチ内熱酸化膜を形成した後に、該トレンチ分離溝内に誘電体材料を埋め込んでトレンチ分離領域を形成するステップである、半導体装置の製造方法。 - 請求項2に記載の半導体装置の製造方法において、
前記トレンチ分離領域を形成するステップは、
前記トレンチ分離溝内面のエッチングダメージが吸収されるよう該トレンチ分離溝内面に熱酸化により犠牲熱酸化膜を形成するステップを含み、
該犠牲熱酸化膜を除去した後、該トレンチ分離溝内面に前記トレンチ内熱酸化膜を形成し、その後、該トレンチ分離溝内に誘電体材料を埋め込んでトレンチ分離領域を形成するステップである、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記トレンチ分離溝を形成するステップは、
前記半導体基板であるシリコン基板上に第1の熱酸化膜を形成するステップと、
該第1の熱酸化膜上に第1のシリコン窒化膜を形成するステップと、
該第1のシリコン窒化膜を、前記素子領域に対応する部分に開口が形成されるようパターニングするステップと、
該パターニングした第1のシリコン窒化膜をマスクとして、該第1の熱酸化膜および該シリコン基板を選択的にエッチングして該トレンチ分離溝を形成するステップとを含み、
該第1の熱酸化膜の一部が、前記オーバーラップ領域で前記酸化防止膜の下側に位置する前記酸化物層となっている、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記低電圧半導体素子で必要となる熱酸化膜の厚さより厚い熱酸化膜は10nm以上の膜厚を有する、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記酸化防止膜の厚さは、0.02um以上である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記オーバーラップ量は、0.2um以上である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記高電圧半導体素子は、5V以上かつ40V以下の範囲内のゲート電圧で動作する、該半導体装置の入出力部を構成する高電圧MOSトランジスタであり、
前記低電圧半導体素子は、1.2V以上かつ3.3V以下の範囲内のゲート電圧で動作する低電圧MOSトランジスタである、半導体装置の製造方法。 - 半導体装置を搭載した電気機器であって、
該半導体装置は、請求項1〜8のいずれかに記載の半導体装置の製造方法により製造されたものである、電機機器。
Priority Applications (5)
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JP2010208574A JP5357121B2 (ja) | 2010-09-16 | 2010-09-16 | 半導体装置の製造方法、および電気機器 |
CN201180043848.7A CN103125018B (zh) | 2010-09-16 | 2011-09-09 | 制造半导体装置和电子设备的方法 |
PCT/JP2011/005079 WO2012035731A1 (ja) | 2010-09-16 | 2011-09-09 | 半導体装置の製造方法、および電気機器 |
US13/824,206 US9012301B2 (en) | 2010-09-16 | 2011-09-09 | Method of manufacturing a semiconductor apparatus and electronic equipment |
TW100132897A TWI458046B (zh) | 2010-09-16 | 2011-09-13 | Semiconductor device manufacturing method and electrical machine |
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JP2010208574A JP5357121B2 (ja) | 2010-09-16 | 2010-09-16 | 半導体装置の製造方法、および電気機器 |
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JP5357121B2 true JP5357121B2 (ja) | 2013-12-04 |
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JP (1) | JP5357121B2 (ja) |
CN (1) | CN103125018B (ja) |
TW (1) | TWI458046B (ja) |
WO (1) | WO2012035731A1 (ja) |
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TWI797941B (zh) * | 2022-01-03 | 2023-04-01 | 力晶積成電子製造股份有限公司 | 半導體裝置的製造方法 |
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JPH11340456A (ja) * | 1998-05-22 | 1999-12-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2000349164A (ja) * | 1999-06-08 | 2000-12-15 | Nec Corp | 素子分離絶縁膜を有する半導体装置の製造方法 |
KR100338767B1 (ko) | 1999-10-12 | 2002-05-30 | 윤종용 | 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법 |
KR100348269B1 (ko) * | 2000-03-22 | 2002-08-09 | 엘지전자 주식회사 | 루데니움 산화물을 이용한 쇼트키 콘택 방법 |
JP2002222942A (ja) * | 2001-01-25 | 2002-08-09 | Nec Corp | 半導体装置およびその製造方法 |
KR100387531B1 (ko) * | 2001-07-30 | 2003-06-18 | 삼성전자주식회사 | 반도체소자 제조방법 |
TWI287880B (en) * | 2004-03-18 | 2007-10-01 | Showa Denko Kk | Group III nitride semiconductor light-emitting device and method of producing the same |
KR100648283B1 (ko) * | 2005-03-16 | 2006-11-23 | 삼성전자주식회사 | 비휘발성 메모리 장치를 형성하는 방법 및 그에 의해형성된 비휘발성 메모리 장치 |
JP2010027688A (ja) * | 2008-07-15 | 2010-02-04 | Toshiba Corp | 半導体装置の製造方法 |
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- 2011-09-09 US US13/824,206 patent/US9012301B2/en not_active Expired - Fee Related
- 2011-09-09 WO PCT/JP2011/005079 patent/WO2012035731A1/ja active Application Filing
- 2011-09-09 CN CN201180043848.7A patent/CN103125018B/zh not_active Expired - Fee Related
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US9012301B2 (en) | 2015-04-21 |
US20130183807A1 (en) | 2013-07-18 |
CN103125018A (zh) | 2013-05-29 |
TW201222723A (en) | 2012-06-01 |
TWI458046B (zh) | 2014-10-21 |
WO2012035731A1 (ja) | 2012-03-22 |
JP2012064814A (ja) | 2012-03-29 |
CN103125018B (zh) | 2016-03-23 |
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