JP5325736B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP5325736B2
JP5325736B2 JP2009232163A JP2009232163A JP5325736B2 JP 5325736 B2 JP5325736 B2 JP 5325736B2 JP 2009232163 A JP2009232163 A JP 2009232163A JP 2009232163 A JP2009232163 A JP 2009232163A JP 5325736 B2 JP5325736 B2 JP 5325736B2
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semiconductor chip
insulating layer
resin
support
semiconductor
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Japanese (ja)
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JP2011082287A (ja
JP2011082287A5 (enExample
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晃明 千野
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009232163A priority Critical patent/JP5325736B2/ja
Priority to US12/897,085 priority patent/US8293576B2/en
Publication of JP2011082287A publication Critical patent/JP2011082287A/ja
Priority to US13/584,115 priority patent/US8536715B2/en
Publication of JP2011082287A5 publication Critical patent/JP2011082287A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2009232163A 2009-10-06 2009-10-06 半導体装置及びその製造方法 Active JP5325736B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009232163A JP5325736B2 (ja) 2009-10-06 2009-10-06 半導体装置及びその製造方法
US12/897,085 US8293576B2 (en) 2009-10-06 2010-10-04 Semiconductor device and method of manufacturing the same
US13/584,115 US8536715B2 (en) 2009-10-06 2012-08-13 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009232163A JP5325736B2 (ja) 2009-10-06 2009-10-06 半導体装置及びその製造方法

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JP2011082287A JP2011082287A (ja) 2011-04-21
JP2011082287A5 JP2011082287A5 (enExample) 2012-08-16
JP5325736B2 true JP5325736B2 (ja) 2013-10-23

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US8653542B2 (en) * 2011-01-13 2014-02-18 Tsmc Solid State Lighting Ltd. Micro-interconnects for light-emitting diodes
FR2974942B1 (fr) * 2011-05-06 2016-07-29 3D Plus Procede de fabrication de plaques reconstituees avec maintien des puces pendant leur encapsulation
JP2013038300A (ja) * 2011-08-10 2013-02-21 Fujitsu Ltd 電子装置及びその製造方法
JP2013187434A (ja) * 2012-03-09 2013-09-19 Fujitsu Ltd 半導体装置、半導体装置の製造方法、電子装置及び基板
US8901435B2 (en) 2012-08-14 2014-12-02 Bridge Semiconductor Corporation Hybrid wiring board with built-in stopper, interposer and build-up circuitry
JP5987696B2 (ja) * 2013-01-09 2016-09-07 富士通株式会社 半導体装置の製造方法
JP5662551B1 (ja) * 2013-12-20 2015-01-28 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
US9171739B1 (en) * 2014-06-24 2015-10-27 Stats Chippac Ltd. Integrated circuit packaging system with coreless substrate and method of manufacture thereof
TWI557853B (zh) * 2014-11-12 2016-11-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US10217710B2 (en) 2014-12-15 2019-02-26 Bridge Semiconductor Corporation Wiring board with embedded component and integrated stiffener, method of making the same and face-to-face semiconductor assembly using the same
US10269722B2 (en) 2014-12-15 2019-04-23 Bridge Semiconductor Corp. Wiring board having component integrated with leadframe and method of making the same
US9947625B2 (en) 2014-12-15 2018-04-17 Bridge Semiconductor Corporation Wiring board with embedded component and integrated stiffener and method of making the same
US10062663B2 (en) 2015-04-01 2018-08-28 Bridge Semiconductor Corporation Semiconductor assembly with built-in stiffener and integrated dual routing circuitries and method of making the same
US10177130B2 (en) 2015-04-01 2019-01-08 Bridge Semiconductor Corporation Semiconductor assembly having anti-warping controller and vertical connecting element in stiffener
US9913385B2 (en) 2015-07-28 2018-03-06 Bridge Semiconductor Corporation Methods of making stackable wiring board having electronic component in dielectric recess
US10177090B2 (en) 2015-07-28 2019-01-08 Bridge Semiconductor Corporation Package-on-package semiconductor assembly having bottom device confined by dielectric recess
US20170133334A1 (en) * 2015-11-09 2017-05-11 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
CN108231606A (zh) * 2016-11-29 2018-06-29 Pep创新私人有限公司 芯片封装方法及封装结构
KR102216172B1 (ko) 2017-07-14 2021-02-15 주식회사 엘지화학 절연층 제조방법 및 반도체 패키지 제조방법
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
US11610855B2 (en) 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11232957B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US11114315B2 (en) 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
IT201900005156A1 (it) * 2019-04-05 2020-10-05 St Microelectronics Srl Procedimento per fabbricare leadframe per dispositivi a semiconduttore
IT201900024292A1 (it) 2019-12-17 2021-06-17 St Microelectronics Srl Procedimento per fabbricare dispositivi a semiconduttore e dispositivo a semiconduttore corrispondente
WO2022024369A1 (ja) * 2020-07-31 2022-02-03 国立大学法人東北大学 半導体装置の製造方法、半導体装置を備えた装置の製造方法、半導体装置、半導体装置を備えた装置

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Also Published As

Publication number Publication date
JP2011082287A (ja) 2011-04-21
US20110079913A1 (en) 2011-04-07
US8536715B2 (en) 2013-09-17
US20120306100A1 (en) 2012-12-06
US8293576B2 (en) 2012-10-23

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