JP5300470B2 - 半導体パッケージ及び同パッケージを形成する方法 - Google Patents
半導体パッケージ及び同パッケージを形成する方法 Download PDFInfo
- Publication number
- JP5300470B2 JP5300470B2 JP2008513466A JP2008513466A JP5300470B2 JP 5300470 B2 JP5300470 B2 JP 5300470B2 JP 2008513466 A JP2008513466 A JP 2008513466A JP 2008513466 A JP2008513466 A JP 2008513466A JP 5300470 B2 JP5300470 B2 JP 5300470B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- gold
- gold layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07336—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
Landscapes
- Die Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/140,351 | 2005-05-26 | ||
| US11/140,351 US7339267B2 (en) | 2005-05-26 | 2005-05-26 | Semiconductor package and method for forming the same |
| PCT/US2006/010745 WO2006127107A2 (en) | 2005-05-26 | 2006-03-24 | Semiconductor package and method for forming the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008543049A JP2008543049A (ja) | 2008-11-27 |
| JP2008543049A5 JP2008543049A5 (https=) | 2009-05-07 |
| JP5300470B2 true JP5300470B2 (ja) | 2013-09-25 |
Family
ID=37452517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008513466A Expired - Fee Related JP5300470B2 (ja) | 2005-05-26 | 2006-03-24 | 半導体パッケージ及び同パッケージを形成する方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7339267B2 (https=) |
| JP (1) | JP5300470B2 (https=) |
| CN (1) | CN100539008C (https=) |
| TW (1) | TWI433279B (https=) |
| WO (1) | WO2006127107A2 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7949601B2 (en) * | 2007-04-21 | 2011-05-24 | Hartford Fire Insurance Company | Method and system for providing minimum contract values in an annuity with lifetime benefit payments |
| DE102009044086A1 (de) * | 2009-09-23 | 2011-03-24 | United Monolithic Semiconductors Gmbh | Verfahren zur Herstellung eines elektronischen Bauteils und nach diesem Verfahren hergestelltes elektronisches Bauteil |
| US8680674B2 (en) | 2012-05-31 | 2014-03-25 | Freescale Semiconductor, Inc. | Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices |
| US9093429B2 (en) | 2012-06-27 | 2015-07-28 | Freescale Semiconductor, Inc. | Methods and structures for reducing heat exposure of thermally sensitive semiconductor devices |
| US9589860B2 (en) * | 2014-10-07 | 2017-03-07 | Nxp Usa, Inc. | Electronic devices with semiconductor die coupled to a thermally conductive substrate |
| US9875987B2 (en) | 2014-10-07 | 2018-01-23 | Nxp Usa, Inc. | Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices |
| US9698116B2 (en) | 2014-10-31 | 2017-07-04 | Nxp Usa, Inc. | Thick-silver layer interface for a semiconductor die and corresponding thermal layer |
| CN107579032B (zh) * | 2017-07-27 | 2019-04-09 | 厦门市三安集成电路有限公司 | 一种化合物半导体器件的背面制程方法 |
| JP7168280B2 (ja) * | 2018-06-26 | 2022-11-09 | 住友電工デバイス・イノベーション株式会社 | 半導体装置、および、半導体チップの搭載方法 |
| CN110767604B (zh) * | 2019-10-31 | 2022-03-18 | 厦门市三安集成电路有限公司 | 化合物半导体器件和化合物半导体器件的背面铜制程方法 |
| US20230253359A1 (en) * | 2022-02-04 | 2023-08-10 | Wolfspeed, Inc. | Semiconductor die including a metal stack |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3881884A (en) * | 1973-10-12 | 1975-05-06 | Ibm | Method for the formation of corrosion resistant electronic interconnections |
| JPH01123418A (ja) * | 1987-11-09 | 1989-05-16 | Nec Corp | 半導体装置の製造方法 |
| US5027189A (en) * | 1990-01-10 | 1991-06-25 | Hughes Aircraft Company | Integrated circuit solder die-attach design and method |
| US5156998A (en) * | 1991-09-30 | 1992-10-20 | Hughes Aircraft Company | Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes |
| JP3374880B2 (ja) * | 1994-10-26 | 2003-02-10 | 三菱電機株式会社 | 半導体装置の製造方法、及び半導体装置 |
| US6140703A (en) * | 1996-08-05 | 2000-10-31 | Motorola, Inc. | Semiconductor metallization structure |
| JP3724110B2 (ja) * | 1997-04-24 | 2005-12-07 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US6040239A (en) * | 1997-08-22 | 2000-03-21 | Micron Technology, Inc. | Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication |
| JP4438133B2 (ja) * | 1999-08-19 | 2010-03-24 | シャープ株式会社 | ヘテロ接合型バイポーラトランジスタおよびその製造方法 |
| US6312830B1 (en) * | 1999-09-02 | 2001-11-06 | Intel Corporation | Method and an apparatus for forming an under bump metallization structure |
| US6960824B1 (en) * | 2000-11-15 | 2005-11-01 | Skyworks Solutions, Inc. | Structure and method for fabrication of a leadless chip carrier |
| JP2003045875A (ja) * | 2001-07-30 | 2003-02-14 | Nec Kagobutsu Device Kk | 半導体装置およびその製造方法 |
| EP1318544A1 (en) * | 2001-12-06 | 2003-06-11 | STMicroelectronics S.r.l. | Method for manufacturing semiconductor device packages |
| US6607941B2 (en) * | 2002-01-11 | 2003-08-19 | National Semiconductor Corporation | Process and structure improvements to shellcase style packaging technology |
| KR100611778B1 (ko) * | 2002-09-24 | 2006-08-10 | 주식회사 하이닉스반도체 | 반도체장치 제조방법 |
-
2005
- 2005-05-26 US US11/140,351 patent/US7339267B2/en not_active Expired - Lifetime
-
2006
- 2006-03-24 WO PCT/US2006/010745 patent/WO2006127107A2/en not_active Ceased
- 2006-03-24 JP JP2008513466A patent/JP5300470B2/ja not_active Expired - Fee Related
- 2006-03-24 CN CNB2006800182164A patent/CN100539008C/zh not_active Expired - Fee Related
- 2006-04-17 TW TW095113584A patent/TWI433279B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| TW200644192A (en) | 2006-12-16 |
| CN101185153A (zh) | 2008-05-21 |
| CN100539008C (zh) | 2009-09-09 |
| US7339267B2 (en) | 2008-03-04 |
| WO2006127107A3 (en) | 2007-06-14 |
| TWI433279B (zh) | 2014-04-01 |
| US20060270194A1 (en) | 2006-11-30 |
| JP2008543049A (ja) | 2008-11-27 |
| WO2006127107A2 (en) | 2006-11-30 |
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