JP5291929B2 - チャンネル膜を有する半導体装置の製造方法 - Google Patents
チャンネル膜を有する半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 154
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 86
- 229910052710 silicon Inorganic materials 0.000 claims description 86
- 239000010703 silicon Substances 0.000 claims description 86
- 238000000034 method Methods 0.000 claims description 77
- 238000005498 polishing Methods 0.000 claims description 47
- 239000000758 substrate Substances 0.000 claims description 47
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 38
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 239000002002 slurry Substances 0.000 claims description 9
- 230000003746 surface roughness Effects 0.000 claims description 9
- 230000001678 irradiating effect Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- -1 amine compound Chemical class 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000004094 surface-active agent Substances 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
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- 125000006850 spacer group Chemical group 0.000 description 2
- VXEGSRKPIUDPQT-UHFFFAOYSA-N 4-[4-(4-methoxyphenyl)piperazin-1-yl]aniline Chemical compound C1=CC(OC)=CC=C1N1CCN(C=2C=CC(N)=CC=2)CC1 VXEGSRKPIUDPQT-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
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- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
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- 229910000077 silane Inorganic materials 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 239000005049 silicon tetrachloride Substances 0.000 description 1
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- 238000004381 surface treatment Methods 0.000 description 1
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Description
本発明の他の目的は、前記チャンネルシリコン膜を含むスタック型の半導体装置の形成方法を提供することにある。
前記第1単結晶シリコン膜を形成するために、前記絶縁膜パターン及び単結晶シリコンパターン上に非晶質シリコン膜を形成する工程、及び前記単結晶シリコンパターンをシードに用いて非晶質シリコン膜を結晶化して単結晶シリコンに相変化させる工程を行うことができる。
前記相変化させる段階は、レーザビームを前記非晶質シリコン膜に照射することによって行うことができる。
前記犠牲膜は、10〜1000Åの厚さに形成することができる。
前記犠牲膜は、シリコン酸化物またはシリコン窒化物を含むことができる。
前記1次研磨は、前記犠牲膜に比べて前記単結晶シリコン膜の研磨率の高いスラリーを用いて行うことができる。
前記第2単結晶シリコン膜の突出部位が前記第1単結晶シリコン膜の最初突出の高さの5〜50%が残るように前記第1研磨工程を行うことが望ましい。
前記犠牲膜パターンを除去する工程は、湿式エッチング工程を通じて行うことができる
。
前記1次研磨は、前記犠牲膜に比べて前記第1単結晶シリコン膜の研磨率の高いスラリーを用いて行うことができる。
前記チャンネルシリコン膜の上部表面の粗さ二乗平均平方根が0.5〜5Åになるまで前記第2研磨工程を行うことができる。
(チャンネルシリコン膜の形成方法)
図1から図7は、本発明の一実施例によるチャンネルシリコン膜の形成方法を示す断面図である。
犠牲膜パターン112aを除去するとき、第2単結晶シリコン膜114の表面損傷を最小化しなければならない。しかし、プラズマを用いる乾式エッチング工程を行って犠牲膜パターン112aを除去する場合、第2単結晶シリコン膜114の表面にアタックが加えられる可能性がある。そのため、犠牲膜パターン112aの除去は、湿式エッチング工程を通じて行うことが望ましい。一例として、犠牲膜パターン112aがシリコン窒化物で形成された場合、リン酸を含むエッチング液で除去することができ、犠牲膜パターン112aがシリコン酸化物で形成された場合、LALエッチング液で除去することができる。
前記第2次化学機械的研磨工程は、チャンネルシリコン膜116の表面粗さの二乗平均平方根が0.5〜5Åになるまで行われる。望ましくは、前記第2次化学的機械的研磨工程は、チャンネルシリコン膜116の表面粗さの二乗平均平方根の値が約0.5〜2Åになるまで行うことができる。
図8から図14は、本発明の一実施例によるスタック型メモリ素子の製造方法を説明するための断面図である。
図8を参照すると、単結晶シリコン基板200上にシャロートレンチ素子分離工程を行い阻止分離膜202を形成する。前記工程によって下部のアクティブ領域が定義される。
図10を参照してより詳細に説明すると、第1開口部216内部を満たす第1エピタキシャルパターン218を形成する。第1エピタキシャル膜パターン218及び第1層間絶縁膜214上に非晶質シリコン膜(図示せず)を形成する。前記非晶質シリコン膜をレーザビームを用いて単結晶シリコンで相変化することで、表面に突出部位220aを有する第1単結晶シリコン膜220を形成する。その後、第1単結晶シリコン膜220上に研磨阻止膜として用いられる犠牲膜222を形成する。
前述した方法を通じて2層に積層された構造のトランジスタを形成することができる。本実施例では、単にトランジスタを形成する方法及びこれを電気的に接続させる方法について説明したが、これを応用して半導体メモリ素子を形成することができる。特に、本実施例による方法は、単位セル内に6つのトランジスタを含むSRAM装置を形成するときに積極的に適用することができる。
(実験例1)
基板上に29.5nmの厚さを有するチャンネルシリコン膜を形成し、前記シリコン膜上に第1トランジスタを形成した。
基板上に25.9nmの厚さを有するチャンネルシリコン膜を形成し、前記チャンネルシリコン膜上に第2トランジスタを形成した。
基板上に19.6nmの厚さを有するチャンネルシリコン膜を形成し、前記チャンネルシリコン膜上に第3トランジスタを形成した。
基板上に16.3nmの厚さを有するチャンネルシリコン膜を形成し、前記チャンネルシリコン膜上に第4トランジスタを形成した。
実験例1から4に開示されている第1から第4トランジスタでターンオン状態の電流を測定して表1に示した。
(実施例1)
図1から図3を参照して説明したことと類似の方法を行って基板上に第1単結晶シリコン膜を形成した。前記第1単結晶シリコン膜で突出しない部位は約516Åの厚さを有し、粗さの二乗平均平方根は約240Åであった。その後、実施例1の図4から図7で説明したような方法で前記第1単結晶シリコン膜を平坦化することによって二乗平均平方根(以下、RMS)が5Åであるチャンネルシリコン膜を形成した。
実施例1の図1から図3を参照して説明したような方法を行って基板上に第1単結晶シリコン膜を形成した。前記第1単結晶シリコン膜で突出しない部位は約516Åの厚さを有し、粗さの二乗平均平方根は約240Åであった。その後、前記第1単結晶シリコン膜に化学機械的研磨工程を行うことで、RMSが5Åであるチャンネルシリコン膜を形成した。即ち、比較例1の方法では、実施例1とは違って1回の化学機械的研磨工程のみを行い、犠牲膜を形成しなかった。
実施例1の図1から図3に説明したような方法を行って基板上に第1単結晶シリコン膜を形成した。前記第1単結晶シリコン膜で突出しない部位は、約516Åの厚さを有し、粗さの二乗平均平方根は約240Åであった。その後、前記第1単結晶シリコン膜に化学機械的研磨工程を行うことでRMSが9Åであるチャンネルシリコン膜を形成した。即ち、比較例2の方法では、実施例1とは異なって1回の化学機械的研磨工程のみを行い、犠牲膜を形成しなかった。
実施例1及び比較例1、2の方法によって基板上に形成されたチャンネルシリコン膜の厚さ、第1単結晶シリコン膜の研磨厚さを測定した。
Claims (11)
- 単結晶シリコン基板上に、前記単結晶シリコン基板の表面を部分的に露出させる開口部を有する絶縁膜パターンを形成する段階と、
前記開口部の内部に単結晶シリコンパターンを形成する段階と、
前記絶縁膜パターン及び前記単結晶シリコンパターン上に、非晶質シリコン膜を形成する段階と、
前記単結晶シリコンパターンをシードに用いて前記非晶質シリコン膜を結晶化して単結晶シリコンに相変化させ、上部表面から延長して突出した部位を含む単結晶シリコン膜を形成する段階と、
前記単結晶シリコン膜の上部表面に犠牲膜を形成する段階と、
前記単結晶シリコン膜の前記突出した部位の一部及び前記犠牲膜の一部が除去されるように前記単結晶シリコン膜及び前記犠牲膜を1次研磨して前記突出した部位の一部が残留する前記単結晶シリコン膜及び犠牲膜パターンを形成する段階と、
前記犠牲膜パターンを除去する段階と、
前記単結晶シリコン膜を研磨して前記突出した部位に残留する一部分を除去し、平坦なチャンネルシリコン膜を形成する段階と、を含むことを特徴とするチャンネル膜を有する半導体装置の製造方法。 - 前記単結晶シリコンパターンは、前記開口部の底面に露出された基板をシードに用いる選択的エピタキシャル成長工程を通じて形成されることを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記非晶質シリコン膜は、500〜5000Åの厚さに蒸着することを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記相変化させる段階は、レーザビームを前記非晶質シリコン膜に照射することによって行われることを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記犠牲膜は、10〜1000Åの厚さに形成されることを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記犠牲膜は、シリコン酸化物またはシリコン窒化物を蒸着して形成することを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記1次研磨は、前記犠牲膜に比べて前記単結晶シリコン膜については研磨率の高いスラリーを用いて行われることを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記犠牲膜としてシリコン酸化物を形成する場合、前記1次研磨はシリカ研磨剤0.5〜20重量%、アミン化合物0.001〜1.0重量%、界面活性剤0.001〜1.0重量%、及び余分の水を含み、pHが8〜12のスラリー組成物を用いることを特徴とする請求項7に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記単結晶シリコン膜の前記突出した部位は、当該突出した部位の最初の突出高さの5〜50%が残るように前記1次研磨が行われることを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記チャンネルシリコン膜の上部表面粗さの二乗平均平方根が0.5〜5Åになるまで2次研磨工程を行うことを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
- 前記犠牲膜パターンを除去する段階は、湿式エッチング工程を通じて行われることを特徴とする請求項1に記載のチャンネル膜を有する半導体装置の製造方法。
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JPH11251599A (ja) * | 1998-03-06 | 1999-09-17 | Toshiba Corp | 薄膜半導体装置の製造方法 |
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JP2000357798A (ja) * | 1998-06-30 | 2000-12-26 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタ及びその製造方法 |
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US6919238B2 (en) * | 2002-07-29 | 2005-07-19 | Intel Corporation | Silicon on insulator (SOI) transistor and methods of fabrication |
US6855607B2 (en) * | 2003-06-12 | 2005-02-15 | Advanced Micro Devices, Inc. | Multi-step chemical mechanical polishing of a gate area in a FinFET |
KR100663349B1 (ko) | 2004-02-24 | 2007-01-02 | 삼성전자주식회사 | 선택적 에피택시얼 성장 기술 및 부분 평탄화 기술을사용하여 박막 트랜지스터들을 갖는 반도체 집적회로를제조하는 방법들 및 그에 의해 제조된 반도체 집적회로들 |
KR100718265B1 (ko) * | 2005-05-23 | 2007-05-14 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
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