TW432491B - Method for formation of source/drain-on-insulator (SDOI) transistors - Google Patents

Abstract

The present invention discloses a method for formation of a source/drain-on-insulator (SDOI) transistor, which comprises using an insulation layer (i.e. dielectric layer) with an opening; growing an epitaxial silicon layer through the opening; and using the epitaxial silicon layer region in the opening as an active region of a device. Since the epitaxial silicon layer is made by annealing of an amorphous silicon layer, its thickness is easy to be controlled. Furthermore, the channel region of the transistor formed according to the method of the present invention can be reliably divided from the substrate such that the device has good characteristics.

Description

43 24 91 V. Description of the invention (1) The present invention relates to a transistor manufacturing technology of an integrated circuit, and particularly to a method of forming a silicon-based insulator (sincon-on-insulator, hereinafter referred to as SOI) A method for manufacturing a source / drain on insulator (hereinafter abbreviated as SD0I) transistor. I) The integrated circuit is formed on a semiconductor substrate. The general material is silicon, and an active area is formed on the surface, which includes circuit elements. These circuit elements can be connected by multiple patterned conductive layers. To the substrate, and separated by a dielectric layer. These active regions are filled with trenches of dielectric material to ensure electrical isolation from each other and to avoid interaction between adjacent active regions. However, as the size of integrated circuit components is shrinking, trenches are also shrinking. Isolation areas formed by shallow trench isolation (STI) are produced by flattening together with the active area of adjacent semiconductor substrates. . The use of S01 technology can reduce the generation of undesired st ray capacitance, and it can be used at higher frequencies, better package density, less contact, latch-up, and less regulation. Shots work. However, for forming a typical SOIj technique, its junction leakage and junction capacitance are still too high for newer manufacturing costs. Day

A method for forming a half-condyle is described in US Pat. No. 5,712,173, which has the advantage of the SOI structure. It uses an interelectrode as a curtain, which is heated after implantation of oxygen ions to form a thin self-aligned horse. '㈣) Buried oxidation area'

432491 V. Description of the invention (2) The oxidation (f i e 1 d ox i de) area is extended and self-aligned to the side surface of the gate electrode. In another embodiment, 'the buried oxide layer extends from a point adjacent to the field oxide region and / or a region partially below the gate electrode. In U.S. Patent No. 4,506,435, it is described that the groove is filled with oxidized stone, and then used, such as shed stone glass (b 〇r 〇si 1 ica 1: eg 1 ass) The groove is filled, and then the contact glass is heated and softened to flow, so as to achieve the purpose of flattening. After that, the borosilicate glass layer and the silicon nitride mask layer are etched, so that the borosilicate glass fills the trenches, and is flattened with the halogenated silicon mask layer.

In U.S. Patent No. 5,882,958, a method for forming a metal-oxide-semiconductor (MOS) of SOI is described, which utilizes damascene patterning of source / drain regions. An amorphous silicon (amotphous) film on the surface of an oxide layer grown on the surface of a silicon wafer, wherein the oxide layer has been etched into a trench pattern. This method enables the amorphous silicon layer to contact the underlying silicon substrate through a plurality of tiny oxide layer openings, and subsequent transistor channel regions can be aligned with these openings.

In US Patent No. 5, 89 1, 76 3, a process for manufacturing a MOS transistor with a SOI with a polycrystalline silicon gate is described. The channel region is formed in an underlying single crystal silicon wafer, and the source / The drain diffusion region is embedded in an amorphous silicon film deposited on an oxide layer on the surface of the silicon wafer. US Patent No. 5,869,359 describes a method for manufacturing a 1-element device having a raised (e 1 evated) source / drain and a polycrystalline silicon gate; wherein the SO I oxide layer is located only under the source / drain region 'But it is not under the channel area, and it can control the length of the channel.

4 3 24 9 1 V. Description of the invention (3) are described in US Patent Nos. 5, 6 1 0, 087 and 5, 728, 6 1 3. A method 'which can produce a narrow substrate on the sdi layer, Lateral bipolar junction transistor and short-path M0SFET element °

A method for forming a semiconductor element on an SOI layer thin film formed by the epitaxial re-growth of solid phase is described in U.S. Patent No. 5, 6 1 0, 087; it forms a layer of amorphous silicon to communicate with the underlying layer. Part of the hair substrate is in direct contact. Next, temper this amorphous stone layer (a η nea 1) to form a single crystal layer of stupid stone layer. Since the amorphous stone layer is only in contact with a part of the silicon substrate below it, it can only grow in a regular way. The crystalline layer 'therefore has low density lattice defects. In US Patent No. 5, 6 1 2, 230, a process for forming a semiconductor element is described, which is to grow a semiconductor body (semic ο nduct 〇rb 〇dy) by using a non-single-crystal substance on the inner wall of the opening. ). In U.S. Patent No. 4,7 4 9,4 4 No. 1, a "mushroom" monocrystalline silicon is described for manufacturing MOSFET devices such as S (H). In U.S. Patent No. 5 No., 686, 343 describes an insulating layer

Isolation method of a semiconductor layer 'It forms a window in a first insulating layer which is one of the epitaxial seed layers, then deposits a semiconductor layer, and grows an epitaxial crystal with the same structure as the semiconductor substrate under the window After that, the active area of the epitaxial layer is formed through the lithography process, and then on the other side of the active area and the first and second marginal layers. A first insulating layer is formed thereon; then, a third insulating layer is formed by the oxidation process in the empty window, thereby achieving the purpose of insulating the active region from the semiconductor layer.

4 3 24 91

In view of the above-mentioned conventional technologies, an object of the present invention is to manufacture an improved SOI transistor element, which completely isolates the active region from the substrate by means of a dielectric layer and an active region separated from each other by STI. Another object of the present invention is to manufacture a S 0 I transistor element with a low junction leakage current and a low junction capacitance. 'Another object of the present invention is to produce a S0I transistor, which is completed by using the growth of a distant spar crystal between active regions. Still another object of the present invention is to produce an SO I transistor which grows epitaxial stones through a channel region. Still another object of the present invention is to fabricate an SOI transistor with an active / drain (SD0I) on an insulating layer, which isolates the source / drain region from the substrate by using a dielectric layer. Still another object of the present invention is to manufacture an SDO I transistor which has a lower cost than the SOI. Still another object of the present invention is to manufacture an SO I transistor, which is completed by growing a stupid crystal layer through an oxide layer opening in a field region to an active region. In order to achieve the purpose of the present invention, a method is provided, which is suitable for a semiconductor substrate and includes the following steps: forming an insulating dielectric layer | on the surface of the semiconductor substrate; defining a pattern of the insulating dielectric layer so that ( An opening is formed on the surface of the semiconductor substrate; an epitaxial silicon layer is formed to cover the insulating dielectric layer and fill the opening; a shallow trench is formed in the semiconductor substrate to form a gate structure in the worm crystal layer A surface of the epitaxial layer; and a pair of spaced source / drain electrodes formed in the epitaxial layer.

Page 7 4 3 24 9 1 V. Description of the invention (5) In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, 'a preferred embodiment is given below, in conjunction with the accompanying drawings, to make The detailed description is as follows: Brief description of the drawings: FIG. 5 is a scraped drawing of the manufacturing process of the SDOI transistor according to the first embodiment of the present invention; FIG. 6 is the layout of the first embodiment of the present invention; No? = 44. The drawing is a sectional view of the manufacturing process of the SDO I transistor of the second embodiment of the present invention, and FIG. 12 is a layout of the second embodiment of the present invention. Explanation of symbols 10, 110 to silicon substrate; 12, 112 to dielectric layer; 14a, 12 amorphous silicon layer; 14b, 122 to epitaxial silicon layer; 16, 126 to pad oxide layer; 18, 28 to silicon nitride Layer; 20, 114 ~ open 21 trench; 22, 132 ~ shallow trench area; 24 ~ gate structure; 241, 134 ~ gate oxide layer; 242, 136 ~ gate electrode; 26, 138a, 138b ~ insulation spacer 28 ~ source / drain; 124 &, 1241) ~ multicrystalline silicon layer; 124a ', 124b' ~ multicrystalline silicon layer; 12 5 ~ silicon oxide sidewall layer; 140a, 140 light source / drain doping doping Regions; 142a, 142b ~ source / electrode highly doped regions; 118a, 118b ~ dielectric layer; 112 ~ inner region; 120a, 120b ~ dielectric layer; 112 ~ outer region. First Embodiment Please refer to FIG. 1 ', a semiconductor structure 10 is provided, such as a semiconductor

432491 V. Description of the invention (6) A bulk wafer or a silicon substrate, and its surface is covered with a dielectric layer 12, and its thickness is preferably between 50 and 500A. The semiconductor structure includes an uppermost silicon substrate 10 'and the dielectric layer 12 is an oxide layer formed by an oxidation method or chemical vapor deposition (CVD). Thereafter, the pattern of the dielectric layer 12 is defined to form an opening 20 ', and its width is " w ", which is between about 1000 and 2000 A.

After that, the $ M bond step of the present invention is performed: a worm-crystal breaking layer is formed on the surface of the dielectric layer 12: first, an amorphous silicon layer 14a is formed on the surface of the pattern 彳 ~ 哥 -dielectric layer 12 and filled with Full mouth. For example, in a cvd process, and using dichlorosilicon (SiHAl2) or siloxane (SiH4) as a reactant, an amorphous silicon layer is deposited at a temperature of 500 to 600 ° C, and the thickness is 300. 0 ~ 丨 5 〇〇A. Then, referring to FIG. 2, a tempering step is performed, for example, the silicon substrate is sent into a pure gas or vacuum chamber, and its temperature is reacted below to form a planarization on the surface of the dielectric layer 12. The epitaxial silicon layer 14b has a thickness tSi between 500 and 100 A. The epitaxial silicon layer 14b has the same lattice structure as that of the broken substrate 10 below, which is (丨 〇〇), and the epitaxial silicon skin 14b has a single crystal structure. In this method, the thickness of the layer is almost the same as that of the previous sinker; therefore, its thickness is very easy to control. And if the contact system is located in the channel area, there will be no channel drift in the contact between the epitaxial silicon layer 14b and the underlying silicon substrate. Next, as shown in FIG. 2, a pad oxide layer 16 is formed on the surface of the epitaxial silicon wafer 14b. For example, a conventional oxidation process is used to form a pad oxide layer with a layer thickness of about 100 A, and then, Multiple etch

43 24 9 1 V. Description of the invention (7) The cover layer 1 8 ′ is, for example, a silicon nitride layer, which is deposited on the surface of the pad oxide layer 16 ′ by the CVI method, and has a thickness of about 1,000 a. The aforementioned pad oxide layer 16 is used to join the (b 1 nd) silicon nitride layer 18 and the epitaxial silicon layer 丨 4b, and can reduce the stress therebetween; and the pad oxide layer 16 can also be used as a 3 1 Etching stop layer of the oxide in the process during chemical mechanical polishing (CMP) ° Production Next, please refer to FIG. 3, which defines the silicon nitride layer 18, the pad oxide layer 16, Pattern with epitaxial silicon layer 14b; for example, a patterned photoresist layer pR is formed before the surface of silicon nitride layer 18, and then, photolithography and etching processes are used, dry etching or wet etching The silicon nitride layer 18 ′, the pad oxide layer 16, and the epitaxial silicon layer 14 b are etched together with the silicon substrate 10 to form a trench 2 丨 with a depth from the surface of the substrate 2,000 to 3,000. Between A, and the remaining epitaxial layer 14b defines the outer diameter 0D (outer diameter) of the subsequently formed transistor. Please refer to FIG. 4 'after the photoresist layer pR is removed by a conventional method, an oxide layer is deposited and etched back to fill the trench 2 to form ST [area 22' then 'remove the silicon nitride layer丨 8 and the pad oxide layer 丨 6; for example, a phosphoric acid aPO4) plus a hydrogen peroxide (H2O2) solution is used to perform a thirst etching process on the silicon nitride layer 18, and then the wet etching is performed with a diluted hydrofluoric acid solution The pad oxide layer 16 ′ sequentially removes the silicon nitride layer 18 and the pad oxide layer. Next, please refer to FIG. 5, which is an active region forming element formed by the patterned epitaxial silicon layer 14 b; for example, thermal oxidation is used at 7000 to 1000 ° C. , Growing a silicon oxide layer between about 15 and 80 A thick as a subsequent transistor element

43 24 9 1 V. Description of the invention (8) Gate oxide layer (not shown). Next, a low-pressure chemical vapor deposition (LPCVD) method was used to deposit a polycrystalline silicon layer (not shown) between 1200 and 300,000 at a temperature of 550 to 650 ° C. After that, optical microscopy was used again. The lithography and etching process defines a gate electrode 24, which includes a gate oxide layer 241 and a gate electrode 242 °. Then, LPCVD or plasma enhanced chemical vapor deposition (PECVD) is used at 600-800 ° C. A silicon oxide layer (not shown) with a thickness of about 800 to 25 00 A is deposited below, and the reactive silicon oxide is used to etch the silicon oxide layer to the gate electrode 24 by using reactive ion etching (RI E). The sidewalls form insulating spacers 2 6. After that, a step of ion implantation is performed; for example, 'arsenic ions are implanted into the epitaxial layer 1 4 b at a dose of 1 to 14 Ke16 at an energy of 5 to 40 KeV to form a source with a shallow junction / & gt And polar regions 28. The SOI transistor formed according to the method of the present invention has no problem of the source / drain junction, so its coupling capacitance is low and no leakage current occurs. In addition, the thickness of the silicon layer in the active region is easy to control, the lattice defect is small, and the manufacturing process is compatible with the conventional integrated circuit technology, so the manufacturing cost is greatly reduced. Fig. 6 is a diagram showing the layout of the transistor according to the present invention; the relationship between the source / drain 28, the gate 242, and the channel can be clearly seen from the figure. A feature of the present invention is that after forming an oxide layer with an opening, an epitaxial silicon layer is grown from the opening, and the epitaxial silicon layer area between the openings is used as the active area of the 7L piece, so that an s〇1 transistor. The openings mentioned in U.S. Patent No. 5,882,958 for growing epitaxial silicon layers require

43 24 91 V. Description of the invention (9) The thickness of the epitaxial layer formed in the active region is not easy to control. Because the channel is not completely isolated from the substrate, it can not be completely called an SOI transistor. The second embodiment is, for example, that a dream substrate is formed by thermal oxidation using optical lithography as shown in FIG. 7. Referring to FIG. 7, a patterned dielectric layer Π 2 is formed on the surface of a semiconductor substrate 110; An emulsified layer is on the surface of the hair substrate 110. Subsequent operations and etching processes 'define the pattern of the dielectric layer 11 2 and its defined opening π system is used as a channel region for subsequent formation of the transistor. It has a length w' and a range of about 1000 to 2 〇〇〇A between. The channel region 114 simultaneously separates the inner regions ii8a and 118b of the dielectric layer 112 and the outer regions 1220a and 12b. Next, referring to FIG. 8A, an amorphous silicon layer is formed on the surface of the dielectric layer 1 12 and fills the channel region u 4; for example, in a CVD process, and using two gas silicon methane (SiH2Cl2) or Silane (SiH4) is a reactant, and an amorphous silicon layer 121 is deposited at 500 ~ 600 ° C, and its thickness is about 700A. After that, a tempering step is performed. For example, the silicon substrate 11 is sent into a pure gas or vacuum chamber, and the temperature is reacted at 550 ~ 650 ° C to form a layer on the surface of the dielectric layer 11 2. The thickness of the planarized epitaxial silicon layer 1 2 2 and the polycrystalline silicon layers 124 a and 124 b ′ is between 500 and 1000 A, as shown in FIG. 8B. Among them, the lattice structure of the epitaxial silicon layer 1 2 2 is the same as that of the silicon substrate 11 〇 below, both of which are (100) ^ In this method, the epitaxial silicon above the dielectric layer 丨 2 The thickness of the layer 122 and the polycrystalline silicon layers 124a and 124b are almost the same as

12 Page 12 ^ 324 9 1 V. Description of the invention (10) --- The deposited thickness is the same, so its thickness is easy to control. Next, as shown in FIG. 9, a pad oxide layer 126 is formed on the surfaces of epitaxial silicon, 1 22 and polycrystalline silicon layers 1 24a, 24b. For example, a conventional oxidation process or a CVD process is used to form After a pad oxide layer 126 ′ having a thickness of about 100 people, an etching mask layer 28 is formed, for example, a silicon nitride layer, which is deposited on the surface of the pad oxide layer 26 by CVD, and the thickness is About 1000A. The aforementioned pad oxide layer 126 is used to join the silicon nitride layer 128 and the epitaxial stone layer 1 2 2, the polycrystalline silicon layer 1 2 4 a, 1 2 4 b ′ and reduce the stress therebetween. Then 'define the pattern of the silicon nitride layer 1 2 8 and the pad oxide layer 1 2 6; for example,' a patterned photoresist layer pR is formed before the surface of the nitride layer 128, and then 'optography and etching are used' In the manufacturing process, the nitride nitride layer 128 and the pad oxide layer 126 (not shown) are dry-etched or wet-etched, and then the silicon nitride layer is used as an etching mask to etch down the polycrystalline silicon layer not covered by the silicon nitride. 24a, 1 24b, and form a left and right outer polycrystalline silicon layer 24a, 1 24b ′ ′ and define the outer diameter of the subsequent transistor. Next, you can choose to form the structure as shown in Figure 10A or Figure 10B. First, as shown in Figure 10A, after sequentially removing the photoresist layer pr, the silicon nitride layer 128, and the pad oxide layer 126, To increase the isolation from neighboring elements, 'insulating sidewall layers are formed on both sides of the polycrystalline silicon layers 1 24a' and 1 24b ', for example, formed on both sides of the polycrystalline silicon layer 124a and 124b' by thermal oxidation. One oxidation hard sidewall layer 1 2 5. If the form shown in FIG. 10B is selected, after the silicon oxide sidewall layer 1 2 5 is formed, then the polycrystalline silicon layers 124 a and 124 b and portions of silicon that are not protected by the silicon nitride layer 1 2 6 are etched downward. Substrate 1 1 0 to a depth of approximately

Page 13 4 3 24 91 V. Description of the invention (π) 2000 ~ 3000 A ′ to form a shallow trench 132, which is filled with oxide, so that it can be isolated from other components. Thereafter, the photoresist layer PR, the silicon nitride layer 1 28, and the pad oxide layer 1 26 are sequentially removed, and a structure shown in FIG. 10B is formed.

Following the structure shown in Figure 10A, please refer to Figure 11. First use the thermal oxidation method to grow an oxide layer between about 15 ~ 80A thick at 700 ~ 1000 ° c as the subsequent formation of the transistor element Gate oxide (not shown). Next, a low-pressure chemical vapor deposition (LPCVD) method was used to deposit a polycrystalline silicon layer (not shown) between 550 and 650 ° C (approximately 1200 to 300 A). The photolithography and etching processes define a gate electrode, which includes a gate oxide layer 134 and a gate electrode 136. It should be noted that the 'silicon oxide sidewall layer 2 5' is used to protect the polycrystalline silicon layer 12 4a, 124b from being damaged by etching. Next, lightly doped ions are implanted into the polycrystalline hard layers 1 24a, 1 24b to form a lightly doped region LDD (not shown in the figure) of the source / drain 'reusing LpcVE) or pECVD method at 600. A silicon oxide layer (not shown) with a thickness of about 800 to 2500Λ is deposited under ~ 800i, and the reactive ion gas etching method (RIE) is used to etch the oxide gas with CHf3. Insulator spacers (spacerM 38a, 138b) are formed on the side walls of the gate electrode 36. After that, an ion implantation step is performed; for example

For example, using insulating spacers 138a and 138b as a mask, heavily doped ions in the lightly doped regions of the source / drain to form the source / drain, which include lightly doped regions 140a, 140b, and heavily doped regions. Areas 142a, U2b. The reference to FIG. 12 shows the layout of the SOI transistor according to the present invention. From the figure, it can be clearly seen that between the source / drain and the gate and the channel.

Page 14 4 3 24 9 1 V. The relationship between the description of the invention (12). Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

4 3 24 S 1 VI. Scope of patent application 1. A method for manufacturing a transistor with a source / drain on an insulating layer, which is suitable for a semiconductor substrate, including the following steps: forming an insulating dielectric layer on the semiconductor substrate Surface; defining a pattern of the insulating dielectric layer to form an opening on the surface of the semiconductor substrate; forming an epitaxial silicon layer to cover the insulating dielectric layer and filling the opening; forming a shallow trench in the semiconductor substrate Forming a gate structure on the surface of the epitaxial layer; and forming a pair of source / drain electrodes spaced apart from each other in the epitaxial layer. 2. The method according to item 1 of the scope of patent application, wherein the method for forming a distant worm crystal layer includes the following steps: forming an amorphous silicon layer to cover the insulating dielectric layer and filling the opening; and heating the non-crystalline layer A crystalline silicon layer to form an epitaxial silicon layer. 3. The method according to item 2 of the scope of patent application, wherein forming a shallow trench in the semiconductor substrate system comprises the following steps: forming a trench in the epitaxial silicon layer, the insulating dielectric layer, and part of In the semiconductor substrate; and depositing and etching back an oxide layer to form a shallow trench in the semiconductor substrate. 4. The method according to item 1 of the scope of patent application, wherein the method for forming a gate structure includes the following steps: forming a gate oxide layer on the surface of the epitaxial silicon layer; Page 16 4 3 24 9 VI. Scope of patent application Form a definition of the surface of the fragmentation layer and deposit and an insulating side wall 5 · For example, the crystalline silicon layer is on the surface of the dielectric layer and the dream layer. 6 · If the medium-edge dielectric layer is a silicon layer, and its thickness is 7. If the medium-conductor substrate is a surface, the layer is patterned on the closed oxide: so that the insect layer and the gate oxide layer form a gate electrode; and > This ★ also creates an oxide layer on the side wall of the > ir > electrode to make the gate complex crystal and complex crystal ζί7 as a retrospective engraving layer. The patented temperature range is requested. The patented method is based on the oxygen level at 50. The patented method is silicon based. ^ +. I method, where the non-vehicle has surrounded the second office, and the insulation is surrounded by 550 ~ 650 = The thickness of the crystal is 500 ~ 10U, v'i- > In the basin, as described in the first item of the absolute range, the basic oxidation method or the chemical vapor deposition method is ~ 500. Between A. The method described in item 1 of the half-range, wherein--plate. The method of making a source / drain transistor on the edge layer is suitable for a silicon substrate, and includes the following steps: The electrical layer is on the surface of the silicon substrate; the pattern of the electrical layer is on the surface of the dream substrate. A method for forming an amorphous silicon layer by defining an insulating dielectric, forming an opening, covering the insulating dielectric layer and filling the opening, and heating the amorphous silicon layer to form the opening and the surface of the insulating dielectric layer An epitaxial silicon layer; forming a trench in the epitaxial silicon layer, the insulating dielectric layer, and a portion Page 17 432491 ------- VI. The patent application scope of the silicon substrate trench deposition and etch back an oxide layer to form a shallow formation of a gate structure on the surface of the epitaxial layer in the silicon substrate And forming a pair of spaced source / drain electrodes within the epitaxial layer. 9. The method according to item 8 of the scope of patent application, wherein the amorphous stone is reacted at a temperature ranging from 55 ° to 6500 ° C, and a thickness is formed on the surface of the insulating dielectric layer. The epitaxial Meng Zhan flattened between 500 ～ 1000A. 10. The method according to item 9 of the scope of the patent application, wherein the insulating dielectric layer is a silicon oxide layer formed by an oxidation method or a chemical vapor deposition method, and has a thickness of 50 to 500 A. between. 11. The method according to item 10 of the scope of patent application, wherein the method for raising a gate structure comprises the following steps: forming a gate oxide layer on the surface of the epitaxial silicon layer; forming a polycrystalline silicon layer on The surface of the gate oxide layer; defining the pattern of the polycrystalline silicon layer and the gate oxide layer to form a gate electrode on the surface of the epitaxial silicon layer; and depositing and etching an oxide layer on the side wall of the gate electrode An insulating sidewall layer is formed. 12. —A method for manufacturing a transistor with a source / drain on an insulating layer, suitable for a stone substrate, including the following steps: forming an oxide layer on the surface of the silicon substrate; defining the pattern of the oxide layer, Forming a silicon substrate surface Page 18 432491 VI. Patent application opening; forming an amorphous silicon layer to cover the oxide layer and filling the opening; heating the amorphous silicon layer to form an epitaxial silicon layer on the opening and the surface of the halogenated layer Forming a trench in the epitaxial silicon layer, the oxide layer, and a part of the sand substrate; depositing and etching back a silicon oxide layer to form a shallow trench in the silicon substrate; forming a gate oxide layer on Forming the surface of the telecrystalline silicon layer; forming a polycrystalline silicon layer on the surface of the gate oxide layer; defining a pattern of the polycrystalline silicon layer and the gate oxide layer to form a gate electrode on the surface of the epitaxial silicon layer; depositing and An oxide layer is etched back to form an insulating sidewall layer on the sidewall of the gate electrode; and a pair of source / drain electrodes spaced apart from each other are formed in the epitaxial layer. 1 3. The method according to item 12 of the scope of the patent application, wherein the amorphous silicon layer reacts at a temperature range of 5 50 to 6 50 ° C, and a thickness is formed on the surface of the oxide layer. The telomerite layer D 1 planarized between 500 and 1000 A 4. The method according to item 13 of the scope of patent application, wherein the oxide layer is formed by an oxidation method or a chemical vapor deposition method The thickness of the oxide stone layer is between 50 ~ 500A. 15. The method according to item 14 of the scope of patent application, wherein the method further comprises the following steps after forming the epitaxial silicon layer: Page 19 4 3 24 91 t. The scope of the patent application forms a pad oxide layer on the surface of the epitaxial silicon layer; a mask mask layer is formed on the surface of the hafnium oxide layer; and a patterned photoresist layer is formed On the surface of the silver engraved mask layer. 16. The method according to item 15 of the scope of the patent application, wherein the etching mask layer is a silicon nitride layer deposited on the surface of the pad oxide layer by a chemical vapor deposition method, and has a thickness of about 1000A. Page 20