TW432491B - Method for formation of source/drain-on-insulator (SDOI) transistors - Google Patents
Method for formation of source/drain-on-insulator (SDOI) transistors Download PDFInfo
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43 24 91 五、發明說明(1) 本發明係有關於一種積體電路之電晶體製造技術’特 別是有關於一種形成絕緣層上有矽 (sincon-on-insulator, 其後以SOI簡稱之)與絕緣層上 源/ 没極(source/drain on insulator,其後以 SD0I 簡稱 之)之電晶體之製造方法。 I) 積體電路係形成於半導體基板上,一般的材質係為 矽,且在其表面形成有主動區,其中包括電路元件,該些 電路元件可藉由多層圖案化的(patterned)傳導層連接至 基板,其間並以介電層予以隔離。而這些主動區間則藉由 填滿介電物質的溝槽(trench)以確保彼此間之電性隔絕, 並避免鄰近之主動區與之發生交互作用。然隨著積體電路 元件尺寸的縮小,溝槽亦日亦縮小,如淺溝槽隔離 (shallow trench isolation,STI)所形成的隔離區域, 係與鄰近之半導體基板的主動區共同平坦化而產生。 利用S01的技術可降低不理想之寄生電容(s t ray capacitance)的產生’且其可在較.高頻率、較佳封裝密 度、較少接觸、自由拴鎖(latch-up)、以及較少轄射量 運作。但是,對於形成典型的S0Ij術而言,其接W面漏 流(junction leakage)與接面電容對於較新的 之製造費用仍舊過高。 日曰43 24 91 V. Description of the invention (1) The present invention relates to a transistor manufacturing technology of an integrated circuit, and particularly to a method of forming a silicon-based insulator (sincon-on-insulator, hereinafter referred to as SOI) A method for manufacturing a source / drain on insulator (hereinafter abbreviated as SD0I) transistor. I) The integrated circuit is formed on a semiconductor substrate. The general material is silicon, and an active area is formed on the surface, which includes circuit elements. These circuit elements can be connected by multiple patterned conductive layers. To the substrate, and separated by a dielectric layer. These active regions are filled with trenches of dielectric material to ensure electrical isolation from each other and to avoid interaction between adjacent active regions. However, as the size of integrated circuit components is shrinking, trenches are also shrinking. Isolation areas formed by shallow trench isolation (STI) are produced by flattening together with the active area of adjacent semiconductor substrates. . The use of S01 technology can reduce the generation of undesired st ray capacitance, and it can be used at higher frequencies, better package density, less contact, latch-up, and less regulation. Shots work. However, for forming a typical SOIj technique, its junction leakage and junction capacitance are still too high for newer manufacturing costs. Day
於美國專利第5, 712, 173號中敘述一種形成半邋 件的方法,其具有S0I構造之優點,係利用間電極作: 幕,在植入氧離子之後加熱以形成薄的自我對準 马’ ㈣)掩埋氧化區域’其由源々及極區下A method for forming a half-condyle is described in US Pat. No. 5,712,173, which has the advantage of the SOI structure. It uses an interelectrode as a curtain, which is heated after implantation of oxygen ions to form a thin self-aligned horse. '㈣) Buried oxidation area'
432491 五、發明說明(2) 氧化(f i e 1 d ox i de)區域延伸,並自我對準該閘電極的側 表面。在另一個實施例中’此掩埋氧化層則由鄰近場氧化 層區域的一個點及/或部分位於閘電極之下的區域延伸。 於美國專利第4, 5 0 6, 435號中係敘述先以氧化石夕填入 溝槽,之後再用,例如是棚石夕酸玻璃(b 〇 r 〇 s i 1 i c a 1: e g 1 a s s )將溝槽填滿,接著對此觸石夕酸玻璃加熱使之軟化後 流動,以達平坦化之目的。之後,蝕刻該硼矽酸玻璃層與 氮化矽罩幕層,以使該硼矽酸玻璃填滿溝槽,並以氡化矽 罩幕層將之平坦化。432491 V. Description of the invention (2) The oxidation (f i e 1 d ox i de) area is extended and self-aligned to the side surface of the gate electrode. In another embodiment, 'the buried oxide layer extends from a point adjacent to the field oxide region and / or a region partially below the gate electrode. In U.S. Patent No. 4,506,435, it is described that the groove is filled with oxidized stone, and then used, such as shed stone glass (b 〇r 〇si 1 ica 1: eg 1 ass) The groove is filled, and then the contact glass is heated and softened to flow, so as to achieve the purpose of flattening. After that, the borosilicate glass layer and the silicon nitride mask layer are etched, so that the borosilicate glass fills the trenches, and is flattened with the halogenated silicon mask layer.
於美國專利第5, 882, 958號中係敘述一種形成SOI之金 氧半電晶體(M0S)的方法,其利用源/汲極區之鑲嵌式 (damascene)圖案化,該圖形係形成於沈積在一矽晶圓表 面上成長的氧化層表面之非晶矽(amotphous )薄膜,其中 該氧化層已先經蝕刻出一溝槽的圖案。這個方法能使非晶 矽層通過多個微小的氧化層開口(opening)而與下層的矽 基板接觸,且後續的電晶體通道區能對準這.些開口。In U.S. Patent No. 5,882,958, a method for forming a metal-oxide-semiconductor (MOS) of SOI is described, which utilizes damascene patterning of source / drain regions. An amorphous silicon (amotphous) film on the surface of an oxide layer grown on the surface of a silicon wafer, wherein the oxide layer has been etched into a trench pattern. This method enables the amorphous silicon layer to contact the underlying silicon substrate through a plurality of tiny oxide layer openings, and subsequent transistor channel regions can be aligned with these openings.
於美國專利第5, 89 1, 76 3號中係敘述一種具有複晶矽 閘極的SOI之M0S電晶體的製程,其中,通道區係形成於下 層之單晶矽晶圓内,而源/汲極擴散區則於沈積在矽晶圓 表面之氧化層上方的非晶矽薄膜中鑲嵌形成。 於美國專利第5,869,359號中係敘述一種具有升起式 (e 1 evated)源/汲極與複晶矽閘極的1元件的製造方法; 其中,SO I氧化層僅位於源/汲極區下方’但並不位於 通道區之下,且其較能控制通道的長度。In US Patent No. 5, 89 1, 76 3, a process for manufacturing a MOS transistor with a SOI with a polycrystalline silicon gate is described. The channel region is formed in an underlying single crystal silicon wafer, and the source / The drain diffusion region is embedded in an amorphous silicon film deposited on an oxide layer on the surface of the silicon wafer. US Patent No. 5,869,359 describes a method for manufacturing a 1-element device having a raised (e 1 evated) source / drain and a polycrystalline silicon gate; wherein the SO I oxide layer is located only under the source / drain region 'But it is not under the channel area, and it can control the length of the channel.
4 3 24 9 1 五、發明說明(3) 於美國專利第5, 6 1 0, 087號與5, 728, 6 1 3號中係敘述. 種方法’其可在sdi層上製造窄基底、側向雙載子接面電 晶體(bipolar junction transistor)、以及短通道之 M0SFET 元件 °4 3 24 9 1 V. Description of the invention (3) are described in US Patent Nos. 5, 6 1 0, 087 and 5, 728, 6 1 3. A method 'which can produce a narrow substrate on the sdi layer, Lateral bipolar junction transistor and short-path M0SFET element °
於美國專利第5, 6 1 0, 087號中係敘述一種於固相蠢晶 (epitaxial)再成長所形成的SOI層薄膜上形成半導體元件 的方法;其形成一層非晶矽’以與下層的部分發基板直接 接觸。接下來將此非晶石夕層回火(a η n e a 1)以形成蠢晶石夕之 單晶層’由於非晶石夕層僅與其下之部分矽基板接觸,其僅 能成長規則之磊晶層’因此具有低密度之晶格缺陷。、 於美國專利第5, 6 1 2, 230號中係敘述一種形成半導體 元件之製程’其係藉由開口之内侧壁上的非單晶物質,成 長一半導體本體(s e m i c ο n d u c t 〇 r b 〇 d y )。 於美國專利第4,7 4 9,4 4 1號中係敘述一種形成”蕈”形 (mushroom)單晶矽以用於製造如S(H之類的M〇SFET元件。 於美國專利第5, 686, 343號中係敘述一種絕緣層上之A method for forming a semiconductor element on an SOI layer thin film formed by the epitaxial re-growth of solid phase is described in U.S. Patent No. 5, 6 1 0, 087; it forms a layer of amorphous silicon to communicate with the underlying layer. Part of the hair substrate is in direct contact. Next, temper this amorphous stone layer (a η nea 1) to form a single crystal layer of stupid stone layer. Since the amorphous stone layer is only in contact with a part of the silicon substrate below it, it can only grow in a regular way. The crystalline layer 'therefore has low density lattice defects. In US Patent No. 5, 6 1 2, 230, a process for forming a semiconductor element is described, which is to grow a semiconductor body (semic ο nduct 〇rb 〇dy) by using a non-single-crystal substance on the inner wall of the opening. ). In U.S. Patent No. 4,7 4 9,4 4 No. 1, a "mushroom" monocrystalline silicon is described for manufacturing MOSFET devices such as S (H). In U.S. Patent No. 5 No., 686, 343 describes an insulating layer
半導體層的隔離方法’其於作為磊晶種層之一第一絕緣層 中形成 空®(window),接著沈積一半導體層,並於該空 ®下成長與該半導體基底具有相同構造的磊晶層;之後, 經由,學微影(ph〇t〇lith〇graphy)製程,形成該磊晶層的 主動區(active area);再於該主動區的另外一側及於該 第、邑緣層上形成一第一絕緣層;接著,藉由於空窗中進 行氧化製程而形成一第三絕緣層,因而達到主動區與半導 體層絕緣的目的。Isolation method of a semiconductor layer 'It forms a window in a first insulating layer which is one of the epitaxial seed layers, then deposits a semiconductor layer, and grows an epitaxial crystal with the same structure as the semiconductor substrate under the window After that, the active area of the epitaxial layer is formed through the lithography process, and then on the other side of the active area and the first and second marginal layers. A first insulating layer is formed thereon; then, a third insulating layer is formed by the oxidation process in the empty window, thereby achieving the purpose of insulating the active region from the semiconductor layer.
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有鑑於上述之各習知技術,本發明的一個目的在於製 造一種改良的SOI電晶體元件,其藉由介電層與利用STI隔 絕鄰近之主動區的方式,而完全將主動區與基板隔絕。 本發明之另一個目的在於製造一種具有I低接面漏電 流與較低接面電容的S 0 I電晶體元件。 ' 本發明之再一個目的在於製造出S〇I電晶體,其利用 主動區域間遙晶石夕的成長而完成。 本發明之再一個目的在於製造出一種SO I電晶體,其 藉由通道區成長磊晶石夕。 本發明之再一個目的在於製造出絕緣層上有源/汲極 (SD0I)之SOI電晶體,其藉由介電層的使用而將源/汲極區 與基板隔絕。 本發明之再一個目的在於製造一種SDO I電晶體,其花 費較SOI為低。 本發明之再一個目的在於製造一種SO I電晶體,其藉 由通過於場區域之氧化層開口成長一蠢晶石夕層至主動區而 完成。 為了達到本發明之目的,係提供了一種方法,適 用於一半導體基板上,包括下列步驟:形成一絕緣介電層 | 於該半導體基板之表面;定義該絕緣介電層之圖案,以於() 該半導體基板表面形成一開口;形成一磊晶矽層使覆蓋該 絕緣介電層並填滿該開口;形成一淺溝槽於該半導體基板 ’ 中’形成一閘極結構於該蟲晶層的表面;以及形成一對互 為相隔的源/汲極於該磊晶層内。In view of the above-mentioned conventional technologies, an object of the present invention is to manufacture an improved SOI transistor element, which completely isolates the active region from the substrate by means of a dielectric layer and an active region separated from each other by STI. Another object of the present invention is to manufacture a S 0 I transistor element with a low junction leakage current and a low junction capacitance. 'Another object of the present invention is to produce a S0I transistor, which is completed by using the growth of a distant spar crystal between active regions. Still another object of the present invention is to produce an SO I transistor which grows epitaxial stones through a channel region. Still another object of the present invention is to fabricate an SOI transistor with an active / drain (SD0I) on an insulating layer, which isolates the source / drain region from the substrate by using a dielectric layer. Still another object of the present invention is to manufacture an SDO I transistor which has a lower cost than the SOI. Still another object of the present invention is to manufacture an SO I transistor, which is completed by growing a stupid crystal layer through an oxide layer opening in a field region to an active region. In order to achieve the purpose of the present invention, a method is provided, which is suitable for a semiconductor substrate and includes the following steps: forming an insulating dielectric layer | on the surface of the semiconductor substrate; defining a pattern of the insulating dielectric layer so that ( An opening is formed on the surface of the semiconductor substrate; an epitaxial silicon layer is formed to cover the insulating dielectric layer and fill the opening; a shallow trench is formed in the semiconductor substrate to form a gate structure in the worm crystal layer A surface of the epitaxial layer; and a pair of spaced source / drain electrodes formed in the epitaxial layer.
第7頁 4 3 24 9 1 五、發明說明(5) 為讓本發明之上述目的、特徵、和優點能更明顯易 懂’下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下: 圖式之簡單說明: 第卜5圖係為依據本發明的第一實施例之SDOI電晶體 之製造流程刮面圖; 第6圖係為本發明之第一實施例之佈局; 第?=44·圖係本發明的第二實施例之SDO I電晶體 之製造流程剖面圖以及 第1 2圖係為本發明之第二實施例之佈局。 符號說明 10、110〜矽基板;12、112~介電層;14a、12卜非晶 矽層;14b、122〜磊晶矽層;16、126~墊氧化層;18、28〜 氮化矽層;20、114〜開口 21溝槽;22、132〜淺溝槽區域; 24〜閘極結構;241、134〜閘氧化層;242、136〜閘電極; 26、138a、138b~絕緣間隔物;28〜源/汲極;124&、1241)〜 複晶矽層;124a’ 、124b’〜複晶矽層;12 5〜氧化矽側壁 層;140a、140卜源/汲極之淡摻雜區域;142a、142b〜源/ 沒極之濃摻雜區域;118a、118b〜介電層;112〜之靠内側 區域;120a、120b〜介電層;112〜之靠外側區域。 第一實施例 請參看第1圖’係提供一半導體結構1 0,例如是半導Page 7 4 3 24 9 1 V. Description of the invention (5) In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, 'a preferred embodiment is given below, in conjunction with the accompanying drawings, to make The detailed description is as follows: Brief description of the drawings: FIG. 5 is a scraped drawing of the manufacturing process of the SDOI transistor according to the first embodiment of the present invention; FIG. 6 is the layout of the first embodiment of the present invention; No? = 44. The drawing is a sectional view of the manufacturing process of the SDO I transistor of the second embodiment of the present invention, and FIG. 12 is a layout of the second embodiment of the present invention. Explanation of symbols 10, 110 to silicon substrate; 12, 112 to dielectric layer; 14a, 12 amorphous silicon layer; 14b, 122 to epitaxial silicon layer; 16, 126 to pad oxide layer; 18, 28 to silicon nitride Layer; 20, 114 ~ open 21 trench; 22, 132 ~ shallow trench area; 24 ~ gate structure; 241, 134 ~ gate oxide layer; 242, 136 ~ gate electrode; 26, 138a, 138b ~ insulation spacer 28 ~ source / drain; 124 &, 1241) ~ multicrystalline silicon layer; 124a ', 124b' ~ multicrystalline silicon layer; 12 5 ~ silicon oxide sidewall layer; 140a, 140 light source / drain doping doping Regions; 142a, 142b ~ source / electrode highly doped regions; 118a, 118b ~ dielectric layer; 112 ~ inner region; 120a, 120b ~ dielectric layer; 112 ~ outer region. First Embodiment Please refer to FIG. 1 ', a semiconductor structure 10 is provided, such as a semiconductor
432491 五、發明說明(6) 體晶圓或矽基板,且其表面係覆蓋—層介電層12,其厚度 在50〜500A之間為佳。其中,該半導體結構包括一最上面 的矽基板1 0 ’而介電層1 2則為由氧化法或是化學氣相沈積 (CVD)所形成的氧化層。之後,定義該介電層12之圖形以 形成一開口 20 ’且其寬度係為"w” ,約在1〇〇〇〜2〇〇〇 A之 間。432491 V. Description of the invention (6) A bulk wafer or a silicon substrate, and its surface is covered with a dielectric layer 12, and its thickness is preferably between 50 and 500A. The semiconductor structure includes an uppermost silicon substrate 10 'and the dielectric layer 12 is an oxide layer formed by an oxidation method or chemical vapor deposition (CVD). Thereafter, the pattern of the dielectric layer 12 is defined to form an opening 20 ', and its width is " w ", which is between about 1000 and 2000 A.
之後’進行本發明$ Μ鍵步驟:在介電層12表面形成 一蟲晶破層:首先,先在圖案彳〜匕—哥-介電層12表面形成一非 晶矽層1 4a,並填滿開口 。例如,以cvd製程,並利用二 氯矽曱烧(SiHAl2)或矽曱烷(SiH4)為反應物,在5〇〇~6〇〇 °C下沈積一非晶矽層,其厚度在3 〇 0〜丨5 〇 〇 A之間。之後, 請參看第2圖,要進行回火的步驟,例如,將矽基板丨〇送 入一純氣或真空腔室中’且其溫度在下反應以 於介電層12之表面形成一平坦化的磊晶矽層14b,其厚度 tSi在500〜1 0 0 0 A之間。其中’磊晶矽層14b之晶格結構與 其下方之破基板1 0之晶格結構相同,係為(丨〇〇 ),且此磊 晶石夕膚14 b农好為單晶結構。於此方法中, 層 的…,匕之厚度幾乎與先前所沈;的m因 此其厚度疋很谷易控制的。而若接觸係位於通道區内,則 ·、 磊晶矽層14b與下方之矽基板之接觸將不會有通道飄移的 現象產生。 接下來’如第2圖所示,形成一層墊氧化層16於磊晶 矽廣14b之表面,例如,利用傳統的氧化製程ϋ製程, 形成-層厚度約為100Α之墊氧化層,之後,开多成一蝕刻After that, the $ M bond step of the present invention is performed: a worm-crystal breaking layer is formed on the surface of the dielectric layer 12: first, an amorphous silicon layer 14a is formed on the surface of the pattern 彳 ~ 哥 -dielectric layer 12 and filled with Full mouth. For example, in a cvd process, and using dichlorosilicon (SiHAl2) or siloxane (SiH4) as a reactant, an amorphous silicon layer is deposited at a temperature of 500 to 600 ° C, and the thickness is 300. 0 ~ 丨 5 〇〇A. Then, referring to FIG. 2, a tempering step is performed, for example, the silicon substrate is sent into a pure gas or vacuum chamber, and its temperature is reacted below to form a planarization on the surface of the dielectric layer 12. The epitaxial silicon layer 14b has a thickness tSi between 500 and 100 A. The epitaxial silicon layer 14b has the same lattice structure as that of the broken substrate 10 below, which is (丨 〇〇), and the epitaxial silicon skin 14b has a single crystal structure. In this method, the thickness of the layer is almost the same as that of the previous sinker; therefore, its thickness is very easy to control. And if the contact system is located in the channel area, there will be no channel drift in the contact between the epitaxial silicon layer 14b and the underlying silicon substrate. Next, as shown in FIG. 2, a pad oxide layer 16 is formed on the surface of the epitaxial silicon wafer 14b. For example, a conventional oxidation process is used to form a pad oxide layer with a layer thickness of about 100 A, and then, Multiple etch
43 24 9 1 五、發明說明(7) 罩幕層1 8 ’例如是氮化矽層,其利用CVI)法沈積於墊氧化 層16之表面’且其厚度約為1〇〇〇a。前述之墊氧化層16係 用以接合(b 1 nd )氮化矽層1 8與磊晶矽層丨4b,並可減低其 間之應力(stress);而墊氧化層16亦可作為3了1製程中之 氧化物在化學機械研磨(CMP)時之蝕刻停止層(etching stop layer) ° 产接下來,請參看第3圖,係為定義該氮化矽層1 8、墊 氧化層1 6、與磊晶矽層1 4b之圖形;例如,先於氮化矽層 1 8表面形成一圖案化的光阻層pR,之後,利用光學微影術 (Photolithography)與蝕刻製程,乾蝕刻或濕蝕刻該氮化 矽層18 '墊氧化層16、與磊晶矽層14b,並且連矽基板1〇 一併蝕刻,以形成一溝槽2丨,其距基板〗〇表面之深度在 2000〜3 000 A之間,而剩餘的磊晶層14b則定義出後續所形 成電晶體之外徑0D(outer diameter)。 請參考第4圖’在以習知之方法移除光阻層pR之後, 沈積並回蝕刻一氧化層使填滿該溝槽2〗而形成ST【區域 22 ’接著’移除該氮化矽層丨8與該墊氧化層丨6 ;例如,以 磷酸aPO4)加過氧化氫(H2〇2)溶液,對氮化矽層18進行渴 蝕刻製程,再以稀釋過的氫氟酸溶液濕蝕刻該墊氧化層 16 ’以依序移除氮化矽層18與該墊氧化層。 接下來,請參考第5圖,係於定義過圖形的磊晶矽層 14b所形成的主動區間形成元件;例如,利用熱氧化法 (thermal oxidation)在7〇0~1〇〇〇°C 下,成長一層厚約 1 5〜80 A之間的氧化矽層以作為後續所形成電晶體元件之43 24 9 1 V. Description of the invention (7) The cover layer 1 8 ′ is, for example, a silicon nitride layer, which is deposited on the surface of the pad oxide layer 16 ′ by the CVI method, and has a thickness of about 1,000 a. The aforementioned pad oxide layer 16 is used to join the (b 1 nd) silicon nitride layer 18 and the epitaxial silicon layer 丨 4b, and can reduce the stress therebetween; and the pad oxide layer 16 can also be used as a 3 1 Etching stop layer of the oxide in the process during chemical mechanical polishing (CMP) ° Production Next, please refer to FIG. 3, which defines the silicon nitride layer 18, the pad oxide layer 16, Pattern with epitaxial silicon layer 14b; for example, a patterned photoresist layer pR is formed before the surface of silicon nitride layer 18, and then, photolithography and etching processes are used, dry etching or wet etching The silicon nitride layer 18 ′, the pad oxide layer 16, and the epitaxial silicon layer 14 b are etched together with the silicon substrate 10 to form a trench 2 丨 with a depth from the surface of the substrate 2,000 to 3,000. Between A, and the remaining epitaxial layer 14b defines the outer diameter 0D (outer diameter) of the subsequently formed transistor. Please refer to FIG. 4 'after the photoresist layer pR is removed by a conventional method, an oxide layer is deposited and etched back to fill the trench 2 to form ST [area 22' then 'remove the silicon nitride layer丨 8 and the pad oxide layer 丨 6; for example, a phosphoric acid aPO4) plus a hydrogen peroxide (H2O2) solution is used to perform a thirst etching process on the silicon nitride layer 18, and then the wet etching is performed with a diluted hydrofluoric acid solution The pad oxide layer 16 ′ sequentially removes the silicon nitride layer 18 and the pad oxide layer. Next, please refer to FIG. 5, which is an active region forming element formed by the patterned epitaxial silicon layer 14 b; for example, thermal oxidation is used at 7000 to 1000 ° C. , Growing a silicon oxide layer between about 15 and 80 A thick as a subsequent transistor element
43 24 9 1 五、發明說明(8) 閘氧化層(未顯示)。接下來,利用低壓化學氣相沈積法 (LPCVD),在550~ 6 5 0 °C下沈積一層厚約1200〜300 0人之間 的複晶矽層(未顯示),之後,再次利用光學微影術與蝕刻 製程’定義一閘極24,其包括一閘氧化層241與一閘電極 242 °接著,利用LPCVD或電漿加強化學氣相沈積法 (PECVD),在6〇〇〜800°C下沈積一層厚約800〜25 00 A之間的 氧化矽層(未顯示),並利用活性離子蝕刻方式(RI E),以 CHF3為蝕刻反應氣體,蝕刻該氧化矽層以於閘極24之側壁 形成絕緣間隔物(s p a c e r) 2 6。之後,施以離子植入之步 驟;例如’以5〜40KeV的能量,lE14~lE16atoms/cm2的劑 量’植入砷離子於磊晶層1 4 b中,以形成具有淺接面之源/ >及極區28。 依據本發明之方法所形成的s〇 I電晶體由於沒有源/汲 極接面的問題’因此其耦合電容低、且較無漏電流發生。 此外’主動區域矽層的厚度容易控制、其間之晶格缺 陷較小、以及製程與習知之積體電路技術相容,因此製造 費用大為降低。 晴參看第6圖’所示係為依據本發明s〇 I電晶體之佈局 (layout);由圖中可明顯看出源/汲極28與閘極242及通道 間的關係。 一本發明的特徵在於先形成一具有開口之氧化層之後, ,、二由該開口而成長一磊晶矽層,以開口間的磊晶矽層區域 作,7L件之主動區,因而形成一s〇 1電晶體。而在美國專 利5, 882, 958號中所提到藉以成長磊晶矽層之開口則需43 24 9 1 V. Description of the invention (8) Gate oxide layer (not shown). Next, a low-pressure chemical vapor deposition (LPCVD) method was used to deposit a polycrystalline silicon layer (not shown) between 1200 and 300,000 at a temperature of 550 to 650 ° C. After that, optical microscopy was used again. The lithography and etching process defines a gate electrode 24, which includes a gate oxide layer 241 and a gate electrode 242 °. Then, LPCVD or plasma enhanced chemical vapor deposition (PECVD) is used at 600-800 ° C. A silicon oxide layer (not shown) with a thickness of about 800 to 25 00 A is deposited below, and the reactive silicon oxide is used to etch the silicon oxide layer to the gate electrode 24 by using reactive ion etching (RI E). The sidewalls form insulating spacers 2 6. After that, a step of ion implantation is performed; for example, 'arsenic ions are implanted into the epitaxial layer 1 4 b at a dose of 1 to 14 Ke16 at an energy of 5 to 40 KeV to form a source with a shallow junction / & gt And polar regions 28. The SOI transistor formed according to the method of the present invention has no problem of the source / drain junction, so its coupling capacitance is low and no leakage current occurs. In addition, the thickness of the silicon layer in the active region is easy to control, the lattice defect is small, and the manufacturing process is compatible with the conventional integrated circuit technology, so the manufacturing cost is greatly reduced. Fig. 6 is a diagram showing the layout of the transistor according to the present invention; the relationship between the source / drain 28, the gate 242, and the channel can be clearly seen from the figure. A feature of the present invention is that after forming an oxide layer with an opening, an epitaxial silicon layer is grown from the opening, and the epitaxial silicon layer area between the openings is used as the active area of the 7L piece, so that an s〇1 transistor. The openings mentioned in U.S. Patent No. 5,882,958 for growing epitaxial silicon layers require
43 24 91 五、發明說明(9) 形成於主動區内,且形成主動區之磊晶層厚度不易控制 由於通道未能完全與基板隔絕,因而並不完全可稱之為 SOI電晶體。 苐二實施例 例如是梦基板 以熱氧化法成 利用光學微影 如第7圖所示, 請參考第7圖,係於一半導體基板110 之表面形成一圖案化的介電層Π2 ;例如 長一層乳化層於發基板1 1 〇之表面。之後 術及蝕刻製程’定義該介電層11 2之圖案 其所定義出之開π係作為後續形成電晶體之通道區丨丨4, 其具有長度為w ’範圍約在l〇〇〇~2〇〇〇A之間。該通道區 114同時分隔出介電層112之靠内側區域ii8a、118b,以及 靠外侧區域1 2 0 a、1 2 0 b。 接下來,請參看第8 A圖,係形成一非晶矽層於介電層 1 1 2之表面並填滿通道區u 4 ;例如,以CVD製程,並利用 二氣矽甲烷(SiH2Cl2)或矽曱烷(SiH4)為反應物,在 500〜600 °C下沈積一非晶矽層121,且其厚度約為7〇〇A。 之後’要進行回火的步驟,例如,將矽基板11 〇送入 一純氣或真空腔室中,且其溫度在550〜650 °C下反應,以 於介電層11 2之表面形成一平坦化的磊晶矽層1 2 2與複晶矽 層124a、124b ’其厚度在500〜1〇〇〇 A之間,係如第8B圖所 不。其中’磊晶矽層1 2 2之晶格結構與其下方之矽基板11 〇 之晶格結構相同,皆為(1 〇 〇 ) ^於此方法中,介電層〗丨2上 方的磊晶矽層122與複晶矽層124a、124b之厚度幾乎與先43 24 91 V. Description of the invention (9) The thickness of the epitaxial layer formed in the active region is not easy to control. Because the channel is not completely isolated from the substrate, it can not be completely called an SOI transistor. The second embodiment is, for example, that a dream substrate is formed by thermal oxidation using optical lithography as shown in FIG. 7. Referring to FIG. 7, a patterned dielectric layer Π 2 is formed on the surface of a semiconductor substrate 110; An emulsified layer is on the surface of the hair substrate 110. Subsequent operations and etching processes 'define the pattern of the dielectric layer 11 2 and its defined opening π system is used as a channel region for subsequent formation of the transistor. It has a length w' and a range of about 1000 to 2 〇〇〇A between. The channel region 114 simultaneously separates the inner regions ii8a and 118b of the dielectric layer 112 and the outer regions 1220a and 12b. Next, referring to FIG. 8A, an amorphous silicon layer is formed on the surface of the dielectric layer 1 12 and fills the channel region u 4; for example, in a CVD process, and using two gas silicon methane (SiH2Cl2) or Silane (SiH4) is a reactant, and an amorphous silicon layer 121 is deposited at 500 ~ 600 ° C, and its thickness is about 700A. After that, a tempering step is performed. For example, the silicon substrate 11 is sent into a pure gas or vacuum chamber, and the temperature is reacted at 550 ~ 650 ° C to form a layer on the surface of the dielectric layer 11 2. The thickness of the planarized epitaxial silicon layer 1 2 2 and the polycrystalline silicon layers 124 a and 124 b ′ is between 500 and 1000 A, as shown in FIG. 8B. Among them, the lattice structure of the epitaxial silicon layer 1 2 2 is the same as that of the silicon substrate 11 〇 below, both of which are (100) ^ In this method, the epitaxial silicon above the dielectric layer 丨 2 The thickness of the layer 122 and the polycrystalline silicon layers 124a and 124b are almost the same as
Η 第12頁 ^324 9 1 五、發明說明(10) --- 所沈積的厚度相同,因此其厚度是报容易控制的。 接下來,如第9圖所示,形成一層墊氧化層126於磊晶 矽,1 22與複晶矽層1 24a、丨24b之表面,例如,利用傳統曰曰 的氧化製程或CVD製程,形成一層厚度約為1〇〇人之墊氧化 層126 ’之後,形成一蝕刻罩幕層丨28,例如是氮化矽層, 其利闬CVD法沈積於墊氧化層丨26之表面,且其厚度約為 1000A。前述之墊氧化層126係用以接合氮化矽層128與磊 晶石夕層1 2 2、複晶矽層1 2 4 a、1 2 4 b ’並可減低其間之應 力。接著’定義該氮化矽層1 2 8、墊氧化層1 2 6之圖形;例 如’先於氮化石夕層128表面形成一圖案化的光阻層pR,之 後’利用光學微影術與蝕刻製程,乾蝕刻或濕蝕刻該氮化 石夕層128、墊氧化層126(未顯示),再以氮化矽層作為蝕刻 罩幕,向下蝕刻未被氮化矽所覆蓋之複晶矽層丨24a、 1 24b,而形成一左外侧與右外側之複晶矽層丨24a,、 1 24b’ ’並定義出後續形成電晶體之外徑。 接下來,可選擇形成如第10A圖或第10B圖之結構;首 先’如第10A圖所示,在依序移除光阻層pr、氮化矽層 128、與墊氧化層126之後,為了要增加與鄰近元件間之隔 絕’在複晶矽層1 24a’與1 24b’之兩侧分別形成絕緣侧壁 層’例如以熱氧化法於複晶矽層124a,與124b’之兩侧形成 一氧化硬側壁層1 2 5。 若選擇形成第10B圖的形式,在形成了氧化矽侧壁層 1 2 5之後’則繼續向下蝕刻未被氮化矽層1 2 6所保護的複晶 矽層124a與124b及部分的矽基板1 1 〇至其深度約為12 Page 12 ^ 324 9 1 V. Description of the invention (10) --- The deposited thickness is the same, so its thickness is easy to control. Next, as shown in FIG. 9, a pad oxide layer 126 is formed on the surfaces of epitaxial silicon, 1 22 and polycrystalline silicon layers 1 24a, 24b. For example, a conventional oxidation process or a CVD process is used to form After a pad oxide layer 126 ′ having a thickness of about 100 people, an etching mask layer 28 is formed, for example, a silicon nitride layer, which is deposited on the surface of the pad oxide layer 26 by CVD, and the thickness is About 1000A. The aforementioned pad oxide layer 126 is used to join the silicon nitride layer 128 and the epitaxial stone layer 1 2 2, the polycrystalline silicon layer 1 2 4 a, 1 2 4 b ′ and reduce the stress therebetween. Then 'define the pattern of the silicon nitride layer 1 2 8 and the pad oxide layer 1 2 6; for example,' a patterned photoresist layer pR is formed before the surface of the nitride layer 128, and then 'optography and etching are used' In the manufacturing process, the nitride nitride layer 128 and the pad oxide layer 126 (not shown) are dry-etched or wet-etched, and then the silicon nitride layer is used as an etching mask to etch down the polycrystalline silicon layer not covered by the silicon nitride. 24a, 1 24b, and form a left and right outer polycrystalline silicon layer 24a, 1 24b ′ ′ and define the outer diameter of the subsequent transistor. Next, you can choose to form the structure as shown in Figure 10A or Figure 10B. First, as shown in Figure 10A, after sequentially removing the photoresist layer pr, the silicon nitride layer 128, and the pad oxide layer 126, To increase the isolation from neighboring elements, 'insulating sidewall layers are formed on both sides of the polycrystalline silicon layers 1 24a' and 1 24b ', for example, formed on both sides of the polycrystalline silicon layer 124a and 124b' by thermal oxidation. One oxidation hard sidewall layer 1 2 5. If the form shown in FIG. 10B is selected, after the silicon oxide sidewall layer 1 2 5 is formed, then the polycrystalline silicon layers 124 a and 124 b and portions of silicon that are not protected by the silicon nitride layer 1 2 6 are etched downward. Substrate 1 1 0 to a depth of approximately
第13頁 4 3 24 91 五、發明說明(π) 2000〜3000 A ’以形成一淺溝槽132,且其間填滿氧化物, 使能做好與其他元件之隔離。之後,依序移除光阻層PR、 氮化矽層1 28、與墊氧化層1 26,則形成如第1 0B圖所示之 結構。Page 13 4 3 24 91 V. Description of the invention (π) 2000 ~ 3000 A ′ to form a shallow trench 132, which is filled with oxide, so that it can be isolated from other components. Thereafter, the photoresist layer PR, the silicon nitride layer 1 28, and the pad oxide layer 1 26 are sequentially removed, and a structure shown in FIG. 10B is formed.
承接第10A圖所示之構造,請參看第11圖,先利用熱 氧化法在700〜1000 °c下,成長一層厚約15〜80A之間的氧 化發層以作為後續所形成電晶體元件之閘氧化層(未顯 示)。接下來,利用低壓化學氣相沈積法(LPCVD),在 550〜650 °C下沈積一層厚約12〇〇〜30 00 A之間的複晶矽層 (未顯示),之後,再次利用光學微影術與蝕刻製程,定義 出一閘極’其包括一閘氧化層134與一閘電極136。在此值 得注意的是’氧化矽侧壁層丨2 5係用以保護複晶矽層 12 4a、124b,使其免受蝕刻之傷害。接下來,淡摻雜離子 入複晶硬層1 24a、1 24b中以形成源/汲極之淡摻雜區域 LDD(未繪於圖中)’再利用LpcVE)或pECVD法,在6〇〇〜8〇〇 i 下沈積一層厚約800〜2500Λ之間的氧化矽層(未顯示),並 利用活性離子韻刻方式(RIE),以CHf3為蝕刻反應氣體, 钱刻該氧化石夕層以於閘極丨36之侧壁形成絕緣間隔物 (spacerM 38a、138b。之後,施以離子植入之步驟;例Following the structure shown in Figure 10A, please refer to Figure 11. First use the thermal oxidation method to grow an oxide layer between about 15 ~ 80A thick at 700 ~ 1000 ° c as the subsequent formation of the transistor element Gate oxide (not shown). Next, a low-pressure chemical vapor deposition (LPCVD) method was used to deposit a polycrystalline silicon layer (not shown) between 550 and 650 ° C (approximately 1200 to 300 A). The photolithography and etching processes define a gate electrode, which includes a gate oxide layer 134 and a gate electrode 136. It should be noted that the 'silicon oxide sidewall layer 2 5' is used to protect the polycrystalline silicon layer 12 4a, 124b from being damaged by etching. Next, lightly doped ions are implanted into the polycrystalline hard layers 1 24a, 1 24b to form a lightly doped region LDD (not shown in the figure) of the source / drain 'reusing LpcVE) or pECVD method at 600. A silicon oxide layer (not shown) with a thickness of about 800 to 2500Λ is deposited under ~ 800i, and the reactive ion gas etching method (RIE) is used to etch the oxide gas with CHf3. Insulator spacers (spacerM 38a, 138b) are formed on the side walls of the gate electrode 36. After that, an ion implantation step is performed; for example
如,以絕緣間隔物138a、138b為罩幕,濃摻雜離子於源/ 汲極之淡摻雜區域中,以形成源/汲極,其包括淡摻雜區 域140a、140b,與濃摻雜區域142a、U2b。 阳參看第1 2圖’所示係為依據本發明s〇 I電晶體之佈 局(layout ),由圖中可明顯看出源/汲極與閘極及通道間For example, using insulating spacers 138a and 138b as a mask, heavily doped ions in the lightly doped regions of the source / drain to form the source / drain, which include lightly doped regions 140a, 140b, and heavily doped regions. Areas 142a, U2b. The reference to FIG. 12 shows the layout of the SOI transistor according to the present invention. From the figure, it can be clearly seen that between the source / drain and the gate and the channel.
第14頁 4 3 24 9 1 五、發明說明(12) 的關係。 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此項技藝者,在不脫離本發明之精 神和範圍内,當可作更動與潤飾,因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Page 14 4 3 24 9 1 V. The relationship between the description of the invention (12). Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.
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