JP5284225B2 - 不揮発性半導体記憶装置とその読み出し方法 - Google Patents
不揮発性半導体記憶装置とその読み出し方法 Download PDFInfo
- Publication number
- JP5284225B2 JP5284225B2 JP2009201969A JP2009201969A JP5284225B2 JP 5284225 B2 JP5284225 B2 JP 5284225B2 JP 2009201969 A JP2009201969 A JP 2009201969A JP 2009201969 A JP2009201969 A JP 2009201969A JP 5284225 B2 JP5284225 B2 JP 5284225B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- sense amplifier
- memory cell
- read
- reference voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 230000015654 memory Effects 0.000 claims description 57
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 230000007423 decrease Effects 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Semiconductor Memories (AREA)
Description
ここで、IOは半選択セルの総電流、Icell(VREAD)は選択セルの電流、Icell(VREAD/2)は半選択セルの電流である。
Claims (5)
- 複数のワード線、複数のビット線の交点に、抵抗変化素子とダイオードからなる複数のメモリセルが配置されたメモリセルアレイと、
前記メモリセルに流れる電流と基準電圧を比較してメモリセルから読み出されたデータを検出するセンスアンプと、
前記センスアンプから出力される信号の論理値に応じて前記基準電圧を生成する制御部と、を具備し、
前記制御部は、選択されたメモリセルのデータを検出する前に、前記センスアンプにより検出された半選択状態とされた前記複数のメモリセルに接続された前記複数のビット線のうち1つのビット線に流れる電流に基づき前記基準電圧を調整することを特徴とする不揮発性半導体記憶装置。 - 前記制御部は、前記センスアンプから出力される信号の論理値に応じてデジタル信号を生成するデジタル信号生成回路と、
前記デジタル信号生成回路により生成されたデジタル信号を前記基準電圧に変換するデジタル/アナログ変換器と
を具備することを特徴とする請求項1記載の不揮発性半導体記憶装置。 - メモリセルからデータを読み出す前に、データ読み出し時における読み出し電圧の半分の電圧に前記ワード線及び前記ビット線をプリチャージし、メモリセルからデータを読み出す時、選択ビット線に前記読み出し電圧を供給し、選択ワード線に前記読み出し電圧の半分の電圧より低い電圧を供給する電圧印加手段をさらに具備することを特徴とする請求項1に記載の不揮発性半導体記憶装置。
- 前記制御部は、前記センスアンプから出力される信号の論理値に応じて前記デジタル信号をアップカウント又はダウンカウントするカウンタを具備することを特徴とする請求項2記載の不揮発性半導体記憶装置。
- データの読み出し前に、全ビット線及び全ワード線に読み出し電圧の半分の電圧を供給し、次いで、センスアンプに接続されたビット線に前記読み出し電圧を供給して全メモリセルを半選択状態に設定し、
前記半選択状態のメモリセルが接続されたビット線に流れる電流に対応した電圧と基準電圧とを比較して前記基準電圧を調整し、
データの読み出し時に、選択されたメモリセルに流れる電流に対応する電圧と調整された前記基準電圧とを比較することにより、前記選択されたメモリセルのデータを読み出すことを特徴とする不揮発性半導体記憶装置の読み出し方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009201969A JP5284225B2 (ja) | 2009-09-01 | 2009-09-01 | 不揮発性半導体記憶装置とその読み出し方法 |
US12/848,487 US8310858B2 (en) | 2009-09-01 | 2010-08-02 | Nonvolatile semiconductor memory device with no decrease in read margin and method of reading the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009201969A JP5284225B2 (ja) | 2009-09-01 | 2009-09-01 | 不揮発性半導体記憶装置とその読み出し方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011054232A JP2011054232A (ja) | 2011-03-17 |
JP5284225B2 true JP5284225B2 (ja) | 2013-09-11 |
Family
ID=43624693
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009201969A Active JP5284225B2 (ja) | 2009-09-01 | 2009-09-01 | 不揮発性半導体記憶装置とその読み出し方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8310858B2 (ja) |
JP (1) | JP5284225B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10199099B2 (en) | 2017-03-22 | 2019-02-05 | Toshiba Memory Corporation | Semiconductor memory device |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5032621B2 (ja) | 2010-03-18 | 2012-09-26 | 株式会社東芝 | 不揮発性半導体メモリ及びその製造方法 |
JP5209013B2 (ja) | 2010-09-22 | 2013-06-12 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP5306401B2 (ja) * | 2011-03-24 | 2013-10-02 | 株式会社東芝 | 抵抗変化メモリ |
JP2014010876A (ja) | 2012-07-02 | 2014-01-20 | Toshiba Corp | 半導体記憶装置 |
JP5966150B2 (ja) * | 2012-07-31 | 2016-08-10 | パナソニックIpマネジメント株式会社 | 不揮発性記憶素子の駆動方法及び不揮発性記憶装置 |
JP2014078302A (ja) | 2012-10-11 | 2014-05-01 | Panasonic Corp | クロスポイント型抵抗変化不揮発性記憶装置及びクロスポイント型抵抗変化不揮発性記憶装置の読み出し方法 |
US9224450B2 (en) * | 2013-05-08 | 2015-12-29 | International Business Machines Corporation | Reference voltage modification in a memory device |
US9245604B2 (en) | 2013-05-08 | 2016-01-26 | International Business Machines Corporation | Prioritizing refreshes in a memory device |
US9494647B1 (en) * | 2013-12-31 | 2016-11-15 | Gsi Technology, Inc. | Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects |
US9460785B2 (en) | 2014-03-06 | 2016-10-04 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
TWI688951B (zh) * | 2014-10-30 | 2020-03-21 | 日商索尼半導體解決方案公司 | 非揮發性記憶體裝置 |
WO2016137449A1 (en) * | 2015-02-24 | 2016-09-01 | Hewlett Packard Enterprise Development Lp | Determining resistance states of memristors in a crossbar array |
CN105632551B (zh) * | 2015-12-18 | 2018-09-25 | 中国科学院上海微系统与信息技术研究所 | 存储阵列、存储对象逻辑关系的存储芯片及方法 |
US9734886B1 (en) * | 2016-02-01 | 2017-08-15 | Micron Technology, Inc | Cell-based reference voltage generation |
US9859000B1 (en) * | 2016-06-17 | 2018-01-02 | Winbond Electronics Corp. | Apparatus for providing adjustable reference voltage for sensing read-out data for memory |
US9842639B1 (en) * | 2016-10-07 | 2017-12-12 | Kilopass Technology, Inc. | Systems and methods for managing read voltages in a cross-point memory array |
US10157671B1 (en) | 2017-09-12 | 2018-12-18 | Macronix International Co., Ltd. | Fast switching 3D cross-point array |
US10475510B2 (en) | 2017-12-21 | 2019-11-12 | Macronix International Co., Ltd. | Leakage compensation read method for memory device |
IT201800005084A1 (it) * | 2018-05-04 | 2019-11-04 | Dispositivo di memoria non volatile, in particolare a cambiamento di fase e relativo metodo di lettura | |
KR102504836B1 (ko) | 2018-06-15 | 2023-02-28 | 삼성전자 주식회사 | 보상 회로를 구비하는 저항성 메모리 장치 |
US11031059B2 (en) * | 2019-02-21 | 2021-06-08 | Sandisk Technologies Llc | Magnetic random-access memory with selector voltage compensation |
US11049557B2 (en) | 2019-07-19 | 2021-06-29 | Macronix International Co., Ltd. | Leakage current compensation in crossbar array |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5640343A (en) * | 1996-03-18 | 1997-06-17 | International Business Machines Corporation | Magnetic memory array using magnetic tunnel junction devices in the memory cells |
DE10010457A1 (de) * | 2000-03-03 | 2001-09-20 | Infineon Technologies Ag | Integrierter Speicher mit Speicherzellen mit magnetoresistivem Speichereffekt |
JP3800925B2 (ja) * | 2000-05-15 | 2006-07-26 | 日本電気株式会社 | 磁気ランダムアクセスメモリ回路 |
JP3812805B2 (ja) * | 2001-01-16 | 2006-08-23 | 日本電気株式会社 | トンネル磁気抵抗素子を利用した半導体記憶装置 |
US7177181B1 (en) * | 2001-03-21 | 2007-02-13 | Sandisk 3D Llc | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics |
US6597598B1 (en) * | 2002-04-30 | 2003-07-22 | Hewlett-Packard Development Company, L.P. | Resistive cross point memory arrays having a charge injection differential sense amplifier |
JP3821066B2 (ja) * | 2002-07-04 | 2006-09-13 | 日本電気株式会社 | 磁気ランダムアクセスメモリ |
US6970375B2 (en) | 2002-08-02 | 2005-11-29 | Unity Semiconductor Corporation | Providing a reference voltage to a cross point memory array |
JP2004319587A (ja) * | 2003-04-11 | 2004-11-11 | Sharp Corp | メモリセル、メモリ装置及びメモリセル製造方法 |
US6970387B2 (en) * | 2003-09-15 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | System and method for determining the value of a memory element |
KR100587694B1 (ko) | 2005-02-16 | 2006-06-08 | 삼성전자주식회사 | 리키지 전류 보상 가능한 반도체 메모리 장치 |
US7372753B1 (en) | 2006-10-19 | 2008-05-13 | Unity Semiconductor Corporation | Two-cycle sensing in a two-terminal memory array having leakage current |
JP5032621B2 (ja) | 2010-03-18 | 2012-09-26 | 株式会社東芝 | 不揮発性半導体メモリ及びその製造方法 |
JP5209013B2 (ja) | 2010-09-22 | 2013-06-12 | 株式会社東芝 | 不揮発性半導体記憶装置 |
-
2009
- 2009-09-01 JP JP2009201969A patent/JP5284225B2/ja active Active
-
2010
- 2010-08-02 US US12/848,487 patent/US8310858B2/en active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10199099B2 (en) | 2017-03-22 | 2019-02-05 | Toshiba Memory Corporation | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
US20110051495A1 (en) | 2011-03-03 |
JP2011054232A (ja) | 2011-03-17 |
US8310858B2 (en) | 2012-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5284225B2 (ja) | 不揮発性半導体記憶装置とその読み出し方法 | |
US7969798B2 (en) | Phase change memory devices and read methods using elapsed time-based read voltages | |
US8085576B2 (en) | Semiconductor memory device | |
RU2620502C2 (ru) | Запоминающее устройство на основе изменения сопротивления | |
US8811059B2 (en) | Resistive memory apparatus, layout structure, and sensing circuit thereof | |
US8315113B2 (en) | Non-volatile semiconductor memory circuit with improved resistance distribution | |
US8625326B2 (en) | Non-volatile semiconductor memory device with a resistance adjusting circuit and an operation method thereof | |
US9799385B2 (en) | Resistance change memory | |
US10297317B2 (en) | Non-volatile semiconductor memory device including clamp circuit with control transistor and amplifier circuit | |
US7668007B2 (en) | Memory system including a resistance variable memory device | |
US10102897B2 (en) | Memory device and method of operating the same | |
KR20110025331A (ko) | 라이트 드라이버를 구비한 상변화 메모리 장치 | |
US20150340087A1 (en) | Nonvolatile random access memory | |
US10811095B2 (en) | Semiconductor storage device | |
KR100944343B1 (ko) | 상 변화 메모리 장치 | |
US8149638B2 (en) | Semiconductor memory device and inspecting method of the same | |
JP2018156700A (ja) | 不揮発性半導体記憶装置 | |
JP5657876B2 (ja) | 半導体メモリ装置 | |
JP5077646B2 (ja) | 半導体記憶装置、及び、半導体記憶装置の動作方法 | |
KR20090131189A (ko) | 저항체를 이용한 비휘발성 메모리 장치 | |
JP6163817B2 (ja) | 不揮発性メモリセルおよび不揮発性メモリ | |
JP6290034B2 (ja) | 不揮発性半導体記憶装置、及びその読み出し方法 | |
KR20140080943A (ko) | 비휘발성 메모리 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110912 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130131 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130205 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130408 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130507 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130529 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5284225 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |