JP5220398B2 - 電子構造の製造方法 - Google Patents
電子構造の製造方法 Download PDFInfo
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- JP5220398B2 JP5220398B2 JP2007316113A JP2007316113A JP5220398B2 JP 5220398 B2 JP5220398 B2 JP 5220398B2 JP 2007316113 A JP2007316113 A JP 2007316113A JP 2007316113 A JP2007316113 A JP 2007316113A JP 5220398 B2 JP5220398 B2 JP 5220398B2
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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Description
(a)半導体基板を用意するステップと、
(b)半導体基板上に第1の層を形成するステップであって、第1の層は、電気絶縁性材料によって分離されたタングステンの複数の導電性領域を含むステップと、
(c)第1の層上にエッチ・ストップ層を形成するステップと、
(d)エッチ・ストップ層上に電気絶縁体層を形成するステップと、
(e)絶縁体層を通ってエッチ・ストップ層まで延びるコンタクト・ビアを、対応する導電性領域の上方に形成するステップと、
(f)コンタクト・ビアの底部のエッチ・ストップ層をエッチングして、コンタクト・ビアの下方の対応する導電性領域の最上面を露出させるステップと、
(g)コンタクト・ビアに高融点金属ライナとダマシン銅とを、コンタクト・ビア内にダマシン銅相互接続部が形成されるように充填するステップであって、ダマシン銅相互接続部を導電性領域の最上部と電気的接続状態にするステップと、を含む電子構造の製造方法を含む。
Claims (1)
- (a)半導体基板(110)を用意するステップと、
(b)前記半導体基板(110)上に第1の層(90)を形成するステップであって、前記第1の層(90)は、電気絶縁性材料(130)によって分離されたタングステンの複数の導電性領域(120)を含むステップと、
(c)前記第1の層(90)上にエッチ・ストップ層(140)を形成するステップと、
(d)前記エッチ・ストップ層(140)上に単一の電気絶縁体層(150、450)を形成するステップと、
(e)前記単一の電気絶縁体層(150、450)を通って前記エッチ・ストップ層(140)まで延びるコンタクト・ビア(910)を、対応する導電性領域(120)の上方に形成するステップと、
(f)前記単一の電気絶縁体層(150、450)の最上部をエッチングして、前記単一の電気絶縁体層(150、450)の高さ低減部分を各コンタクト・ビア(910)に隣接して残し、各コンタクト・ビアと前記絶縁体層の高さ低減部分の上方のスペースを含む連続スペース(630)を形成するステップと、
(g)前記コンタクト・ビア(910)における前記単一の電気絶縁体層(150、450)の前記高さ低減部分上に、丸みが付けられた角縁を形成するステップと、
(h)前記コンタクト・ビア(910)の底部の前記エッチ・ストップ層(140)をエッチングして、前記コンタクト・ビア(910)の下方の前記導電性領域(120)の最上面を露出させるステップと、
(i)前記コンタクト・ビア(910)における前記単一の電気絶縁層(150、450)の前記高さ低減部分とは反対側に前記半導体基板(110)に対して垂直なコンタクト側壁(830)を形成するステップと、
(j)前記コンタクト・ビア(910)に高融点金属ライナ(1110、1115)とダマシン銅(1120、1251)とを、前記コンタクト・ビア(910)内にダマシン銅相互接続部(1250)が形成されるように充填するステップであって、前記ダマシン銅相互接続部(1250)を前記導電性領域(120)の最上部と電気的接続状態にするステップとを含み、
前記導電性領域(120)の最上面を露出させるステップは、フッ化水素酸を用いて、前記コンタクト・ビア(910)の底部の前記エッチ・ストップ層(140)および前記導電性領域(120)の最上面を洗浄し、
前記丸みが付けられた角縁は、前記高さ低減部分と共に形成される、電子構造の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/816,977 US6566242B1 (en) | 2001-03-23 | 2001-03-23 | Dual damascene copper interconnect to a damascene tungsten wiring level |
US09/816,977 | 2001-03-23 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2002576013A Division JP2004532519A (ja) | 2001-03-23 | 2002-03-25 | 電子構造の製造方法 |
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Publication Number | Publication Date |
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JP2008135758A JP2008135758A (ja) | 2008-06-12 |
JP5220398B2 true JP5220398B2 (ja) | 2013-06-26 |
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Application Number | Title | Priority Date | Filing Date |
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JP2002576013A Pending JP2004532519A (ja) | 2001-03-23 | 2002-03-25 | 電子構造の製造方法 |
JP2007316113A Expired - Fee Related JP5220398B2 (ja) | 2001-03-23 | 2007-12-06 | 電子構造の製造方法 |
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JP2002576013A Pending JP2004532519A (ja) | 2001-03-23 | 2002-03-25 | 電子構造の製造方法 |
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US (2) | US6566242B1 (ja) |
JP (2) | JP2004532519A (ja) |
KR (1) | KR100530306B1 (ja) |
GB (1) | GB2391388B (ja) |
TW (1) | TW587327B (ja) |
WO (1) | WO2002078082A2 (ja) |
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- 2001-03-23 US US09/816,977 patent/US6566242B1/en not_active Expired - Lifetime
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- 2002-03-25 KR KR10-2003-7011768A patent/KR100530306B1/ko not_active IP Right Cessation
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TW587327B (en) | 2004-05-11 |
US6566242B1 (en) | 2003-05-20 |
WO2002078082A2 (en) | 2002-10-03 |
US7230336B2 (en) | 2007-06-12 |
GB2391388A (en) | 2004-02-04 |
GB2391388B (en) | 2005-10-26 |
JP2004532519A (ja) | 2004-10-21 |
KR20030086603A (ko) | 2003-11-10 |
WO2002078082A3 (en) | 2003-02-27 |
JP2008135758A (ja) | 2008-06-12 |
GB0322556D0 (en) | 2003-10-29 |
US20030232494A1 (en) | 2003-12-18 |
KR100530306B1 (ko) | 2005-11-22 |
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