JP5165287B2 - 配線構造およびその製造方法 - Google Patents
配線構造およびその製造方法 Download PDFInfo
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- JP5165287B2 JP5165287B2 JP2007168588A JP2007168588A JP5165287B2 JP 5165287 B2 JP5165287 B2 JP 5165287B2 JP 2007168588 A JP2007168588 A JP 2007168588A JP 2007168588 A JP2007168588 A JP 2007168588A JP 5165287 B2 JP5165287 B2 JP 5165287B2
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- Prior art keywords
- wiring
- opening
- insulating film
- forming
- interlayer insulating
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000011229 interlayer Substances 0.000 claims description 52
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 35
- 239000004065 semiconductor Substances 0.000 description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 229910016570 AlCu Inorganic materials 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000009413 insulation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53219—Aluminium alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
4 層間絶縁膜(第1層間絶縁膜)
4a ビア(第1開口部)
4b ビア(第3開口部)
5a プラグ(第1接続部、接続部)
5b プラグ(第2接続部、接続部)
6 配線(第2配線)
6a 凹部(第1凹部)
7 層間絶縁膜(第2層間絶縁膜)
7a ビア(第2開口部)
7b 内側面
7c 上端部近傍
8 配線(第3配線)
51a 凹部(第2凹部)
100 配線構造
Claims (3)
- 第1配線と、
前記第1配線上に形成されるとともに、第1開口部を有する第1層間絶縁膜と、
前記第1層間絶縁膜を覆うように形成されるとともに、前記第1開口部と対応する領域に第1凹部が形成された第2配線と、
前記第2配線を覆うように形成されるとともに、第2開口部を有する第2層間絶縁膜と、
前記第2層間絶縁膜を覆うように形成された第3配線と、
前記第1配線と前記第2配線とを電気的に接続するために設けられた接続部とを備え、
前記第2開口部の内側面は、前記第1凹部と対応する領域に配置されるとともに、上端部近傍の開口幅が下方から上方に向かって大きくなるような形状に形成されており、
前記接続部は、第1開口部の内部に形成されるとともに、第2凹部を有する第1接続部を含み、
前記第1凹部は、前記第2凹部と対応する領域に形成されており、
前記第1層間絶縁膜は、前記第1開口部の幅よりも小さい幅を有する第3開口部をさらに含み、
前記接続部は、前記第3開口部の内部全体に充填された第2接続部を含み、
前記第1開口部が、前記第2開口部の周縁部に設けられ、前記第3開口部が、前記第2開口部の内部に設けられている、配線構造。 - 前記第1開口部は、平面的に見て環状に形成されており、
前記第1凹部は、平面的に見て環状に形成されている、請求項1に記載の配線構造。 - 第1配線を形成する工程と、
前記第1配線上に第1層間絶縁膜を形成するとともに、前記第1層間絶縁膜に第1開口部を形成する工程と、
前記第1層間絶縁膜を覆うとともに、前記第1開口部と対応する領域に第1凹部が設けられるように第2配線を形成する工程と、
前記第2配線を覆うとともに、前記第1凹部と対応する領域に窪んだ領域が設けられるように第2層間絶縁膜を形成する工程と、
前記第2層間絶縁膜の前記窪んだ領域の一部を含む領域を除去することによって、内側面が前記第1凹部と対応する領域に配置されるとともに、前記内側面の上端部近傍の開口幅が下方から上方に向かって大きくなるような形状を有する第2開口部を形成する工程と、
前記第2層間絶縁膜を覆うように第3配線を形成する工程と、
前記第1開口部を形成する工程と、前記第2配線を形成する工程との間に、前記第1配線と前記第2配線とを電気的に接続するための接続部を形成する工程とを備え、
前記接続部を形成する工程は、前記第1開口部の内部に第2凹部を有する第1接続部を形成する工程を含み、
前記第1層間絶縁膜に第1開口部を形成する工程は、前記第1層間絶縁膜に前記第1開口部の幅よりも小さい幅を有する第3開口部を形成する工程を含み、
前記接続部を形成する工程は、前記第3開口部の内部全体に第2接続部を充填する工程を含み、
前記第1開口部を形成する工程は、前記第1開口部を前記第2開口部の周縁部に形成する工程を含み、前記第3開口部を形成する工程は、前記第3開口部を前記第2開口部の内部に形成する工程を含む、配線構造の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007168588A JP5165287B2 (ja) | 2007-06-27 | 2007-06-27 | 配線構造およびその製造方法 |
US12/147,122 US7851917B2 (en) | 2007-06-27 | 2008-06-26 | Wiring structure and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007168588A JP5165287B2 (ja) | 2007-06-27 | 2007-06-27 | 配線構造およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009010083A JP2009010083A (ja) | 2009-01-15 |
JP5165287B2 true JP5165287B2 (ja) | 2013-03-21 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007168588A Active JP5165287B2 (ja) | 2007-06-27 | 2007-06-27 | 配線構造およびその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7851917B2 (ja) |
JP (1) | JP5165287B2 (ja) |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05190686A (ja) * | 1992-01-08 | 1993-07-30 | Seiko Epson Corp | 半導体装置 |
JPH0684788A (ja) | 1992-09-01 | 1994-03-25 | Clarion Co Ltd | 半導体装置及びその製造方法 |
JP3401805B2 (ja) * | 1992-10-31 | 2003-04-28 | ソニー株式会社 | Al系材料配線構造、半導体装置、及び配線構造形成方法 |
JPH09172017A (ja) | 1995-10-18 | 1997-06-30 | Ricoh Co Ltd | 半導体装置の製造方法 |
US5933756A (en) * | 1995-10-18 | 1999-08-03 | Ricoh Company, Ltd. | Fabrication process of a semiconductor device having a multilayered interconnection structure |
US6291848B1 (en) * | 1999-01-13 | 2001-09-18 | Agere Systems Guardian Corp. | Integrated circuit capacitor including anchored plugs |
US6221780B1 (en) * | 1999-09-29 | 2001-04-24 | International Business Machines Corporation | Dual damascene flowable oxide insulation structure and metallic barrier |
US7186648B1 (en) * | 2001-03-13 | 2007-03-06 | Novellus Systems, Inc. | Barrier first method for single damascene trench applications |
US6566242B1 (en) * | 2001-03-23 | 2003-05-20 | International Business Machines Corporation | Dual damascene copper interconnect to a damascene tungsten wiring level |
US6930038B2 (en) * | 2001-05-23 | 2005-08-16 | United Microelectronics Corp. | Dual damascene partial gap fill polymer fabrication process |
US6794293B2 (en) * | 2001-10-05 | 2004-09-21 | Lam Research Corporation | Trench etch process for low-k dielectrics |
JP2003107721A (ja) | 2001-09-28 | 2003-04-09 | Nikon Corp | マイクロレンズの製造方法、物品の製造方法、レジスト層の加工方法、および、マイクロレンズ |
US6806579B2 (en) * | 2003-02-11 | 2004-10-19 | Infineon Technologies Ag | Robust via structure and method |
US7026714B2 (en) * | 2003-03-18 | 2006-04-11 | Cunningham James A | Copper interconnect systems which use conductive, metal-based cap layers |
JP2005116756A (ja) * | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20060024953A1 (en) * | 2004-07-29 | 2006-02-02 | Papa Rao Satyavolu S | Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess |
US20060024958A1 (en) * | 2004-07-29 | 2006-02-02 | Abbas Ali | HSQ/SOG dry strip process |
US7470929B2 (en) * | 2006-07-24 | 2008-12-30 | International Business Machines Corporation | Fuse/anti-fuse structure and methods of making and programming same |
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2007
- 2007-06-27 JP JP2007168588A patent/JP5165287B2/ja active Active
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2008
- 2008-06-26 US US12/147,122 patent/US7851917B2/en active Active
Also Published As
Publication number | Publication date |
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JP2009010083A (ja) | 2009-01-15 |
US7851917B2 (en) | 2010-12-14 |
US20090001590A1 (en) | 2009-01-01 |
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